Initial project setup
This commit is contained in:
@@ -0,0 +1,150 @@
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/*
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* FreeRTOS Kernel V10.0.0
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* Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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||||
*
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||||
* Permission is hereby granted, free of charge, to any person obtaining a copy of
|
||||
* this software and associated documentation files (the "Software"), to deal in
|
||||
* the Software without restriction, including without limitation the rights to
|
||||
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
|
||||
* the Software, and to permit persons to whom the Software is furnished to do so,
|
||||
* subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in all
|
||||
* copies or substantial portions of the Software. If you wish to use our Amazon
|
||||
* FreeRTOS name, please do so in a fair use way that does not cause confusion.
|
||||
*
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||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
|
||||
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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||||
*
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||||
* http://www.FreeRTOS.org
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* http://aws.amazon.com/freertos
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||||
*
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* 1 tab == 4 spaces!
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*/
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#ifndef FREERTOS_CONFIG_H
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#define FREERTOS_CONFIG_H
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/*-----------------------------------------------------------
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* Application specific definitions.
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*
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||||
* These definitions should be adjusted for your particular hardware and
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* application requirements.
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*
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* THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
|
||||
* FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
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*
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* See http://www.freertos.org/a00110.html.
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*----------------------------------------------------------*/
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// skip if included from IAR assembler
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#ifndef __IASMARM__
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#include "stm32n6xx.h"
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#endif
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/* Cortex M55 port configuration. */
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#define configENABLE_MVE 0
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#define configENABLE_MPU 0
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#define configENABLE_FPU 1
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#define configENABLE_TRUSTZONE 0
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#define configMINIMAL_SECURE_STACK_SIZE (1024)
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#define configUSE_PREEMPTION 1
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#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
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#define configCPU_CLOCK_HZ SystemCoreClock
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#define configTICK_RATE_HZ ( 1000 )
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#define configMAX_PRIORITIES ( 5 )
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#define configMINIMAL_STACK_SIZE ( 128 )
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#define configTOTAL_HEAP_SIZE ( configSUPPORT_DYNAMIC_ALLOCATION*8*1024 )
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#define configMAX_TASK_NAME_LEN 16
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#define configUSE_16_BIT_TICKS 0
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#define configIDLE_SHOULD_YIELD 1
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#define configUSE_MUTEXES 1
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#define configUSE_RECURSIVE_MUTEXES 1
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#define configUSE_COUNTING_SEMAPHORES 1
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#define configQUEUE_REGISTRY_SIZE 4
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#define configUSE_QUEUE_SETS 0
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#define configUSE_TIME_SLICING 0
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#define configUSE_NEWLIB_REENTRANT 0
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#define configENABLE_BACKWARD_COMPATIBILITY 1
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#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0
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#define configSUPPORT_STATIC_ALLOCATION 1
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#define configSUPPORT_DYNAMIC_ALLOCATION 0
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/* Hook function related definitions. */
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#define configUSE_IDLE_HOOK 0
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#define configUSE_TICK_HOOK 0
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#define configUSE_MALLOC_FAILED_HOOK 0 // cause nested extern warning
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#define configCHECK_FOR_STACK_OVERFLOW 2
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#define configCHECK_HANDLER_INSTALLATION 0
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/* Run time and task stats gathering related definitions. */
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#define configGENERATE_RUN_TIME_STATS 0
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#define configRECORD_STACK_HIGH_ADDRESS 1
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#define configUSE_TRACE_FACILITY 1 // legacy trace
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#define configUSE_STATS_FORMATTING_FUNCTIONS 0
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/* Co-routine definitions. */
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#define configUSE_CO_ROUTINES 0
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#define configMAX_CO_ROUTINE_PRIORITIES 2
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/* Software timer related definitions. */
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#define configUSE_TIMERS 1
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#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES-2)
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#define configTIMER_QUEUE_LENGTH 32
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#define configTIMER_TASK_STACK_DEPTH configMINIMAL_STACK_SIZE
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/* Optional functions - most linkers will remove unused functions anyway. */
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#define INCLUDE_vTaskPrioritySet 0
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#define INCLUDE_uxTaskPriorityGet 0
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#define INCLUDE_vTaskDelete 0
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#define INCLUDE_vTaskSuspend 1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
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#define INCLUDE_xResumeFromISR 0
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#define INCLUDE_vTaskDelayUntil 1
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#define INCLUDE_vTaskDelay 1
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#define INCLUDE_xTaskGetSchedulerState 0
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#define INCLUDE_xTaskGetCurrentTaskHandle 1
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#define INCLUDE_uxTaskGetStackHighWaterMark 0
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#define INCLUDE_xTaskGetIdleTaskHandle 0
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#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
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#define INCLUDE_pcTaskGetTaskName 0
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#define INCLUDE_eTaskGetState 0
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#define INCLUDE_xEventGroupSetBitFromISR 0
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#define INCLUDE_xTimerPendFunctionCall 0
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/* FreeRTOS hooks to NVIC vectors */
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#define xPortPendSVHandler PendSV_Handler
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#define xPortSysTickHandler SysTick_Handler
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#define vPortSVCHandler SVC_Handler
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//--------------------------------------------------------------------+
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// Interrupt nesting behavior configuration.
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//--------------------------------------------------------------------+
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// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
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#define configPRIO_BITS 4
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/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
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#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1<<configPRIO_BITS) - 1)
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/* The highest interrupt priority that can be used by any interrupt service
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routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL
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INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
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PRIORITY THAN THIS! (higher priorities are lower numeric values. */
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#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 2
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/* Interrupt priorities used by the kernel port layer itself. These are generic
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to all Cortex-M ports, and do not rely on any particular library functions. */
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#define configKERNEL_INTERRUPT_PRIORITY ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
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/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
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See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
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#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
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#endif
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@@ -0,0 +1,203 @@
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/*
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||||
******************************************************************************
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||||
**
|
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** @file : STM32N657XX_AXISRAM2_fsbl.ld
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**
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||||
** @author : GPM Application Team
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||||
**
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** @brief : Linker script for STM32N657XX Device from STM32N6 series
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** 512 KBytes RAM
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**
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** Set heap size, stack size and stack location according
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** to application requirements.
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||||
**
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||||
** Set memory bank area and size if external memory is used
|
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**
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||||
** Target : STMicroelectronics STM32
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||||
**
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||||
** Distribution: The file is distributed as is, without any warranty
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||||
** of any kind.
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||||
**
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||||
******************************************************************************
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** @attention
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**
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||||
** Copyright (c) 2023 STMicroelectronics.
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** All rights reserved.
|
||||
**
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||||
** This software is licensed under terms that can be found in the LICENSE file
|
||||
** in the root directory of this software component.
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||||
** If no LICENSE file comes with this software, it is provided AS-IS.
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||||
**
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||||
******************************************************************************
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*/
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/* Entry Point */
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ENTRY(Reset_Handler)
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/* Highest address of the user mode stack */
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_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
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_sstack = _estack - _Min_Stack_Size;
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_Min_Heap_Size = 0x200; /* required amount of heap */
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_Min_Stack_Size = 0x800; /* required amount of stack */
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/* Memories definition */
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MEMORY
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{
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ROM (xrw) : ORIGIN = 0x34180400, LENGTH = 255K
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RAM (xrw) : ORIGIN = 0x341C0000, LENGTH = 256K
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}
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/* Sections */
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SECTIONS
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{
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/* The startup code into "RAM" Ram type memory */
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.isr_vector :
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{
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. = ALIGN(4);
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KEEP(*(.isr_vector)) /* Startup code */
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. = ALIGN(4);
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} >ROM
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/* The program code and other data into "RAM" Ram type memory */
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.text :
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{
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. = ALIGN(4);
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*(.text) /* .text sections (code) */
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*(.text*) /* .text* sections (code) */
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*(.glue_7) /* glue arm to thumb code */
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*(.glue_7t) /* glue thumb to arm code */
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*(.eh_frame)
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*(.RamFunc) /* .RamFunc sections */
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*(.RamFunc*) /* .RamFunc* sections */
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KEEP (*(.init))
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KEEP (*(.fini))
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. = ALIGN(4);
|
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_etext = .; /* define a global symbols at end of code */
|
||||
} >ROM
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/* Constant data into "RAM" Ram type memory */
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.rodata :
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{
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. = ALIGN(4);
|
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*(.rodata) /* .rodata sections (constants, strings, etc.) */
|
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*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
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. = ALIGN(4);
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} >ROM
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||||
|
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.ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
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{
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. = ALIGN(4);
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*(.ARM.extab* .gnu.linkonce.armextab.*)
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. = ALIGN(4);
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} >ROM
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||||
.ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
|
||||
{
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||||
. = ALIGN(4);
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||||
__exidx_start = .;
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*(.ARM.exidx*)
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__exidx_end = .;
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||||
. = ALIGN(4);
|
||||
} >ROM
|
||||
|
||||
.preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
|
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{
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. = ALIGN(4);
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||||
PROVIDE_HIDDEN (__preinit_array_start = .);
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KEEP (*(.preinit_array*))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
. = ALIGN(4);
|
||||
} >ROM
|
||||
|
||||
.init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
|
||||
{
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||||
. = ALIGN(4);
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array*))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
. = ALIGN(4);
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||||
} >ROM
|
||||
|
||||
.fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
KEEP (*(.fini_array*))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
. = ALIGN(4);
|
||||
} >ROM
|
||||
|
||||
/* Used by the startup to initialize data */
|
||||
_sidata = LOADADDR(.data);
|
||||
|
||||
/* Initialized data sections into "RAM" Ram type memory */
|
||||
.data :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sdata = .; /* create a global symbol at data start */
|
||||
*(.data) /* .data sections */
|
||||
*(.data*) /* .data* sections */
|
||||
|
||||
. = ALIGN(4);
|
||||
_edata = .; /* define a global symbol at data end */
|
||||
|
||||
} >RAM AT> ROM
|
||||
|
||||
.noncacheable :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
__snoncacheable = .;/* create symbol for start of section */
|
||||
KEEP(*(.noncacheable))
|
||||
. = ALIGN(8);
|
||||
__enoncacheable = .; /* create symbol for end of section */
|
||||
} > RAM
|
||||
|
||||
|
||||
.gnu.sgstubs :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.gnu.sgstubs*) /* Secure Gateway stubs */
|
||||
. = ALIGN(4);
|
||||
} >ROM
|
||||
/* Uninitialized data section into "RAM" Ram type memory */
|
||||
. = ALIGN(4);
|
||||
.bss :
|
||||
{
|
||||
/* This is used by the startup in order to initialize the .bss section */
|
||||
_sbss = .; /* define a global symbol at bss start */
|
||||
__bss_start__ = _sbss;
|
||||
*(.bss)
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
|
||||
. = ALIGN(4);
|
||||
_ebss = .; /* define a global symbol at bss end */
|
||||
__bss_end__ = _ebss;
|
||||
} >RAM
|
||||
|
||||
/* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
|
||||
._user_heap_stack :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
PROVIDE ( end = . );
|
||||
PROVIDE ( _end = . );
|
||||
. = . + _Min_Heap_Size;
|
||||
. = . + _Min_Stack_Size;
|
||||
. = ALIGN(8);
|
||||
} >RAM
|
||||
|
||||
/* Remove information from the compiler libraries */
|
||||
/DISCARD/ :
|
||||
{
|
||||
libc.a ( * )
|
||||
libm.a ( * )
|
||||
libgcc.a ( * )
|
||||
}
|
||||
|
||||
.ARM.attributes 0 : { *(.ARM.attributes) }
|
||||
}
|
||||
@@ -0,0 +1,17 @@
|
||||
set(MCU_VARIANT stm32n657xx)
|
||||
set(JLINK_DEVICE stm32n6xx)
|
||||
|
||||
set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32N657XX_AXISRAM2_fsbl.ld)
|
||||
|
||||
function(update_board TARGET)
|
||||
target_compile_definitions(${TARGET} PUBLIC
|
||||
STM32N657xx
|
||||
)
|
||||
target_sources(${TARGET} PUBLIC
|
||||
${ST_TCPP0203}/tcpp0203.c
|
||||
${ST_TCPP0203}/tcpp0203_reg.c
|
||||
)
|
||||
target_include_directories(${TARGET} PUBLIC
|
||||
${ST_TCPP0203}
|
||||
)
|
||||
endfunction()
|
||||
@@ -0,0 +1,283 @@
|
||||
/*
|
||||
* The MIT License (MIT)
|
||||
*
|
||||
* Copyright (c) 2021, Ha Thach (tinyusb.org)
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
* THE SOFTWARE.
|
||||
*
|
||||
* This file is part of the TinyUSB stack.
|
||||
*/
|
||||
|
||||
/* metadata:
|
||||
name: STM32 N6570-DK
|
||||
url: https://www.st.com/en/evaluation-tools/stm32n6570-dk.html
|
||||
*/
|
||||
|
||||
#ifndef BOARD_H_
|
||||
#define BOARD_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "stm32n657xx.h"
|
||||
#include "stm32n6xx_ll_exti.h"
|
||||
#include "stm32n6xx_ll_system.h"
|
||||
#include "tcpp0203.h"
|
||||
|
||||
#define UART_DEV USART1
|
||||
#define UART_CLK_EN __HAL_RCC_USART1_CLK_ENABLE
|
||||
|
||||
#define BOARD_TUD_RHPORT 1
|
||||
|
||||
// VBUS Sense detection
|
||||
#define OTG_FS_VBUS_SENSE 1
|
||||
#define OTG_HS_VBUS_SENSE 1
|
||||
|
||||
#define PINID_LED 0
|
||||
#define PINID_BUTTON 1
|
||||
#define PINID_UART_TX 2
|
||||
#define PINID_UART_RX 3
|
||||
#define PINID_TCPP0203_EN 4
|
||||
|
||||
static board_pindef_t board_pindef[] = {
|
||||
{// LED
|
||||
.port = GPIOG,
|
||||
.pin_init = {.Pin = GPIO_PIN_10, .Mode = GPIO_MODE_OUTPUT_PP, .Pull = GPIO_PULLDOWN, .Speed = GPIO_SPEED_FREQ_HIGH, .Alternate = 0},
|
||||
.active_state = 1},
|
||||
{// Button
|
||||
.port = GPIOC,
|
||||
.pin_init = {.Pin = GPIO_PIN_13, .Mode = GPIO_MODE_INPUT, .Pull = GPIO_PULLDOWN, .Speed = GPIO_SPEED_FREQ_HIGH, .Alternate = 0},
|
||||
.active_state = 1},
|
||||
{// UART TX
|
||||
.port = GPIOE,
|
||||
.pin_init = {.Pin = GPIO_PIN_5, .Mode = GPIO_MODE_AF_PP, .Pull = GPIO_NOPULL, .Speed = GPIO_SPEED_FREQ_LOW, .Alternate = GPIO_AF7_USART1},
|
||||
.active_state = 0},
|
||||
{// UART RX
|
||||
.port = GPIOE,
|
||||
.pin_init = {.Pin = GPIO_PIN_6, .Mode = GPIO_MODE_AF_PP, .Pull = GPIO_NOPULL, .Speed = GPIO_SPEED_FREQ_LOW, .Alternate = GPIO_AF7_USART1},
|
||||
.active_state = 0},
|
||||
{// VBUS input pin used for TCPP0203 EN
|
||||
.port = GPIOA,
|
||||
.pin_init = {.Pin = GPIO_PIN_4, .Mode = GPIO_MODE_OUTPUT_PP, .Pull = GPIO_PULLDOWN, .Speed = GPIO_SPEED_FREQ_HIGH, .Alternate = 0},
|
||||
.active_state = 0},
|
||||
{
|
||||
// I2C SCL for TCPP0203
|
||||
.port = GPIOD,
|
||||
.pin_init = {.Pin = GPIO_PIN_14, .Mode = GPIO_MODE_AF_OD, .Pull = GPIO_NOPULL, .Speed = GPIO_SPEED_FREQ_LOW, .Alternate = GPIO_AF4_I2C2},
|
||||
},
|
||||
{
|
||||
// I2C SDA for TCPP0203
|
||||
.port = GPIOD,
|
||||
.pin_init = {.Pin = GPIO_PIN_4, .Mode = GPIO_MODE_AF_OD, .Pull = GPIO_NOPULL, .Speed = GPIO_SPEED_FREQ_LOW, .Alternate = GPIO_AF4_I2C2},
|
||||
},
|
||||
{
|
||||
// INT for TCPP0203
|
||||
.port = GPIOD,
|
||||
.pin_init = {.Pin = GPIO_PIN_10, .Mode = GPIO_MODE_IT_FALLING, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_FREQ_HIGH, .Alternate = 0},
|
||||
},
|
||||
};
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// RCC Clock
|
||||
//--------------------------------------------------------------------+
|
||||
void SystemClock_Config(void) {
|
||||
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
|
||||
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
|
||||
/* Configure the power domain */
|
||||
if (HAL_PWREx_ConfigSupply(PWR_EXTERNAL_SOURCE_SUPPLY) != HAL_OK) {
|
||||
Error_Handler();
|
||||
}
|
||||
|
||||
/* Get current CPU/System buses clocks configuration */
|
||||
/* and if necessary switch to intermediate HSI clock */
|
||||
/* to ensure target clock can be set */
|
||||
HAL_RCC_GetClockConfig(&RCC_ClkInitStruct);
|
||||
if ((RCC_ClkInitStruct.CPUCLKSource == RCC_CPUCLKSOURCE_IC1) ||
|
||||
(RCC_ClkInitStruct.SYSCLKSource == RCC_SYSCLKSOURCE_IC2_IC6_IC11)) {
|
||||
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_CPUCLK | RCC_CLOCKTYPE_SYSCLK);
|
||||
RCC_ClkInitStruct.CPUCLKSource = RCC_CPUCLKSOURCE_HSI;
|
||||
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
|
||||
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct) != HAL_OK) {
|
||||
Error_Handler();
|
||||
}
|
||||
}
|
||||
|
||||
/* HSE selected as source (stable clock on Level 0 samples */
|
||||
/* PLL1 output = ((HSE/PLLM)*PLLN)/PLLP1/PLLP2 */
|
||||
/* = ((48000000/3)*75)/1/1 */
|
||||
/* = (16000000*75)/1/1 */
|
||||
/* = 1200000000 (1200 MHz) */
|
||||
/* PLL2 off */
|
||||
/* PLL3 off */
|
||||
/* PLL4 off */
|
||||
|
||||
/* Enable HSE && HSI */
|
||||
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
|
||||
RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
|
||||
RCC_OscInitStruct.HSIDiv = RCC_HSI_DIV1;
|
||||
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
|
||||
RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* 48 MHz */
|
||||
|
||||
RCC_OscInitStruct.PLL1.PLLState = RCC_PLL_ON;
|
||||
RCC_OscInitStruct.PLL1.PLLSource = RCC_PLLSOURCE_HSE;
|
||||
RCC_OscInitStruct.PLL1.PLLM = 3;
|
||||
RCC_OscInitStruct.PLL1.PLLN = 75; /* PLL1 VCO = 48/3 * 75 = 1200MHz */
|
||||
RCC_OscInitStruct.PLL1.PLLP1 = 1; /* PLL output = PLL VCO frequency / (PLLP1 * PLLP2) */
|
||||
RCC_OscInitStruct.PLL1.PLLP2 = 1; /* PLL output = 1200 MHz */
|
||||
RCC_OscInitStruct.PLL1.PLLFractional = 0;
|
||||
|
||||
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
|
||||
/* Initialization error */
|
||||
Error_Handler();
|
||||
}
|
||||
|
||||
/* Select PLL1 outputs as CPU and System bus clock source */
|
||||
/* CPUCLK = ic1_ck = PLL1 output/ic1_divider = 600 MHz */
|
||||
/* SYSCLK = ic2_ck = PLL1 output/ic2_divider = 400 MHz */
|
||||
/* Configure the HCLK clock divider */
|
||||
/* HCLK = PLL1 SYSCLK/HCLK divider = 200 MHz */
|
||||
/* PCLKx = HCLK / PCLKx divider = 200 MHz */
|
||||
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_CPUCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK |
|
||||
RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_PCLK4 | RCC_CLOCKTYPE_PCLK5);
|
||||
RCC_ClkInitStruct.CPUCLKSource = RCC_CPUCLKSOURCE_IC1;
|
||||
RCC_ClkInitStruct.IC1Selection.ClockSelection = RCC_ICCLKSOURCE_PLL1;
|
||||
RCC_ClkInitStruct.IC1Selection.ClockDivider = 2;
|
||||
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_IC2_IC6_IC11;
|
||||
RCC_ClkInitStruct.IC2Selection.ClockSelection = RCC_ICCLKSOURCE_PLL1;
|
||||
RCC_ClkInitStruct.IC2Selection.ClockDivider = 3;
|
||||
RCC_ClkInitStruct.IC6Selection.ClockSelection = RCC_ICCLKSOURCE_PLL1;
|
||||
RCC_ClkInitStruct.IC6Selection.ClockDivider = 3;
|
||||
RCC_ClkInitStruct.IC11Selection.ClockSelection = RCC_ICCLKSOURCE_PLL1;
|
||||
RCC_ClkInitStruct.IC11Selection.ClockDivider = 3;
|
||||
RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2;
|
||||
RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV1;
|
||||
RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV1;
|
||||
RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV1;
|
||||
RCC_ClkInitStruct.APB5CLKDivider = RCC_APB5_DIV1;
|
||||
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct) != HAL_OK) {
|
||||
/* Initialization Error */
|
||||
Error_Handler();
|
||||
}
|
||||
|
||||
/** Initializes the peripherals clock
|
||||
*/
|
||||
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
|
||||
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USBOTGHS1;
|
||||
PeriphClkInitStruct.UsbOtgHs1ClockSelection = RCC_USBPHY1REFCLKSOURCE_HSE_DIRECT;
|
||||
|
||||
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
|
||||
/* Initialization Error */
|
||||
Error_Handler();
|
||||
}
|
||||
|
||||
/** Set USB OTG HS PHY1 Reference Clock Source */
|
||||
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USBPHY1;
|
||||
PeriphClkInitStruct.UsbPhy1ClockSelection = RCC_USBPHY1REFCLKSOURCE_HSE_DIRECT;
|
||||
|
||||
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
|
||||
/* Initialization Error */
|
||||
Error_Handler();
|
||||
}
|
||||
}
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// USB PD
|
||||
//--------------------------------------------------------------------+
|
||||
static I2C_HandleTypeDef i2c_handle = {
|
||||
.Instance = I2C2,
|
||||
.Init = {
|
||||
.Timing = 0x20C0EDFF,
|
||||
.OwnAddress1 = 0,
|
||||
.AddressingMode = I2C_ADDRESSINGMODE_7BIT,
|
||||
.DualAddressMode = I2C_DUALADDRESS_DISABLE,
|
||||
.OwnAddress2 = 0,
|
||||
.OwnAddress2Masks = I2C_OA2_NOMASK,
|
||||
.GeneralCallMode = I2C_GENERALCALL_DISABLE,
|
||||
.NoStretchMode = I2C_NOSTRETCH_DISABLE,
|
||||
}};
|
||||
static TCPP0203_Object_t tcpp0203_obj = {0};
|
||||
|
||||
int32_t board_tcpp0203_init(void) {
|
||||
board_pindef_t *pindef = &board_pindef[PINID_TCPP0203_EN];
|
||||
HAL_GPIO_WritePin(pindef->port, pindef->pin_init.Pin, GPIO_PIN_SET);
|
||||
|
||||
__HAL_RCC_I2C2_CLK_ENABLE();
|
||||
__HAL_RCC_I2C2_FORCE_RESET();
|
||||
__HAL_RCC_I2C2_RELEASE_RESET();
|
||||
if (HAL_I2C_Init(&i2c_handle) != HAL_OK) {
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
NVIC_SetPriority(EXTI10_IRQn, 12);
|
||||
NVIC_EnableIRQ(EXTI10_IRQn);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int32_t board_tcpp0203_deinit(void) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
int32_t i2c_readreg(uint16_t DevAddr, uint16_t Reg, uint8_t *pData, uint16_t Length) {
|
||||
TU_ASSERT(HAL_OK == HAL_I2C_Mem_Read(&i2c_handle, DevAddr, Reg, I2C_MEMADD_SIZE_8BIT, pData, Length, 10000));
|
||||
return 0;
|
||||
}
|
||||
|
||||
int32_t i2c_writereg(uint16_t DevAddr, uint16_t Reg, uint8_t *pData, uint16_t Length) {
|
||||
TU_ASSERT(HAL_OK == HAL_I2C_Mem_Write(&i2c_handle, DevAddr, Reg, I2C_MEMADD_SIZE_8BIT, pData, Length, 10000));
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline void board_init2(void) {
|
||||
TCPP0203_IO_t io_ctx;
|
||||
|
||||
io_ctx.Address = TCPP0203_I2C_ADDRESS_X68;
|
||||
io_ctx.Init = board_tcpp0203_init;
|
||||
io_ctx.DeInit = board_tcpp0203_deinit;
|
||||
io_ctx.ReadReg = i2c_readreg;
|
||||
io_ctx.WriteReg = i2c_writereg;
|
||||
|
||||
TU_ASSERT(TCPP0203_RegisterBusIO(&tcpp0203_obj, &io_ctx) == TCPP0203_OK, );
|
||||
|
||||
TU_ASSERT(TCPP0203_Init(&tcpp0203_obj) == TCPP0203_OK, );
|
||||
|
||||
TU_ASSERT(TCPP0203_SetPowerMode(&tcpp0203_obj, TCPP0203_POWER_MODE_NORMAL) == TCPP0203_OK, );
|
||||
}
|
||||
|
||||
void board_vbus_set(uint8_t rhport, bool state) {
|
||||
(void) state;
|
||||
if (rhport == 1) {
|
||||
TU_ASSERT(TCPP0203_SetGateDriverProvider(&tcpp0203_obj, TCPP0203_GD_PROVIDER_SWITCH_CLOSED) == TCPP0203_OK, );
|
||||
}
|
||||
}
|
||||
|
||||
void EXTI10_IRQHandler(void) {
|
||||
__HAL_GPIO_EXTI_CLEAR_IT(GPIO_PIN_10);
|
||||
if (tcpp0203_obj.IsInitialized) {
|
||||
TU_ASSERT(TCPP0203_SetPowerMode(&tcpp0203_obj, TCPP0203_POWER_MODE_NORMAL) == TCPP0203_OK, );
|
||||
TU_ASSERT(TCPP0203_SetGateDriverProvider(&tcpp0203_obj, TCPP0203_GD_PROVIDER_SWITCH_CLOSED) == TCPP0203_OK, );
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,17 @@
|
||||
MCU_VARIANT = stm32n657xx
|
||||
CFLAGS += -DSTM32N657xx
|
||||
JLINK_DEVICE = stm32n6xx
|
||||
|
||||
LD_FILE_GCC = $(BOARD_PATH)/STM32N657XX_AXISRAM2_fsbl.ld
|
||||
|
||||
# flash target using on-board stlink
|
||||
flash: flash-stlink
|
||||
|
||||
PORT = 1
|
||||
|
||||
SRC_C += \
|
||||
$(ST_TCPP0203)/tcpp0203.c \
|
||||
$(ST_TCPP0203)/tcpp0203_reg.c \
|
||||
|
||||
INC += \
|
||||
$(TOP)/$(ST_TCPP0203) \
|
||||
@@ -0,0 +1,203 @@
|
||||
/*
|
||||
******************************************************************************
|
||||
**
|
||||
** @file : STM32N657XX_AXISRAM2_fsbl.ld
|
||||
**
|
||||
** @author : GPM Application Team
|
||||
**
|
||||
** @brief : Linker script for STM32N657XX Device from STM32N6 series
|
||||
** 512 KBytes RAM
|
||||
**
|
||||
** Set heap size, stack size and stack location according
|
||||
** to application requirements.
|
||||
**
|
||||
** Set memory bank area and size if external memory is used
|
||||
**
|
||||
** Target : STMicroelectronics STM32
|
||||
**
|
||||
** Distribution: The file is distributed as is, without any warranty
|
||||
** of any kind.
|
||||
**
|
||||
******************************************************************************
|
||||
** @attention
|
||||
**
|
||||
** Copyright (c) 2023 STMicroelectronics.
|
||||
** All rights reserved.
|
||||
**
|
||||
** This software is licensed under terms that can be found in the LICENSE file
|
||||
** in the root directory of this software component.
|
||||
** If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
**
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Entry Point */
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
/* Highest address of the user mode stack */
|
||||
_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
|
||||
_sstack = _estack - _Min_Stack_Size;
|
||||
|
||||
_Min_Heap_Size = 0x200; /* required amount of heap */
|
||||
_Min_Stack_Size = 0x800; /* required amount of stack */
|
||||
|
||||
/* Memories definition */
|
||||
MEMORY
|
||||
{
|
||||
ROM (xrw) : ORIGIN = 0x34180400, LENGTH = 255K
|
||||
RAM (xrw) : ORIGIN = 0x341C0000, LENGTH = 256K
|
||||
}
|
||||
|
||||
/* Sections */
|
||||
SECTIONS
|
||||
{
|
||||
/* The startup code into "RAM" Ram type memory */
|
||||
.isr_vector :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.isr_vector)) /* Startup code */
|
||||
. = ALIGN(4);
|
||||
} >ROM
|
||||
|
||||
/* The program code and other data into "RAM" Ram type memory */
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.text) /* .text sections (code) */
|
||||
*(.text*) /* .text* sections (code) */
|
||||
*(.glue_7) /* glue arm to thumb code */
|
||||
*(.glue_7t) /* glue thumb to arm code */
|
||||
*(.eh_frame)
|
||||
*(.RamFunc) /* .RamFunc sections */
|
||||
*(.RamFunc*) /* .RamFunc* sections */
|
||||
|
||||
KEEP (*(.init))
|
||||
KEEP (*(.fini))
|
||||
|
||||
. = ALIGN(4);
|
||||
_etext = .; /* define a global symbols at end of code */
|
||||
} >ROM
|
||||
|
||||
/* Constant data into "RAM" Ram type memory */
|
||||
.rodata :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.rodata) /* .rodata sections (constants, strings, etc.) */
|
||||
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
|
||||
. = ALIGN(4);
|
||||
} >ROM
|
||||
|
||||
.ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
. = ALIGN(4);
|
||||
} >ROM
|
||||
|
||||
.ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__exidx_start = .;
|
||||
*(.ARM.exidx*)
|
||||
__exidx_end = .;
|
||||
. = ALIGN(4);
|
||||
} >ROM
|
||||
|
||||
.preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array*))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
. = ALIGN(4);
|
||||
} >ROM
|
||||
|
||||
.init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array*))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
. = ALIGN(4);
|
||||
} >ROM
|
||||
|
||||
.fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
KEEP (*(.fini_array*))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
. = ALIGN(4);
|
||||
} >ROM
|
||||
|
||||
/* Used by the startup to initialize data */
|
||||
_sidata = LOADADDR(.data);
|
||||
|
||||
/* Initialized data sections into "RAM" Ram type memory */
|
||||
.data :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sdata = .; /* create a global symbol at data start */
|
||||
*(.data) /* .data sections */
|
||||
*(.data*) /* .data* sections */
|
||||
|
||||
. = ALIGN(4);
|
||||
_edata = .; /* define a global symbol at data end */
|
||||
|
||||
} >RAM AT> ROM
|
||||
|
||||
.noncacheable :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
__snoncacheable = .;/* create symbol for start of section */
|
||||
KEEP(*(.noncacheable))
|
||||
. = ALIGN(8);
|
||||
__enoncacheable = .; /* create symbol for end of section */
|
||||
} > RAM
|
||||
|
||||
|
||||
.gnu.sgstubs :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.gnu.sgstubs*) /* Secure Gateway stubs */
|
||||
. = ALIGN(4);
|
||||
} >ROM
|
||||
/* Uninitialized data section into "RAM" Ram type memory */
|
||||
. = ALIGN(4);
|
||||
.bss :
|
||||
{
|
||||
/* This is used by the startup in order to initialize the .bss section */
|
||||
_sbss = .; /* define a global symbol at bss start */
|
||||
__bss_start__ = _sbss;
|
||||
*(.bss)
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
|
||||
. = ALIGN(4);
|
||||
_ebss = .; /* define a global symbol at bss end */
|
||||
__bss_end__ = _ebss;
|
||||
} >RAM
|
||||
|
||||
/* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
|
||||
._user_heap_stack :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
PROVIDE ( end = . );
|
||||
PROVIDE ( _end = . );
|
||||
. = . + _Min_Heap_Size;
|
||||
. = . + _Min_Stack_Size;
|
||||
. = ALIGN(8);
|
||||
} >RAM
|
||||
|
||||
/* Remove information from the compiler libraries */
|
||||
/DISCARD/ :
|
||||
{
|
||||
libc.a ( * )
|
||||
libm.a ( * )
|
||||
libgcc.a ( * )
|
||||
}
|
||||
|
||||
.ARM.attributes 0 : { *(.ARM.attributes) }
|
||||
}
|
||||
@@ -0,0 +1,17 @@
|
||||
set(MCU_VARIANT stm32n657xx)
|
||||
set(JLINK_DEVICE stm32n6xx)
|
||||
|
||||
set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32N657XX_AXISRAM2_fsbl.ld)
|
||||
|
||||
function(update_board TARGET)
|
||||
target_compile_definitions(${TARGET} PUBLIC
|
||||
STM32N657xx
|
||||
)
|
||||
target_sources(${TARGET} PUBLIC
|
||||
${ST_TCPP0203}/tcpp0203.c
|
||||
${ST_TCPP0203}/tcpp0203_reg.c
|
||||
)
|
||||
target_include_directories(${TARGET} PUBLIC
|
||||
${ST_TCPP0203}
|
||||
)
|
||||
endfunction()
|
||||
@@ -0,0 +1,283 @@
|
||||
/*
|
||||
* The MIT License (MIT)
|
||||
*
|
||||
* Copyright (c) 2021, Ha Thach (tinyusb.org)
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
* THE SOFTWARE.
|
||||
*
|
||||
* This file is part of the TinyUSB stack.
|
||||
*/
|
||||
|
||||
/* metadata:
|
||||
name: STM32 N657X0-Q Nucleo
|
||||
url: https://www.st.com/en/evaluation-tools/nucleo-n657x0-q.html
|
||||
*/
|
||||
|
||||
#ifndef BOARD_H_
|
||||
#define BOARD_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "stm32n657xx.h"
|
||||
#include "stm32n6xx_ll_exti.h"
|
||||
#include "stm32n6xx_ll_system.h"
|
||||
#include "tcpp0203.h"
|
||||
|
||||
#define UART_DEV USART1
|
||||
#define UART_CLK_EN __HAL_RCC_USART1_CLK_ENABLE
|
||||
|
||||
#define BOARD_TUD_RHPORT 1
|
||||
|
||||
// VBUS Sense detection
|
||||
#define OTG_FS_VBUS_SENSE 1
|
||||
#define OTG_HS_VBUS_SENSE 1
|
||||
|
||||
#define PINID_LED 0
|
||||
#define PINID_BUTTON 1
|
||||
#define PINID_UART_TX 2
|
||||
#define PINID_UART_RX 3
|
||||
#define PINID_TCPP0203_EN 4
|
||||
|
||||
static board_pindef_t board_pindef[] = {
|
||||
{// LED
|
||||
.port = GPIOG,
|
||||
.pin_init = {.Pin = GPIO_PIN_10, .Mode = GPIO_MODE_OUTPUT_PP, .Pull = GPIO_PULLDOWN, .Speed = GPIO_SPEED_FREQ_HIGH, .Alternate = 0},
|
||||
.active_state = 1},
|
||||
{// Button
|
||||
.port = GPIOC,
|
||||
.pin_init = {.Pin = GPIO_PIN_13, .Mode = GPIO_MODE_INPUT, .Pull = GPIO_PULLDOWN, .Speed = GPIO_SPEED_FREQ_HIGH, .Alternate = 0},
|
||||
.active_state = 1},
|
||||
{// UART TX
|
||||
.port = GPIOE,
|
||||
.pin_init = {.Pin = GPIO_PIN_5, .Mode = GPIO_MODE_AF_PP, .Pull = GPIO_NOPULL, .Speed = GPIO_SPEED_FREQ_LOW, .Alternate = GPIO_AF7_USART1},
|
||||
.active_state = 0},
|
||||
{// UART RX
|
||||
.port = GPIOE,
|
||||
.pin_init = {.Pin = GPIO_PIN_6, .Mode = GPIO_MODE_AF_PP, .Pull = GPIO_NOPULL, .Speed = GPIO_SPEED_FREQ_LOW, .Alternate = GPIO_AF7_USART1},
|
||||
.active_state = 0},
|
||||
{// VBUS input pin used for TCPP0203 EN
|
||||
.port = GPIOA,
|
||||
.pin_init = {.Pin = GPIO_PIN_7, .Mode = GPIO_MODE_OUTPUT_PP, .Pull = GPIO_PULLDOWN, .Speed = GPIO_SPEED_FREQ_HIGH, .Alternate = 0},
|
||||
.active_state = 0},
|
||||
{
|
||||
// I2C SCL for TCPP0203
|
||||
.port = GPIOB,
|
||||
.pin_init = {.Pin = GPIO_PIN_10, .Mode = GPIO_MODE_AF_OD, .Pull = GPIO_NOPULL, .Speed = GPIO_SPEED_FREQ_LOW, .Alternate = GPIO_AF4_I2C2},
|
||||
},
|
||||
{
|
||||
// I2C SDA for TCPP0203
|
||||
.port = GPIOB,
|
||||
.pin_init = {.Pin = GPIO_PIN_11, .Mode = GPIO_MODE_AF_OD, .Pull = GPIO_NOPULL, .Speed = GPIO_SPEED_FREQ_LOW, .Alternate = GPIO_AF4_I2C2},
|
||||
},
|
||||
{
|
||||
// INT for TCPP0203
|
||||
.port = GPIOD,
|
||||
.pin_init = {.Pin = GPIO_PIN_2, .Mode = GPIO_MODE_IT_FALLING, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_FREQ_HIGH, .Alternate = 0},
|
||||
},
|
||||
};
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// RCC Clock
|
||||
//--------------------------------------------------------------------+
|
||||
void SystemClock_Config(void) {
|
||||
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
|
||||
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
|
||||
/* Configure the power domain */
|
||||
if (HAL_PWREx_ConfigSupply(PWR_EXTERNAL_SOURCE_SUPPLY) != HAL_OK) {
|
||||
Error_Handler();
|
||||
}
|
||||
|
||||
/* Get current CPU/System buses clocks configuration */
|
||||
/* and if necessary switch to intermediate HSI clock */
|
||||
/* to ensure target clock can be set */
|
||||
HAL_RCC_GetClockConfig(&RCC_ClkInitStruct);
|
||||
if ((RCC_ClkInitStruct.CPUCLKSource == RCC_CPUCLKSOURCE_IC1) ||
|
||||
(RCC_ClkInitStruct.SYSCLKSource == RCC_SYSCLKSOURCE_IC2_IC6_IC11)) {
|
||||
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_CPUCLK | RCC_CLOCKTYPE_SYSCLK);
|
||||
RCC_ClkInitStruct.CPUCLKSource = RCC_CPUCLKSOURCE_HSI;
|
||||
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
|
||||
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct) != HAL_OK) {
|
||||
Error_Handler();
|
||||
}
|
||||
}
|
||||
|
||||
/* HSE selected as source (stable clock on Level 0 samples */
|
||||
/* PLL1 output = ((HSE/PLLM)*PLLN)/PLLP1/PLLP2 */
|
||||
/* = ((48000000/3)*75)/1/1 */
|
||||
/* = (16000000*75)/1/1 */
|
||||
/* = 1200000000 (1200 MHz) */
|
||||
/* PLL2 off */
|
||||
/* PLL3 off */
|
||||
/* PLL4 off */
|
||||
|
||||
/* Enable HSE && HSI */
|
||||
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
|
||||
RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
|
||||
RCC_OscInitStruct.HSIDiv = RCC_HSI_DIV1;
|
||||
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
|
||||
RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* 48 MHz */
|
||||
|
||||
RCC_OscInitStruct.PLL1.PLLState = RCC_PLL_ON;
|
||||
RCC_OscInitStruct.PLL1.PLLSource = RCC_PLLSOURCE_HSE;
|
||||
RCC_OscInitStruct.PLL1.PLLM = 3;
|
||||
RCC_OscInitStruct.PLL1.PLLN = 75; /* PLL1 VCO = 48/3 * 75 = 1200MHz */
|
||||
RCC_OscInitStruct.PLL1.PLLP1 = 1; /* PLL output = PLL VCO frequency / (PLLP1 * PLLP2) */
|
||||
RCC_OscInitStruct.PLL1.PLLP2 = 1; /* PLL output = 1200 MHz */
|
||||
RCC_OscInitStruct.PLL1.PLLFractional = 0;
|
||||
|
||||
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
|
||||
/* Initialization error */
|
||||
Error_Handler();
|
||||
}
|
||||
|
||||
/* Select PLL1 outputs as CPU and System bus clock source */
|
||||
/* CPUCLK = ic1_ck = PLL1 output/ic1_divider = 600 MHz */
|
||||
/* SYSCLK = ic2_ck = PLL1 output/ic2_divider = 400 MHz */
|
||||
/* Configure the HCLK clock divider */
|
||||
/* HCLK = PLL1 SYSCLK/HCLK divider = 200 MHz */
|
||||
/* PCLKx = HCLK / PCLKx divider = 200 MHz */
|
||||
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_CPUCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK |
|
||||
RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_PCLK4 | RCC_CLOCKTYPE_PCLK5);
|
||||
RCC_ClkInitStruct.CPUCLKSource = RCC_CPUCLKSOURCE_IC1;
|
||||
RCC_ClkInitStruct.IC1Selection.ClockSelection = RCC_ICCLKSOURCE_PLL1;
|
||||
RCC_ClkInitStruct.IC1Selection.ClockDivider = 2;
|
||||
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_IC2_IC6_IC11;
|
||||
RCC_ClkInitStruct.IC2Selection.ClockSelection = RCC_ICCLKSOURCE_PLL1;
|
||||
RCC_ClkInitStruct.IC2Selection.ClockDivider = 3;
|
||||
RCC_ClkInitStruct.IC6Selection.ClockSelection = RCC_ICCLKSOURCE_PLL1;
|
||||
RCC_ClkInitStruct.IC6Selection.ClockDivider = 3;
|
||||
RCC_ClkInitStruct.IC11Selection.ClockSelection = RCC_ICCLKSOURCE_PLL1;
|
||||
RCC_ClkInitStruct.IC11Selection.ClockDivider = 3;
|
||||
RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2;
|
||||
RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV1;
|
||||
RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV1;
|
||||
RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV1;
|
||||
RCC_ClkInitStruct.APB5CLKDivider = RCC_APB5_DIV1;
|
||||
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct) != HAL_OK) {
|
||||
/* Initialization Error */
|
||||
Error_Handler();
|
||||
}
|
||||
|
||||
/** Initializes the peripherals clock
|
||||
*/
|
||||
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
|
||||
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USBOTGHS1;
|
||||
PeriphClkInitStruct.UsbOtgHs1ClockSelection = RCC_USBPHY1REFCLKSOURCE_HSE_DIRECT;
|
||||
|
||||
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
|
||||
/* Initialization Error */
|
||||
Error_Handler();
|
||||
}
|
||||
|
||||
/** Set USB OTG HS PHY1 Reference Clock Source */
|
||||
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USBPHY1;
|
||||
PeriphClkInitStruct.UsbPhy1ClockSelection = RCC_USBPHY1REFCLKSOURCE_HSE_DIRECT;
|
||||
|
||||
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
|
||||
/* Initialization Error */
|
||||
Error_Handler();
|
||||
}
|
||||
}
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// USB PD
|
||||
//--------------------------------------------------------------------+
|
||||
static I2C_HandleTypeDef i2c_handle = {
|
||||
.Instance = I2C2,
|
||||
.Init = {
|
||||
.Timing = 0x20C0EDFF,
|
||||
.OwnAddress1 = 0,
|
||||
.AddressingMode = I2C_ADDRESSINGMODE_7BIT,
|
||||
.DualAddressMode = I2C_DUALADDRESS_DISABLE,
|
||||
.OwnAddress2 = 0,
|
||||
.OwnAddress2Masks = I2C_OA2_NOMASK,
|
||||
.GeneralCallMode = I2C_GENERALCALL_DISABLE,
|
||||
.NoStretchMode = I2C_NOSTRETCH_DISABLE,
|
||||
}};
|
||||
static TCPP0203_Object_t tcpp0203_obj = {0};
|
||||
|
||||
int32_t board_tcpp0203_init(void) {
|
||||
board_pindef_t *pindef = &board_pindef[PINID_TCPP0203_EN];
|
||||
HAL_GPIO_WritePin(pindef->port, pindef->pin_init.Pin, GPIO_PIN_SET);
|
||||
|
||||
__HAL_RCC_I2C2_CLK_ENABLE();
|
||||
__HAL_RCC_I2C2_FORCE_RESET();
|
||||
__HAL_RCC_I2C2_RELEASE_RESET();
|
||||
if (HAL_I2C_Init(&i2c_handle) != HAL_OK) {
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
NVIC_SetPriority(EXTI8_IRQn, 12);
|
||||
NVIC_EnableIRQ(EXTI8_IRQn);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int32_t board_tcpp0203_deinit(void) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
int32_t i2c_readreg(uint16_t DevAddr, uint16_t Reg, uint8_t *pData, uint16_t Length) {
|
||||
TU_ASSERT(HAL_OK == HAL_I2C_Mem_Read(&i2c_handle, DevAddr, Reg, I2C_MEMADD_SIZE_8BIT, pData, Length, 10000));
|
||||
return 0;
|
||||
}
|
||||
|
||||
int32_t i2c_writereg(uint16_t DevAddr, uint16_t Reg, uint8_t *pData, uint16_t Length) {
|
||||
TU_ASSERT(HAL_OK == HAL_I2C_Mem_Write(&i2c_handle, DevAddr, Reg, I2C_MEMADD_SIZE_8BIT, pData, Length, 10000));
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline void board_init2(void) {
|
||||
TCPP0203_IO_t io_ctx;
|
||||
|
||||
io_ctx.Address = TCPP0203_I2C_ADDRESS_X68;
|
||||
io_ctx.Init = board_tcpp0203_init;
|
||||
io_ctx.DeInit = board_tcpp0203_deinit;
|
||||
io_ctx.ReadReg = i2c_readreg;
|
||||
io_ctx.WriteReg = i2c_writereg;
|
||||
|
||||
TU_ASSERT(TCPP0203_RegisterBusIO(&tcpp0203_obj, &io_ctx) == TCPP0203_OK, );
|
||||
|
||||
TU_ASSERT(TCPP0203_Init(&tcpp0203_obj) == TCPP0203_OK, );
|
||||
|
||||
TU_ASSERT(TCPP0203_SetPowerMode(&tcpp0203_obj, TCPP0203_POWER_MODE_NORMAL) == TCPP0203_OK, );
|
||||
}
|
||||
|
||||
void board_vbus_set(uint8_t rhport, bool state) {
|
||||
(void) state;
|
||||
if (rhport == 1) {
|
||||
TU_ASSERT(TCPP0203_SetGateDriverProvider(&tcpp0203_obj, TCPP0203_GD_PROVIDER_SWITCH_CLOSED) == TCPP0203_OK, );
|
||||
}
|
||||
}
|
||||
|
||||
void EXTI8_IRQHandler(void) {
|
||||
__HAL_GPIO_EXTI_CLEAR_IT(GPIO_PIN_8);
|
||||
if (tcpp0203_obj.IsInitialized) {
|
||||
TU_ASSERT(TCPP0203_SetPowerMode(&tcpp0203_obj, TCPP0203_POWER_MODE_NORMAL) == TCPP0203_OK, );
|
||||
TU_ASSERT(TCPP0203_SetGateDriverProvider(&tcpp0203_obj, TCPP0203_GD_PROVIDER_SWITCH_CLOSED) == TCPP0203_OK, );
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,17 @@
|
||||
MCU_VARIANT = stm32n657xx
|
||||
CFLAGS += -DSTM32N657xx
|
||||
JLINK_DEVICE = stm32n6xx
|
||||
|
||||
LD_FILE_GCC = $(BOARD_PATH)/STM32N657XX_AXISRAM2_fsbl.ld
|
||||
|
||||
# flash target using on-board stlink
|
||||
flash: flash-stlink
|
||||
|
||||
PORT = 1
|
||||
|
||||
SRC_C += \
|
||||
$(ST_TCPP0203)/tcpp0203.c \
|
||||
$(ST_TCPP0203)/tcpp0203_reg.c \
|
||||
|
||||
INC += \
|
||||
$(TOP)/$(ST_TCPP0203) \
|
||||
280
managed_components/espressif__tinyusb/hw/bsp/stm32n6/family.c
Normal file
280
managed_components/espressif__tinyusb/hw/bsp/stm32n6/family.c
Normal file
@@ -0,0 +1,280 @@
|
||||
/*
|
||||
* The MIT License (MIT)
|
||||
*
|
||||
* Copyright (c) 2019
|
||||
* William D. Jones (thor0505@comcast.net),
|
||||
* Ha Thach (tinyusb.org)
|
||||
* Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
* THE SOFTWARE.
|
||||
*
|
||||
* This file is part of the TinyUSB stack.
|
||||
*/
|
||||
|
||||
/* metadata:
|
||||
manufacturer: STMicroelectronics
|
||||
*/
|
||||
|
||||
// Suppress warning caused by mcu driver
|
||||
#ifdef __GNUC__
|
||||
#pragma GCC diagnostic push
|
||||
#pragma GCC diagnostic ignored "-Wcast-align"
|
||||
#endif
|
||||
|
||||
#include "stm32n6xx_hal.h"
|
||||
|
||||
#ifdef __GNUC__
|
||||
#pragma GCC diagnostic pop
|
||||
#endif
|
||||
|
||||
#include "bsp/board_api.h"
|
||||
|
||||
TU_ATTR_UNUSED static void Error_Handler(void) { }
|
||||
|
||||
void HardFault_Handler(void);
|
||||
|
||||
typedef struct {
|
||||
GPIO_TypeDef* port;
|
||||
GPIO_InitTypeDef pin_init;
|
||||
uint8_t active_state;
|
||||
} board_pindef_t;
|
||||
|
||||
#include "board.h"
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// MACRO TYPEDEF CONSTANT ENUM
|
||||
//--------------------------------------------------------------------+
|
||||
|
||||
#ifdef UART_DEV
|
||||
UART_HandleTypeDef UartHandle = {
|
||||
.Instance = UART_DEV,
|
||||
.Init = {
|
||||
.BaudRate = CFG_BOARD_UART_BAUDRATE,
|
||||
.WordLength = UART_WORDLENGTH_8B,
|
||||
.StopBits = UART_STOPBITS_1,
|
||||
.Parity = UART_PARITY_NONE,
|
||||
.HwFlowCtl = UART_HWCONTROL_NONE,
|
||||
.Mode = UART_MODE_TX_RX,
|
||||
.OverSampling = UART_OVERSAMPLING_16,
|
||||
}
|
||||
};
|
||||
#endif
|
||||
|
||||
#ifndef SWO_FREQ
|
||||
#define SWO_FREQ 4000000
|
||||
#endif
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// Forward USB interrupt events to TinyUSB IRQ Handler
|
||||
//--------------------------------------------------------------------+
|
||||
|
||||
// Despite being call USB2_OTG_FS on some MCUs
|
||||
// OTG_FS is marked as RHPort0 by TinyUSB to be consistent across stm32 port
|
||||
void USB2_OTG_HS_IRQHandler(void) {
|
||||
tusb_int_handler(0, true);
|
||||
}
|
||||
|
||||
// Despite being call USB1_OTG_HS on some MCUs
|
||||
// OTG_HS is marked as RHPort1 by TinyUSB to be consistent across stm32 port
|
||||
void USB1_OTG_HS_IRQHandler(void) {
|
||||
tusb_int_handler(1, true);
|
||||
}
|
||||
|
||||
void board_init(void) {
|
||||
|
||||
/* Enable BusFault and SecureFault handlers (HardFault is default) */
|
||||
SCB->SHCSR |= (SCB_SHCSR_BUSFAULTENA_Msk | SCB_SHCSR_SECUREFAULTENA_Msk);
|
||||
|
||||
HAL_PWREx_EnableVddA();
|
||||
HAL_PWREx_EnableVddIO2();
|
||||
HAL_PWREx_EnableVddIO3();
|
||||
HAL_PWREx_EnableVddIO4();
|
||||
HAL_PWREx_EnableVddIO5();
|
||||
|
||||
HAL_Init();
|
||||
|
||||
// Implemented in board.h
|
||||
SystemClock_Config();
|
||||
|
||||
// Enable All GPIOs clocks
|
||||
__HAL_RCC_GPIOA_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOB_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOC_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOD_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOE_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOF_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOG_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOH_CLK_ENABLE();
|
||||
__HAL_RCC_GPION_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOO_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOP_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOQ_CLK_ENABLE();
|
||||
|
||||
// HAL_ICACHE_Enable();
|
||||
|
||||
for (uint8_t i = 0; i < TU_ARRAY_SIZE(board_pindef); i++) {
|
||||
HAL_GPIO_Init(board_pindef[i].port, &board_pindef[i].pin_init);
|
||||
}
|
||||
|
||||
NVIC_SetPriority(UCPD1_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),5, 0));
|
||||
NVIC_EnableIRQ(UCPD1_IRQn);
|
||||
|
||||
#if CFG_TUSB_OS == OPT_OS_NONE
|
||||
// 1ms tick timer
|
||||
SysTick_Config(SystemCoreClock / 1000);
|
||||
|
||||
#elif CFG_TUSB_OS == OPT_OS_FREERTOS
|
||||
// Explicitly disable systick to prevent its ISR runs before scheduler start
|
||||
SysTick->CTRL &= ~1U;
|
||||
|
||||
// If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
|
||||
|
||||
NVIC_SetPriority(USB1_OTG_HS_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
#ifdef UART_DEV
|
||||
UART_CLK_EN();
|
||||
HAL_UART_Init(&UartHandle);
|
||||
#endif
|
||||
|
||||
|
||||
__HAL_RCC_USB1_OTG_HS_CLK_ENABLE();
|
||||
__HAL_RCC_PWR_CLK_ENABLE();
|
||||
HAL_PWREx_EnableVddUSBVMEN();
|
||||
while(__HAL_PWR_GET_FLAG(PWR_FLAG_USB33RDY));
|
||||
HAL_PWREx_EnableVddUSB();
|
||||
|
||||
LL_AHB5_GRP1_ForceReset(0x00800000);
|
||||
__HAL_RCC_USB1_OTG_HS_FORCE_RESET();
|
||||
__HAL_RCC_USB1_OTG_HS_PHY_FORCE_RESET();
|
||||
|
||||
LL_RCC_HSE_SelectHSEDiv2AsDiv2Clock();
|
||||
LL_AHB5_GRP1_ReleaseReset(0x00800000);
|
||||
|
||||
/* Peripheral clock enable */
|
||||
__HAL_RCC_USB1_OTG_HS_CLK_ENABLE();
|
||||
|
||||
/* Required few clock cycles before accessing USB PHY Controller Registers */
|
||||
for (volatile uint32_t i = 0; i < 10; i++) {
|
||||
__NOP(); // No Operation instruction to create a delay
|
||||
}
|
||||
|
||||
USB1_HS_PHYC->USBPHYC_CR &= ~(0x7 << 0x4);
|
||||
|
||||
USB1_HS_PHYC->USBPHYC_CR |= (0x1 << 16) |
|
||||
(0x2 << 4) |
|
||||
(0x1 << 2) |
|
||||
0x1U;
|
||||
|
||||
__HAL_RCC_USB1_OTG_HS_PHY_RELEASE_RESET();
|
||||
|
||||
/* Required few clock cycles before Releasing Reset */
|
||||
for (volatile uint32_t i = 0; i < 10; i++) {
|
||||
__NOP(); // No Operation instruction to create a delay
|
||||
}
|
||||
|
||||
__HAL_RCC_USB1_OTG_HS_RELEASE_RESET();
|
||||
|
||||
/* Peripheral PHY clock enable */
|
||||
__HAL_RCC_USB1_OTG_HS_PHY_CLK_ENABLE();
|
||||
|
||||
board_init2();
|
||||
|
||||
#if CFG_TUH_ENABLED
|
||||
board_vbus_set(BOARD_TUH_RHPORT, 1);
|
||||
#endif
|
||||
}
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// Board porting API
|
||||
//--------------------------------------------------------------------+
|
||||
|
||||
void board_led_write(bool state) {
|
||||
#ifdef PINID_LED
|
||||
board_pindef_t* pindef = &board_pindef[PINID_LED];
|
||||
GPIO_PinState pin_state = state == pindef->active_state ? GPIO_PIN_SET : GPIO_PIN_RESET;
|
||||
HAL_GPIO_WritePin(pindef->port, pindef->pin_init.Pin, pin_state);
|
||||
#else
|
||||
(void) state;
|
||||
#endif
|
||||
}
|
||||
|
||||
uint32_t board_button_read(void) {
|
||||
#ifdef PINID_BUTTON
|
||||
board_pindef_t* pindef = &board_pindef[PINID_BUTTON];
|
||||
return pindef->active_state == HAL_GPIO_ReadPin(pindef->port, pindef->pin_init.Pin);
|
||||
#else
|
||||
return 0;
|
||||
#endif
|
||||
}
|
||||
|
||||
size_t board_get_unique_id(uint8_t id[], size_t max_len) {
|
||||
(void) max_len;
|
||||
volatile uint32_t * stm32_uuid = (volatile uint32_t *) UID_BASE;
|
||||
uint32_t* id32 = (uint32_t*) (uintptr_t) id;
|
||||
uint8_t const len = 12;
|
||||
|
||||
id32[0] = stm32_uuid[0];
|
||||
id32[1] = stm32_uuid[1];
|
||||
id32[2] = stm32_uuid[2];
|
||||
|
||||
return len;
|
||||
}
|
||||
|
||||
int board_uart_read(uint8_t *buf, int len) {
|
||||
(void) buf;
|
||||
(void) len;
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_uart_write(void const *buf, int len) {
|
||||
#ifdef UART_DEV
|
||||
HAL_UART_Transmit(&UartHandle, (uint8_t * )(uintptr_t)
|
||||
buf, len, 0xffff);
|
||||
return len;
|
||||
#else
|
||||
(void) buf; (void) len;
|
||||
return -1;
|
||||
#endif
|
||||
}
|
||||
|
||||
#if CFG_TUSB_OS == OPT_OS_NONE
|
||||
volatile uint32_t system_ticks = 0;
|
||||
|
||||
void SysTick_Handler(void) {
|
||||
HAL_IncTick();
|
||||
system_ticks++;
|
||||
}
|
||||
|
||||
uint32_t board_millis(void) {
|
||||
return system_ticks;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
void HardFault_Handler(void) {
|
||||
__asm("BKPT #0\n");
|
||||
}
|
||||
|
||||
// Required by __libc_init_array in startup code if we are compiling using
|
||||
// -nostdlib/-nostartfiles.
|
||||
void _init(void) {
|
||||
}
|
||||
@@ -0,0 +1,148 @@
|
||||
include_guard()
|
||||
|
||||
set(ST_FAMILY n6)
|
||||
set(ST_PREFIX stm32${ST_FAMILY}xx)
|
||||
|
||||
set(ST_HAL_DRIVER ${TOP}/hw/mcu/st/stm32${ST_FAMILY}xx_hal_driver)
|
||||
set(ST_CMSIS ${TOP}/hw/mcu/st/cmsis_device_${ST_FAMILY})
|
||||
set(CMSIS_5 ${TOP}/lib/CMSIS_5)
|
||||
set(ST_TCPP0203 ${TOP}/hw/mcu/st/stm32-tcpp0203)
|
||||
|
||||
# include board specific
|
||||
include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
|
||||
|
||||
# toolchain set up
|
||||
set(CMAKE_SYSTEM_CPU cortex-m55 CACHE INTERNAL "System Processor")
|
||||
set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
|
||||
|
||||
set(FAMILY_MCUS STM32N6 CACHE INTERNAL "")
|
||||
|
||||
# ----------------------
|
||||
# Port & Speed Selection
|
||||
# ----------------------
|
||||
if (NOT DEFINED RHPORT_DEVICE)
|
||||
set(RHPORT_DEVICE 1)
|
||||
endif ()
|
||||
if (NOT DEFINED RHPORT_HOST)
|
||||
set(RHPORT_HOST 1)
|
||||
endif ()
|
||||
|
||||
# N6 are all high speed
|
||||
if (NOT DEFINED RHPORT_DEVICE_SPEED)
|
||||
set(RHPORT_DEVICE_SPEED OPT_MODE_HIGH_SPEED)
|
||||
endif ()
|
||||
if (NOT DEFINED RHPORT_HOST_SPEED)
|
||||
set(RHPORT_HOST_SPEED OPT_MODE_HIGH_SPEED)
|
||||
endif ()
|
||||
|
||||
cmake_print_variables(RHPORT_DEVICE RHPORT_DEVICE_SPEED RHPORT_HOST RHPORT_HOST_SPEED)
|
||||
|
||||
#------------------------------------
|
||||
# BOARD_TARGET
|
||||
#------------------------------------
|
||||
# only need to be built ONCE for all examples
|
||||
function(add_board_target BOARD_TARGET)
|
||||
if (TARGET ${BOARD_TARGET})
|
||||
return()
|
||||
endif()
|
||||
|
||||
# Startup & Linker script
|
||||
set(STARTUP_FILE_GNU ${ST_CMSIS}/Source/Templates/gcc/startup_${MCU_VARIANT}.s)
|
||||
set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
|
||||
set(STARTUP_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/startup_${MCU_VARIANT}.s)
|
||||
|
||||
if(NOT DEFINED LD_FILE_GNU)
|
||||
set(LD_FILE_GNU ${ST_CMSIS}/Source/Templates/gcc/linker/${MCU_VARIANT}_flash.ld)
|
||||
endif()
|
||||
set(LD_FILE_Clang ${LD_FILE_GNU})
|
||||
if(NOT DEFINED LD_FILE_IAR)
|
||||
set(LD_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/linker/${MCU_VARIANT}_flash.icf)
|
||||
endif()
|
||||
|
||||
add_library(${BOARD_TARGET} STATIC
|
||||
${ST_CMSIS}/Source/Templates/system_${ST_PREFIX}_fsbl.c
|
||||
${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal.c
|
||||
${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_cortex.c
|
||||
${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_dma.c
|
||||
${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_gpio.c
|
||||
${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_pwr.c
|
||||
${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_i2c.c
|
||||
${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_pwr_ex.c
|
||||
${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc.c
|
||||
${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc_ex.c
|
||||
${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart.c
|
||||
${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart_ex.c
|
||||
${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
|
||||
)
|
||||
target_include_directories(${BOARD_TARGET} PUBLIC
|
||||
${CMAKE_CURRENT_FUNCTION_LIST_DIR}
|
||||
${CMSIS_5}/CMSIS/Core/Include
|
||||
${ST_CMSIS}/Include
|
||||
${ST_HAL_DRIVER}/Inc
|
||||
)
|
||||
target_compile_definitions(${BOARD_TARGET} PUBLIC
|
||||
BOARD_TUD_RHPORT=${RHPORT_DEVICE}
|
||||
BOARD_TUD_MAX_SPEED=${RHPORT_DEVICE_SPEED}
|
||||
BOARD_TUH_RHPORT=${RHPORT_HOST}
|
||||
BOARD_TUH_MAX_SPEED=${RHPORT_HOST_SPEED}
|
||||
SEGGER_RTT_SECTION="noncacheable_buffer"
|
||||
BUFFER_SIZE_UP=0x3000
|
||||
)
|
||||
|
||||
update_board(${BOARD_TARGET})
|
||||
|
||||
if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
|
||||
target_link_options(${BOARD_TARGET} PUBLIC
|
||||
"LINKER:--script=${LD_FILE_GNU}"
|
||||
-nostartfiles
|
||||
--specs=nosys.specs --specs=nano.specs
|
||||
)
|
||||
elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
|
||||
target_link_options(${BOARD_TARGET} PUBLIC
|
||||
"LINKER:--script=${LD_FILE_Clang}"
|
||||
)
|
||||
elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
|
||||
target_link_options(${BOARD_TARGET} PUBLIC
|
||||
"LINKER:--config=${LD_FILE_IAR}"
|
||||
)
|
||||
endif ()
|
||||
endfunction()
|
||||
|
||||
|
||||
#------------------------------------
|
||||
# Functions
|
||||
#------------------------------------
|
||||
function(family_configure_example TARGET RTOS)
|
||||
family_configure_common(${TARGET} ${RTOS})
|
||||
|
||||
# Board target
|
||||
add_board_target(board_${BOARD})
|
||||
|
||||
#---------- Port Specific ----------
|
||||
# These files are built for each example since it depends on example's tusb_config.h
|
||||
target_sources(${TARGET} PUBLIC
|
||||
# BSP
|
||||
${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
|
||||
${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
|
||||
)
|
||||
target_include_directories(${TARGET} PUBLIC
|
||||
# family, hw, board
|
||||
${CMAKE_CURRENT_FUNCTION_LIST_DIR}
|
||||
${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
|
||||
${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
|
||||
)
|
||||
|
||||
# Add TinyUSB target and port source
|
||||
family_add_tinyusb(${TARGET} OPT_MCU_STM32N6 ${RTOS})
|
||||
target_sources(${TARGET} PUBLIC
|
||||
${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c
|
||||
${TOP}/src/portable/synopsys/dwc2/hcd_dwc2.c
|
||||
${TOP}/src/portable/synopsys/dwc2/dwc2_common.c
|
||||
)
|
||||
target_link_libraries(${TARGET} PUBLIC board_${BOARD})
|
||||
|
||||
# Flashing
|
||||
family_add_bin_hex(${TARGET})
|
||||
family_flash_stlink(${TARGET})
|
||||
family_flash_jlink(${TARGET})
|
||||
endfunction()
|
||||
@@ -0,0 +1,89 @@
|
||||
ST_FAMILY = n6
|
||||
ST_PREFIX = stm32${ST_FAMILY}xx
|
||||
ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY)
|
||||
ST_HAL_DRIVER = hw/mcu/st/${ST_PREFIX}_hal_driver
|
||||
ST_TCPP0203 = hw/mcu/st/stm32-tcpp0203
|
||||
|
||||
UF2_FAMILY_ID = 0x6db66083
|
||||
|
||||
include $(TOP)/$(BOARD_PATH)/board.mk
|
||||
CPU_CORE ?= cortex-m55
|
||||
|
||||
# ----------------------
|
||||
# Port & Speed Selection
|
||||
# ----------------------
|
||||
RHPORT_DEVICE ?= 1
|
||||
RHPORT_HOST ?= 1
|
||||
|
||||
ifndef RHPORT_DEVICE_SPEED
|
||||
RHPORT_DEVICE_SPEED = OPT_MODE_HIGH_SPEED
|
||||
endif
|
||||
|
||||
ifndef RHPORT_HOST_SPEED
|
||||
RHPORT_HOST_SPEED = OPT_MODE_HIGH_SPEED
|
||||
endif
|
||||
|
||||
# --------------
|
||||
# Compiler Flags
|
||||
# --------------
|
||||
CFLAGS += \
|
||||
-DCFG_TUSB_MCU=OPT_MCU_STM32N6 \
|
||||
-DBOARD_TUD_RHPORT=${RHPORT_DEVICE} \
|
||||
-DBOARD_TUD_MAX_SPEED=${RHPORT_DEVICE_SPEED} \
|
||||
-DBOARD_TUH_RHPORT=${RHPORT_HOST} \
|
||||
-DBOARD_TUH_MAX_SPEED=${RHPORT_HOST_SPEED} \
|
||||
-DSEGGER_RTT_SECTION=\"noncacheable_buffer\" \
|
||||
-DBUFFER_SIZE_UP=0x3000 \
|
||||
|
||||
# GCC Flags
|
||||
CFLAGS_GCC += \
|
||||
-flto \
|
||||
|
||||
# suppress warning caused by vendor mcu driver
|
||||
CFLAGS_GCC += \
|
||||
-Wno-error=cast-align \
|
||||
-Wno-error=unused-parameter \
|
||||
|
||||
LDFLAGS_GCC += \
|
||||
-nostdlib -nostartfiles \
|
||||
--specs=nosys.specs --specs=nano.specs
|
||||
|
||||
# -----------------
|
||||
# Sources & Include
|
||||
# -----------------
|
||||
|
||||
SRC_C += \
|
||||
src/portable/synopsys/dwc2/dcd_dwc2.c \
|
||||
src/portable/synopsys/dwc2/hcd_dwc2.c \
|
||||
src/portable/synopsys/dwc2/dwc2_common.c \
|
||||
$(ST_CMSIS)/Source/Templates/system_${ST_PREFIX}_fsbl.c \
|
||||
$(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal.c \
|
||||
$(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_cortex.c \
|
||||
$(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_dma.c \
|
||||
$(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_gpio.c \
|
||||
$(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_hcd.c \
|
||||
$(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_i2c.c \
|
||||
$(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_pcd.c \
|
||||
$(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_pcd_ex.c \
|
||||
$(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_pwr.c \
|
||||
$(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_pwr_ex.c \
|
||||
$(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_rcc.c \
|
||||
$(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_rcc_ex.c \
|
||||
$(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_rif.c \
|
||||
$(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_uart.c \
|
||||
$(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_uart_ex.c \
|
||||
$(ST_HAL_DRIVER)/Src/${ST_PREFIX}_ll_usb.c \
|
||||
|
||||
INC += \
|
||||
$(TOP)/$(BOARD_PATH) \
|
||||
$(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
|
||||
$(TOP)/$(ST_CMSIS)/Include \
|
||||
$(TOP)/$(ST_HAL_DRIVER)/Inc
|
||||
|
||||
# Startup
|
||||
SRC_S_GCC += $(ST_CMSIS)/Source/Templates/gcc/startup_$(MCU_VARIANT)_fsbl.s
|
||||
SRC_S_IAR += $(ST_CMSIS)/Source/Templates/iar/startup_$(MCU_VARIANT).s
|
||||
|
||||
# Linker
|
||||
LD_FILE_GCC ?= $(ST_CMSIS)/Source/Templates/gcc/linker/$(MCU_VARIANT)_flash.ld
|
||||
LD_FILE_IAR ?= $(ST_CMSIS)/Source/Templates/iar/linker/$(MCU_VARIANT)_flash.icf
|
||||
@@ -0,0 +1,792 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file partition_stm32n657xx.h
|
||||
* @author MCD Application Team
|
||||
* @brief CMSIS STM32N657xx Device Initial Setup for Secure / Non-Secure Zones
|
||||
* for ARMCM55 based on CMSIS CORE V5.3.1 partition_ARMCM33.h Template.
|
||||
*
|
||||
* This file contains:
|
||||
* - Initialize Security Attribution Unit (SAU) CTRL register
|
||||
* - Setup behavior of Sleep and Exception Handling
|
||||
* - Setup behavior of Floating Point Unit
|
||||
* - Setup Interrupt Target
|
||||
*
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2016 ARM Limited. All rights reserved.
|
||||
* Portions Copyright (c) 2023 STMicroelectronics, all rights reserved
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef PARTITION_STM32N657XX_H
|
||||
#define PARTITION_STM32N657XX_H
|
||||
|
||||
/*
|
||||
//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
|
||||
*/
|
||||
|
||||
/*
|
||||
// <e>Initialize Security Attribution Unit (SAU) CTRL register
|
||||
*/
|
||||
#define SAU_INIT_CTRL 0
|
||||
|
||||
/*
|
||||
// <q> Enable SAU
|
||||
// <i> Value for SAU->CTRL register bit ENABLE
|
||||
*/
|
||||
#define SAU_INIT_CTRL_ENABLE 0
|
||||
|
||||
/*
|
||||
// <o> When SAU is disabled
|
||||
// <0=> All Memory is Secure
|
||||
// <1=> All Memory is Non-Secure
|
||||
// <i> Value for SAU->CTRL register bit ALLNS
|
||||
// <i> When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration.
|
||||
*/
|
||||
#define SAU_INIT_CTRL_ALLNS 0
|
||||
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// <h>Initialize Security Attribution Unit (SAU) Address Regions
|
||||
// <i>SAU configuration specifies regions to be one of:
|
||||
// <i> - Secure and Non-Secure Callable
|
||||
// <i> - Non-Secure
|
||||
// <i>Note: All memory regions not configured by SAU are Secure
|
||||
*/
|
||||
#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */
|
||||
|
||||
/*
|
||||
// <e>Initialize SAU Region 0
|
||||
// <i> Setup SAU Region 0 memory attributes
|
||||
*/
|
||||
#define SAU_INIT_REGION0 0
|
||||
|
||||
/*
|
||||
// <o>Start Address <0-0xFFFFFFE0>
|
||||
*/
|
||||
#define SAU_INIT_START0 0x00000000 /* start address of SAU region 0 */
|
||||
|
||||
/*
|
||||
// <o>End Address <0x1F-0xFFFFFFFF>
|
||||
*/
|
||||
#define SAU_INIT_END0 0x00000000 /* end address of SAU region 0 */
|
||||
|
||||
/*
|
||||
// <o>Region is
|
||||
// <0=>Non-Secure
|
||||
// <1=>Secure, Non-Secure Callable
|
||||
*/
|
||||
#define SAU_INIT_NSC0 0
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// <e>Initialize SAU Region 1
|
||||
// <i> Setup SAU Region 1 memory attributes
|
||||
*/
|
||||
#define SAU_INIT_REGION1 0
|
||||
|
||||
/*
|
||||
// <o>Start Address <0-0xFFFFFFE0>
|
||||
*/
|
||||
#define SAU_INIT_START1 0x00000000 /* start address of SAU region 1 */
|
||||
|
||||
/*
|
||||
// <o>End Address <0x1F-0xFFFFFFFF>
|
||||
*/
|
||||
#define SAU_INIT_END1 0x00000000 /* end address of SAU region 1 */
|
||||
|
||||
/*
|
||||
// <o>Region is
|
||||
// <0=>Non-Secure
|
||||
// <1=>Secure, Non-Secure Callable
|
||||
*/
|
||||
#define SAU_INIT_NSC1 0
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// <e>Initialize SAU Region 2
|
||||
// <i> Setup SAU Region 2 memory attributes
|
||||
*/
|
||||
#define SAU_INIT_REGION2 0
|
||||
|
||||
/*
|
||||
// <o>Start Address <0-0xFFFFFFE0>
|
||||
*/
|
||||
#define SAU_INIT_START2 0x00000000 /* start address of SAU region 2 */
|
||||
|
||||
/*
|
||||
// <o>End Address <0x1F-0xFFFFFFFF>
|
||||
*/
|
||||
#define SAU_INIT_END2 0x00000000 /* end address of SAU region 2 */
|
||||
|
||||
/*
|
||||
// <o>Region is
|
||||
// <0=>Non-Secure
|
||||
// <1=>Secure, Non-Secure Callable
|
||||
*/
|
||||
#define SAU_INIT_NSC2 0
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// <e>Initialize SAU Region 3
|
||||
// <i> Setup SAU Region 3 memory attributes
|
||||
*/
|
||||
#define SAU_INIT_REGION3 0
|
||||
|
||||
/*
|
||||
// <o>Start Address <0-0xFFFFFFE0>
|
||||
*/
|
||||
#define SAU_INIT_START3 0x00000000 /* start address of SAU region 3 */
|
||||
|
||||
/*
|
||||
// <o>End Address <0x1F-0xFFFFFFFF>
|
||||
*/
|
||||
#define SAU_INIT_END3 0x00000000 /* end address of SAU region 3 */
|
||||
|
||||
/*
|
||||
// <o>Region is
|
||||
// <0=>Non-Secure
|
||||
// <1=>Secure, Non-Secure Callable
|
||||
*/
|
||||
#define SAU_INIT_NSC3 0
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// <e>Initialize SAU Region 4
|
||||
// <i> Setup SAU Region 4 memory attributes
|
||||
*/
|
||||
#define SAU_INIT_REGION4 0
|
||||
|
||||
/*
|
||||
// <o>Start Address <0-0xFFFFFFE0>
|
||||
*/
|
||||
#define SAU_INIT_START4 0x00000000 /* start address of SAU region 4 */
|
||||
|
||||
/*
|
||||
// <o>End Address <0x1F-0xFFFFFFFF>
|
||||
*/
|
||||
#define SAU_INIT_END4 0x00000000 /* end address of SAU region 4 */
|
||||
|
||||
/*
|
||||
// <o>Region is
|
||||
// <0=>Non-Secure
|
||||
// <1=>Secure, Non-Secure Callable
|
||||
*/
|
||||
#define SAU_INIT_NSC4 0
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// <e>Initialize SAU Region 5
|
||||
// <i> Setup SAU Region 5 memory attributes
|
||||
*/
|
||||
#define SAU_INIT_REGION5 0
|
||||
|
||||
/*
|
||||
// <o>Start Address <0-0xFFFFFFE0>
|
||||
*/
|
||||
#define SAU_INIT_START5 0x00000000 /* start address of SAU region 5 */
|
||||
|
||||
/*
|
||||
// <o>End Address <0x1F-0xFFFFFFFF>
|
||||
*/
|
||||
#define SAU_INIT_END5 0x00000000 /* end address of SAU region 5 */
|
||||
|
||||
/*
|
||||
// <o>Region is
|
||||
// <0=>Non-Secure
|
||||
// <1=>Secure, Non-Secure Callable
|
||||
*/
|
||||
#define SAU_INIT_NSC5 0
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// <e>Initialize SAU Region 6
|
||||
// <i> Setup SAU Region 6 memory attributes
|
||||
*/
|
||||
#define SAU_INIT_REGION6 0
|
||||
|
||||
/*
|
||||
// <o>Start Address <0-0xFFFFFFE0>
|
||||
*/
|
||||
#define SAU_INIT_START6 0x00000000 /* start address of SAU region 6 */
|
||||
|
||||
/*
|
||||
// <o>End Address <0x1F-0xFFFFFFFF>
|
||||
*/
|
||||
#define SAU_INIT_END6 0x00000000 /* end address of SAU region 6 */
|
||||
|
||||
/*
|
||||
// <o>Region is
|
||||
// <0=>Non-Secure
|
||||
// <1=>Secure, Non-Secure Callable
|
||||
*/
|
||||
#define SAU_INIT_NSC6 0
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// <e>Initialize SAU Region 7
|
||||
// <i> Setup SAU Region 7 memory attributes
|
||||
*/
|
||||
#define SAU_INIT_REGION7 0
|
||||
|
||||
/*
|
||||
// <o>Start Address <0-0xFFFFFFE0>
|
||||
*/
|
||||
#define SAU_INIT_START7 0x00000000 /* start address of SAU region 7 */
|
||||
|
||||
/*
|
||||
// <o>End Address <0x1F-0xFFFFFFFF>
|
||||
*/
|
||||
#define SAU_INIT_END7 0x00000000 /* end address of SAU region 7 */
|
||||
|
||||
/*
|
||||
// <o>Region is
|
||||
// <0=>Non-Secure
|
||||
// <1=>Secure, Non-Secure Callable
|
||||
*/
|
||||
#define SAU_INIT_NSC7 0
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// </h>
|
||||
*/
|
||||
|
||||
/*
|
||||
// <e>Setup behaviour of Sleep and Exception Handling
|
||||
*/
|
||||
#define SCB_CSR_AIRCR_INIT 0
|
||||
|
||||
/*
|
||||
// <o> Deep Sleep can be enabled by
|
||||
// <0=>Secure and Non-Secure state
|
||||
// <1=>Secure state only
|
||||
// <i> Value for SCB->CSR register bit DEEPSLEEPS
|
||||
*/
|
||||
#define SCB_CSR_DEEPSLEEPS_VAL 0
|
||||
|
||||
/*
|
||||
// <o>System reset request accessible from
|
||||
// <0=> Secure and Non-Secure state
|
||||
// <1=> Secure state only
|
||||
// <i> Value for SCB->AIRCR register bit SYSRESETREQS
|
||||
*/
|
||||
#define SCB_AIRCR_SYSRESETREQS_VAL 0
|
||||
|
||||
/*
|
||||
// <o>Priority of Non-Secure exceptions is
|
||||
// <0=> Not altered
|
||||
// <1=> Lowered to 0x04-0x07
|
||||
// <i> Value for SCB->AIRCR register bit PRIS
|
||||
*/
|
||||
#define SCB_AIRCR_PRIS_VAL 0
|
||||
|
||||
/*
|
||||
// <o>BusFault, HardFault, and NMI target
|
||||
// <0=> Secure state
|
||||
// <1=> Non-Secure state
|
||||
// <i> Value for SCB->AIRCR register bit BFHFNMINS
|
||||
*/
|
||||
#define SCB_AIRCR_BFHFNMINS_VAL 0
|
||||
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// <e>Setup behaviour of Floating Point Unit
|
||||
*/
|
||||
#define TZ_FPU_NS_USAGE 1
|
||||
|
||||
/*
|
||||
// <o>Floating Point Unit usage
|
||||
// <0=> Secure state only
|
||||
// <3=> Secure and Non-Secure state
|
||||
// <i> Value for SCB->NSACR register bits CP10, CP11
|
||||
*/
|
||||
#define SCB_NSACR_CP10_11_VAL 3
|
||||
|
||||
/*
|
||||
// <o>Treat floating-point registers as Secure
|
||||
// <0=> Disabled
|
||||
// <1=> Enabled
|
||||
// <i> Value for FPU->FPCCR register bit TS
|
||||
*/
|
||||
#define FPU_FPCCR_TS_VAL 0
|
||||
|
||||
/*
|
||||
// <o>Clear on return (CLRONRET) accessibility
|
||||
// <0=> Secure and Non-Secure state
|
||||
// <1=> Secure state only
|
||||
// <i> Value for FPU->FPCCR register bit CLRONRETS
|
||||
*/
|
||||
#define FPU_FPCCR_CLRONRETS_VAL 0
|
||||
|
||||
/*
|
||||
// <o>Clear floating-point caller saved registers on exception return
|
||||
// <0=> Disabled
|
||||
// <1=> Enabled
|
||||
// <i> Value for FPU->FPCCR register bit CLRONRET
|
||||
*/
|
||||
#define FPU_FPCCR_CLRONRET_VAL 1
|
||||
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// <h>Setup Interrupt Target
|
||||
*/
|
||||
|
||||
/*
|
||||
// <e>Initialize ITNS 0 (Interrupts 0..31)
|
||||
*/
|
||||
#define NVIC_INIT_ITNS0 1
|
||||
|
||||
/*
|
||||
// Interrupts 0..31
|
||||
// <o.0> PVD_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.1> Reserved <0=> Secure state <1=> Non-Secure state
|
||||
// <o.2> DTS_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.3> RCC_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.4> LOCKUP_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.5> CACHE_ECC_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.6> TCM_ECC_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.7> BKP_ECC_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.8> FPU_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.9> Reserved <0=> Secure state <1=> Non-Secure state
|
||||
// <o.10> RTC_S_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.11> TAMP_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.12> RIFSC_TAMPER_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.13> IAC_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.14> RCC_S_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.15> Reserved <0=> Secure state <1=> Non-Secure state
|
||||
// <o.16> RTC_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.17> Reserved <0=> Secure state <1=> Non-Secure state
|
||||
// <o.18> IWDG_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.19> WWDG_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.20> EXTI0_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.21> EXTI1_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.22> EXTI2_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.23> EXTI3_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.24> EXTI4_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.25> EXTI5_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.26> EXTI6_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.27> EXTI7_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.28> EXTI8_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.29> EXTI9_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.30> EXTI10_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.31> EXTI11_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
*/
|
||||
#define NVIC_INIT_ITNS0_VAL 0x00000000
|
||||
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// <e>Initialize ITNS 1 (Interrupts 32..63)
|
||||
*/
|
||||
#define NVIC_INIT_ITNS1 1
|
||||
|
||||
/*
|
||||
// Interrupts 32..63
|
||||
// <o.0> EXTI12_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.1> EXTI13_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.2> EXTI14_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.3> EXTI15_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.4> SAES_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.5> CRYP_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.6> PKA_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.7> HASH_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.8> RNG_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.9> Reserved <0=> Secure state <1=> Non-Secure state
|
||||
// <o.10> MCE1_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.11> MCE2_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.12> MCE3_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.13> MCE4_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.14> ADC1_2_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.15> CSI_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.16> DCMIPP_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.17> Reserved <0=> Secure state <1=> Non-Secure state
|
||||
// <o.18> Reserved <0=> Secure state <1=> Non-Secure state
|
||||
// <o.19> Reserved <0=> Secure state <1=> Non-Secure state
|
||||
// <o.20> PAHB_ERR_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.21> NPU0_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.22> NPU1_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.23> NPU2_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.24> NPU3_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.25> CACHEAXI_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.26> LTDC_LO_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.27> LTDC_LO_ERR_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.28> DMA2D_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.29> JPEG_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.30> VENC_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.31> GFXMMU_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
*/
|
||||
#define NVIC_INIT_ITNS1_VAL 0x00000000
|
||||
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// <e>Initialize ITNS 2 (Interrupts 64..95)
|
||||
*/
|
||||
#define NVIC_INIT_ITNS2 1
|
||||
|
||||
/*
|
||||
// Interrupts 64..95
|
||||
// <o.0> GFXTIM_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.1> GPU2D_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.2> GPU2D_ER_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.3> ICACHE_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.4> HPDMA1_Channel0_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.5> HPDMA1_Channel1_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.6> HPDMA1_Channel2_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.7> HPDMA1_Channel3_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.8> HPDMA1_Channel4_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.9> HPDMA1_Channel5_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.10> HPDMA1_Channel6_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.11> HPDMA1_Channel7_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.12> HPDMA1_Channel8_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.13> HPDMA1_Channel9_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.14> HPDMA1_Channel10_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.15> HPDMA1_Channel11_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.16> HPDMA1_Channel12_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.17> HPDMA1_Channel13_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.18> HPDMA1_Channel14_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.19> HPDMA1_Channel15_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.20> GPDMA1_Channel0_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.21> GPDMA1_Channel1_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.22> GPDMA1_Channel2_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.23> GPDMA1_Channel3_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.24> GPDMA1_Channel4_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.25> GPDMA1_Channel5_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.26> GPDMA1_Channel6_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.27> GPDMA1_Channel7_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.28> GPDMA1_Channel8_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.29> GPDMA1_Channel9_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.30> GPDMA1_Channel10_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.31> GPDMA1_Channel11_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
*/
|
||||
#define NVIC_INIT_ITNS2_VAL 0x00000000
|
||||
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// <e>Initialize ITNS 3 (Interrupts 96..127)
|
||||
*/
|
||||
#define NVIC_INIT_ITNS3 1
|
||||
|
||||
/*
|
||||
// Interrupts 96..127
|
||||
// <o.0> GPDMA1_Channel12_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.1> GPDMA1_Channel13_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.2> GPDMA1_Channel14_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.3> GPDMA1_Channel15_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.4> I2C1_EV_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.5> I2C1_ER_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.6> I2C2_EV_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.7> I2C2_ER_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.8> I2C3_EV_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.9> I2C3_ER_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.10> I2C4_EV_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.11> I2C4_ER_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.12> I3C1_EV_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.13> I3C1_ER_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.14> I3C2_EV_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.15> I3C2_ER_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.16> TIM1_BRK_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.17> TIM1_UP_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.18> TIM1_TRG_COM_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.19> TIM1_CC_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.20> TIM2_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.21> TIM3_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.22> TIM4_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.23> TIM5_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.24> TIM6_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.25> TIM7_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.26> TIM8_BRK_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.27> TIM8_UP_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.28> TIM8_TRG_COM_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.29> TIM8_CC_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.30> TIM9_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.31> TIM10_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
|
||||
*/
|
||||
#define NVIC_INIT_ITNS3_VAL 0x00000000
|
||||
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// <e>Initialize ITNS 4 (Interrupts 128..159)
|
||||
*/
|
||||
#define NVIC_INIT_ITNS4 1
|
||||
|
||||
/*
|
||||
// Interrupts 128..159
|
||||
// <o.0> TIM11_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.1> TIM12_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.2> TIM13_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.3> TIM14_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.4> TIM15_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.5> TIM16_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.6> TIM17_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.7> TIM18_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.8> LPTIM1_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.9> LPTIM2_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.10> LPTIM3_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.11> LPTIM4_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.12> LPTIM5_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.13> ADF1_FLT0_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.14> MDF1_FLT0_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.15> MDF1_FLT1_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.16> MDF1_FLT2_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.17> MDF1_FLT3_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.18> MDF1_FLT4_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.19> MDF1_FLT5_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.20> SAI1_A_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.21> SAI1_B_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.22> SAI2_A_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.23> SAI2_B_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.24> SPDIFRX1_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.25> SPI1_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.26> SPI2_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.27> SPI3_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.28> SPI4_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.29> SPI5_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.30> SPI6_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.31> USART1_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
|
||||
*/
|
||||
#define NVIC_INIT_ITNS4_VAL 0x00000000
|
||||
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// <e>Initialize ITNS 5 (Interrupts 160..191)
|
||||
*/
|
||||
#define NVIC_INIT_ITNS5 1
|
||||
|
||||
/*
|
||||
// Interrupts 160..191
|
||||
// <o.0> USART2_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.1> USART3_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.2> UART4_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.3> UART5_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.4> USART6_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.5> UART7_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.6> UART8_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.7> UART9_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.8> USART10_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.9> LPUART1_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.10> XSPI1_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.11> XSPI2_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.12> XSPI3_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.13> FMC_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.14> SDMMC1_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.15> SDMMC2_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.16> UCPD1_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.17> USB1_OTG_HS_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.18> USB2_OTG_HS_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.19> ETH1_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.20> FDCAN1_IT0_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.21> FDCAN1_IT1_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.22> FDCAN2_IT0_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.23> FDCAN2_IT1_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.24> FDCAN3_IT0_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.25> FDCAN3_IT1_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.26> FDCAN_CU_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.27> MDIOS_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.28> DCMI_PSSI_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.29> WAKEUP_PIN_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.30> CTI_INT0_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.31> CTI_INT1_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
|
||||
*/
|
||||
#define NVIC_INIT_ITNS5_VAL 0x00000000
|
||||
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// <e>Initialize ITNS 6 (Interrupts 192..223)
|
||||
*/
|
||||
#define NVIC_INIT_ITNS6 1
|
||||
|
||||
/*
|
||||
// Interrupts 192..223
|
||||
// <o.0> Reserved <0=> Secure state <1=> Non-Secure state
|
||||
// <o.1> LTDC_UP_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
// <o.2> LTDC_UP_ERR_IRQn <0=> Secure state <1=> Non-Secure state
|
||||
|
||||
*/
|
||||
#define NVIC_INIT_ITNS6_VAL 0x00000000
|
||||
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// </h>
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/*
|
||||
max 8 SAU regions.
|
||||
SAU regions are defined in partition.h
|
||||
*/
|
||||
|
||||
#define SAU_INIT_REGION(n) \
|
||||
SAU->RNR = (n & SAU_RNR_REGION_Msk); \
|
||||
SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \
|
||||
SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \
|
||||
((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U
|
||||
|
||||
/**
|
||||
\brief Setup a SAU Region
|
||||
\details Writes the region information contained in SAU_Region to the
|
||||
registers SAU_RNR, SAU_RBAR, and SAU_RLAR
|
||||
*/
|
||||
__STATIC_INLINE void TZ_SAU_Setup (void)
|
||||
{
|
||||
|
||||
#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
|
||||
|
||||
#if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U)
|
||||
SAU_INIT_REGION(0);
|
||||
#endif
|
||||
|
||||
#if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U)
|
||||
SAU_INIT_REGION(1);
|
||||
#endif
|
||||
|
||||
#if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U)
|
||||
SAU_INIT_REGION(2);
|
||||
#endif
|
||||
|
||||
#if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U)
|
||||
SAU_INIT_REGION(3);
|
||||
#endif
|
||||
|
||||
#if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U)
|
||||
SAU_INIT_REGION(4);
|
||||
#endif
|
||||
|
||||
#if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U)
|
||||
SAU_INIT_REGION(5);
|
||||
#endif
|
||||
|
||||
#if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U)
|
||||
SAU_INIT_REGION(6);
|
||||
#endif
|
||||
|
||||
#if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U)
|
||||
SAU_INIT_REGION(7);
|
||||
#endif
|
||||
|
||||
/* repeat this for all possible SAU regions */
|
||||
|
||||
#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
|
||||
|
||||
|
||||
#if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U)
|
||||
SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) |
|
||||
((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ;
|
||||
#endif
|
||||
|
||||
#if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U)
|
||||
SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) |
|
||||
((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk);
|
||||
|
||||
SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk |
|
||||
SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk) ) |
|
||||
((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) |
|
||||
((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) |
|
||||
((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) |
|
||||
((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk);
|
||||
#endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */
|
||||
|
||||
#if defined (__FPU_USED) && (__FPU_USED == 1U) && \
|
||||
defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U)
|
||||
|
||||
SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) |
|
||||
((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk));
|
||||
|
||||
FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) |
|
||||
((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) |
|
||||
((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) |
|
||||
((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk );
|
||||
#endif
|
||||
|
||||
#if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U)
|
||||
NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL;
|
||||
#endif
|
||||
|
||||
#if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U)
|
||||
NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL;
|
||||
#endif
|
||||
|
||||
#if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U)
|
||||
NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL;
|
||||
#endif
|
||||
|
||||
#if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U)
|
||||
NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL;
|
||||
#endif
|
||||
|
||||
#if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U)
|
||||
NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL;
|
||||
#endif
|
||||
|
||||
#if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U)
|
||||
NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL;
|
||||
#endif
|
||||
|
||||
#if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U)
|
||||
NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL;
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
#endif /* PARTITION_STM32N657XX_H */
|
||||
@@ -0,0 +1,504 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32n6xx_hal_conf_template.h
|
||||
* @author MCD Application Team
|
||||
* @brief HAL configuration template file.
|
||||
* This file should be copied to the application folder and renamed
|
||||
* to stm32n6xx_hal_conf.h.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2023 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32N6xx_HAL_CONF_H
|
||||
#define STM32N6xx_HAL_CONF_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/* ########################## Module Selection ############################## */
|
||||
/**
|
||||
* @brief This is the list of modules to be used in the HAL driver
|
||||
*/
|
||||
#define HAL_MODULE_ENABLED
|
||||
/*#define HAL_ADC_MODULE_ENABLED */
|
||||
/*#define HAL_BSEC_MODULE_ENABLED */
|
||||
/*#define HAL_CRC_MODULE_ENABLED */
|
||||
/*#define HAL_CRYP_MODULE_ENABLED */
|
||||
/*#define HAL_DCMI_MODULE_ENABLED */
|
||||
/*#define HAL_DCMIPP_MODULE_ENABLED */
|
||||
/*#define HAL_DMA2D_MODULE_ENABLED */
|
||||
/*#define HAL_DTS_MODULE_ENABLED */
|
||||
/*#define HAL_ETH_MODULE_ENABLED */
|
||||
/*#define HAL_EXTI_MODULE_ENABLED */
|
||||
/*#define HAL_FDCAN_MODULE_ENABLED */
|
||||
/*#define HAL_GFXMMU_MODULE_ENABLED */
|
||||
/*#define HAL_GFXTIM_MODULE_ENABLED */
|
||||
/*#define HAL_HASH_MODULE_ENABLED */
|
||||
/*#define HAL_HCD_MODULE_ENABLED */
|
||||
#define HAL_I2C_MODULE_ENABLED
|
||||
/*#define HAL_I2S_MODULE_ENABLED */
|
||||
/*#define HAL_I3C_MODULE_ENABLED */
|
||||
/*#define HAL_ICACHE_MODULE_ENABLED */
|
||||
/*#define HAL_IRDA_MODULE_ENABLED */
|
||||
/*#define HAL_IWDG_MODULE_ENABLED */
|
||||
/*#define HAL_JPEG_MODULE_ENABLED */
|
||||
/*#define HAL_LPTIM_MODULE_ENABLED */
|
||||
/*#define HAL_LTDC_MODULE_ENABLED */
|
||||
/*#define HAL_MCE_MODULE_ENABLED */
|
||||
/*#define HAL_MDF_MODULE_ENABLED */
|
||||
/*#define HAL_MMC_MODULE_ENABLED */
|
||||
/*#define HAL_NAND_MODULE_ENABLED */
|
||||
/*#define HAL_NOR_MODULE_ENABLED */
|
||||
/*#define HAL_PCD_MODULE_ENABLED */
|
||||
/*#define HAL_PKA_MODULE_ENABLED */
|
||||
/*#define HAL_PSSI_MODULE_ENABLED */
|
||||
/*#define HAL_RAMCFG_MODULE_ENABLED */
|
||||
/*#define HAL_RIF_MODULE_ENABLED */
|
||||
/*#define HAL_RNG_MODULE_ENABLED */
|
||||
/*#define HAL_RTC_MODULE_ENABLED */
|
||||
/*#define HAL_SAI_MODULE_ENABLED */
|
||||
/*#define HAL_SD_MODULE_ENABLED */
|
||||
/*#define HAL_SDIO_MODULE_ENABLED */
|
||||
/*#define HAL_SDRAM_MODULE_ENABLED */
|
||||
/*#define HAL_SMARTCARD_MODULE_ENABLED*/
|
||||
/*#define HAL_SMBUS_MODULE_ENABLED */
|
||||
/*#define HAL_SPDIFRX_MODULE_ENABLED */
|
||||
/*#define HAL_SPI_MODULE_ENABLED */
|
||||
/*#define HAL_SRAM_MODULE_ENABLED */
|
||||
/*#define HAL_TIM_MODULE_ENABLED */
|
||||
#define HAL_UART_MODULE_ENABLED
|
||||
/*#define HAL_USART_MODULE_ENABLED */
|
||||
/*#define HAL_WWDG_MODULE_ENABLED */
|
||||
/*#define HAL_XSPI_MODULE_ENABLED */
|
||||
/*#define HAL_CACHEAXI_MODULE_ENABLED */
|
||||
/*#define HAL_MDIOS_MODULE_ENABLED */
|
||||
/*#define HAL_GPU2D_MODULE_ENABLED */
|
||||
/*#define HAL_CACHEAXI_MODULE_ENABLED */
|
||||
#define HAL_GPIO_MODULE_ENABLED
|
||||
#define HAL_EXTI_MODULE_ENABLED
|
||||
#define HAL_DMA_MODULE_ENABLED
|
||||
#define HAL_RCC_MODULE_ENABLED
|
||||
#define HAL_PWR_MODULE_ENABLED
|
||||
#define HAL_CORTEX_MODULE_ENABLED
|
||||
|
||||
/* ########################## Oscillator Values adaptation ####################*/
|
||||
/**
|
||||
* @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
|
||||
* This value is used by the RCC HAL module to compute the system frequency
|
||||
* (when HSE is used as system clock source, directly or through the PLL).
|
||||
*/
|
||||
#if !defined (HSE_VALUE)
|
||||
#define HSE_VALUE 48000000UL /*!< Value of the External oscillator in Hz */
|
||||
#endif /* HSE_VALUE */
|
||||
|
||||
#if !defined (HSE_STARTUP_TIMEOUT)
|
||||
#define HSE_STARTUP_TIMEOUT 100UL /*!< Time out for HSE start up, in ms */
|
||||
#endif /* HSE_STARTUP_TIMEOUT */
|
||||
|
||||
/**
|
||||
* @brief External Low Speed oscillator (LSE) value.
|
||||
* This value is used by the UART, RTC HAL module to compute the system frequency
|
||||
*/
|
||||
#if !defined (LSE_VALUE)
|
||||
#define LSE_VALUE 32768UL /*!< Value of the External oscillator in Hz */
|
||||
#endif /* LSE_VALUE */
|
||||
|
||||
#if !defined (LSE_STARTUP_TIMEOUT)
|
||||
#define LSE_STARTUP_TIMEOUT 5000UL /*!< Time out for LSE start up, in ms */
|
||||
#endif /* LSE_STARTUP_TIMEOUT */
|
||||
|
||||
/**
|
||||
* @brief Internal Multiple Speed oscillator (MSI) default value.
|
||||
* This value is the default MSI range value after Reset.
|
||||
*/
|
||||
#if !defined (MSI_VALUE)
|
||||
#define MSI_VALUE 4000000UL /*!< Value of the Internal oscillator in Hz */
|
||||
#endif /* MSI_VALUE */
|
||||
|
||||
/**
|
||||
* @brief Internal High Speed oscillator (HSI) value.
|
||||
* This value is used by the RCC HAL module to compute the system frequency
|
||||
* (when HSI is used as system clock source, directly or through the PLL).
|
||||
*/
|
||||
#if !defined (HSI_VALUE)
|
||||
#define HSI_VALUE 64000000UL /*!< Value of the Internal oscillator in Hz */
|
||||
#endif /* HSI_VALUE */
|
||||
|
||||
/**
|
||||
* @brief Internal Low Speed oscillator (LSI) value.
|
||||
*/
|
||||
#if !defined (LSI_VALUE)
|
||||
#define LSI_VALUE 32000UL /*!< LSI Typical Value in Hz */
|
||||
#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz */
|
||||
/* The real value may vary depending on the variations in voltage and temperature.*/
|
||||
|
||||
/* Tip: To avoid modifying this file each time you need to use different HSE,
|
||||
=== you can define the HSE value in your toolchain compiler preprocessor. */
|
||||
|
||||
/* ########################### System Configuration ######################### */
|
||||
/**
|
||||
* @brief This is the HAL system configuration section
|
||||
*/
|
||||
#define VDD_VALUE 3300UL /*!< Value of VDD in mv */
|
||||
#define TICK_INT_PRIORITY 15U /*!< tick interrupt priority (lowest by default) */
|
||||
#define USE_RTOS 0U
|
||||
|
||||
/* ########################## Assert Selection ############################## */
|
||||
/**
|
||||
* @brief Uncomment the line below to expanse the "assert_param" macro in the
|
||||
* HAL drivers code
|
||||
*/
|
||||
/* #define USE_FULL_ASSERT 1U */
|
||||
|
||||
/* ################## Register callback feature configuration ############### */
|
||||
/**
|
||||
* @brief Set below the peripheral configuration to "1U" to add the support
|
||||
* of HAL callback registration/unregistration feature for the HAL
|
||||
* driver(s). This allows user application to provide specific callback
|
||||
* functions thanks to HAL_PPP_RegisterCallback() rather than overwriting
|
||||
* the default weak callback functions (see each stm32n6xx_hal_ppp.h file
|
||||
* for possible callback identifiers defined in HAL_PPP_CallbackIDTypeDef
|
||||
* for each PPP peripheral).
|
||||
*/
|
||||
#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */
|
||||
#define USE_HAL_CACHEAXI_REGISTER_CALLBACKS 0U /* CACHEAXI register callback disabled */
|
||||
#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */
|
||||
#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */
|
||||
#define USE_HAL_DCMIPP_REGISTER_CALLBACKS 0U /* DCMIPP register callback disabled */
|
||||
#define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U /* DMA2D register callback disabled */
|
||||
#define USE_HAL_DTS_REGISTER_CALLBACKS 0U /* DTS register callback disabled */
|
||||
#define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */
|
||||
#define USE_HAL_FDCAN_REGISTER_CALLBACKS 0U /* FDCAN register callback disabled */
|
||||
#define USE_HAL_GFXMMU_REGISTER_CALLBACKS 0U /* GFXMMU register callback disabled */
|
||||
#define USE_HAL_GFXTIM_REGISTER_CALLBACKS 0U /* GFXTIM register callback disabled */
|
||||
#define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */
|
||||
#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */
|
||||
#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */
|
||||
#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */
|
||||
#define USE_HAL_I3C_REGISTER_CALLBACKS 0U /* I3C register callback disabled */
|
||||
#define USE_HAL_IWDG_REGISTER_CALLBACKS 0U /* IWDG register callback disabled */
|
||||
#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */
|
||||
#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */
|
||||
#define USE_HAL_LTDC_REGISTER_CALLBACKS 0U /* LTDC register callback disabled */
|
||||
#define USE_HAL_MCE_REGISTER_CALLBACKS 0U /* MCE register callback disabled */
|
||||
#define USE_HAL_MDF_REGISTER_CALLBACKS 0U /* MDF register callback disabled */
|
||||
#define USE_HAL_MMC_REGISTER_CALLBACKS 0U /* MMC register callback disabled */
|
||||
#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */
|
||||
#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */
|
||||
#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */
|
||||
#define USE_HAL_PKA_REGISTER_CALLBACKS 0U /* PKA register callback disabled */
|
||||
#define USE_HAL_PSSI_REGISTER_CALLBACKS 0U /* PSSI register callback disabled */
|
||||
#define USE_HAL_RAMCFG_REGISTER_CALLBACKS 0U /* RAMCFG register callback disabled */
|
||||
#define USE_HAL_RNG_REGISTER_CALLBACKS 0U /* RNG register callback disabled */
|
||||
#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */
|
||||
#define USE_HAL_SAI_REGISTER_CALLBACKS 0U /* SAI register callback disabled */
|
||||
#define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */
|
||||
#define USE_HAL_SDIO_REGISTER_CALLBACKS 0U /* SDIO register callback disabled */
|
||||
#define USE_HAL_SDRAM_REGISTER_CALLBACKS 0U /* SDRAM register callback disabled */
|
||||
#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */
|
||||
#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */
|
||||
#define USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */
|
||||
#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */
|
||||
#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */
|
||||
#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */
|
||||
#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */
|
||||
#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */
|
||||
#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */
|
||||
#define USE_HAL_XSPI_REGISTER_CALLBACKS 0U /* XSPI register callback disabled */
|
||||
|
||||
/* ################## SPI peripheral configuration ########################## */
|
||||
|
||||
/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
|
||||
* Activated: CRC code is present inside driver
|
||||
* Deactivated: CRC code cleaned from driver
|
||||
*/
|
||||
#define USE_SPI_CRC 0U
|
||||
|
||||
/* ################## SDMMC peripheral configuration ######################### */
|
||||
|
||||
#define USE_SD_TRANSCEIVER 0U
|
||||
|
||||
/* ################## SDIO peripheral configuration ########################## */
|
||||
#define USE_SDIO_TRANSCEIVER 1U
|
||||
#define SDIO_MAX_IO_NUMBER 7U /*!< SDIO device support maximum IO number */
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
/**
|
||||
* @brief Include module's header file
|
||||
*/
|
||||
#ifdef HAL_RCC_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_rcc.h"
|
||||
#endif /* HAL_RCC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_GPIO_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_gpio.h"
|
||||
#endif /* HAL_GPIO_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_RIF_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_rif.h"
|
||||
#endif /* HAL_RIF_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_DMA_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_dma.h"
|
||||
#endif /* HAL_DMA_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_CACHEAXI_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_cacheaxi.h"
|
||||
#endif /* HAL_CACHEAXI_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_CORTEX_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_cortex.h"
|
||||
#endif /* HAL_CORTEX_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_ADC_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_adc.h"
|
||||
#endif /* HAL_ADC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_BSEC_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_bsec.h"
|
||||
#endif /* HAL_BSEC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_CRC_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_crc.h"
|
||||
#endif /* HAL_CRC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_CRYP_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_cryp.h"
|
||||
#endif /* HAL_CRYP_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_DCMI_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_dcmi.h"
|
||||
#endif /* HAL_DCMI_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_DCMIPP_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_dcmipp.h"
|
||||
#endif /* HAL_DCMIPP_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_DMA2D_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_dma2d.h"
|
||||
#endif /* HAL_DMA2D_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_DTS_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_dts.h"
|
||||
#endif /* HAL_DTS_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_ETH_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_eth.h"
|
||||
#endif /* HAL_ETH_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_EXTI_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_exti.h"
|
||||
#endif /* HAL_EXTI_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_FDCAN_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_fdcan.h"
|
||||
#endif /* HAL_FDCAN_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_GFXMMU_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_gfxmmu.h"
|
||||
#endif /* HAL_GFXMMU_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_GFXTIM_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_gfxtim.h"
|
||||
#endif /* HAL_GFXTIM_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_GPIO_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_gpio.h"
|
||||
#endif /* HAL_GPIO_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_GPU2D_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_gpu2d.h"
|
||||
#endif /* HAL_GPU2D_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_HASH_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_hash.h"
|
||||
#endif /* HAL_HASH_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_HCD_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_hcd.h"
|
||||
#endif /* HAL_HCD_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_I2C_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_i2c.h"
|
||||
#endif /* HAL_I2C_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_I2S_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_i2s.h"
|
||||
#endif /* HAL_I2S_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_I3C_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_i3c.h"
|
||||
#endif /* HAL_I3C_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_ICACHE_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_icache.h"
|
||||
#endif /* HAL_ICACHE_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_IRDA_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_irda.h"
|
||||
#endif /* HAL_IRDA_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_IWDG_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_iwdg.h"
|
||||
#endif /* HAL_IWDG_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_JPEG_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_jpeg.h"
|
||||
#endif /* HAL_JPEG_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_LPTIM_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_lptim.h"
|
||||
#endif /* HAL_LPTIM_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_LTDC_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_ltdc.h"
|
||||
#endif /* HAL_LTDC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_MCE_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_mce.h"
|
||||
#endif /* HAL_MCE_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_MDF_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_mdf.h"
|
||||
#endif /* HAL_MDF_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_MDIOS_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_mdios.h"
|
||||
#endif /* HAL_MDIOS_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_MMC_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_mmc.h"
|
||||
#endif /* HAL_MMC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_NAND_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_nand.h"
|
||||
#endif /* HAL_NAND_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_NOR_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_nor.h"
|
||||
#endif /* HAL_NOR_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_NAND_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_nand.h"
|
||||
#endif /* HAL_NAND_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_PCD_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_pcd.h"
|
||||
#endif /* HAL_PCD_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_PKA_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_pka.h"
|
||||
#endif /* HAL_PKA_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_PSSI_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_pssi.h"
|
||||
#endif /* HAL_PSSI_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_PWR_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_pwr.h"
|
||||
#endif /* HAL_PWR_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_RAMCFG_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_ramcfg.h"
|
||||
#endif /* HAL_RAMCFG_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_RNG_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_rng.h"
|
||||
#endif /* HAL_RNG_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_RTC_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_rtc.h"
|
||||
#endif /* HAL_RTC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SAI_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_sai.h"
|
||||
#endif /* HAL_SAI_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SD_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_sd.h"
|
||||
#endif /* HAL_SD_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SDIO_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_sdio.h"
|
||||
#endif /* HAL_SDIO_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SDRAM_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_sdram.h"
|
||||
#endif /* HAL_SDRAM_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SMARTCARD_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_smartcard.h"
|
||||
#endif /* HAL_SMARTCARD_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SMBUS_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_smbus.h"
|
||||
#endif /* HAL_SMBUS_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SPDIFRX_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_spdifrx.h"
|
||||
#endif /* HAL_SPDIFRX_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SPI_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_spi.h"
|
||||
#endif /* HAL_SPI_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SRAM_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_sram.h"
|
||||
#endif /* HAL_SRAM_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_TIM_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_tim.h"
|
||||
#endif /* HAL_TIM_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_UART_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_uart.h"
|
||||
#endif /* HAL_UART_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_USART_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_usart.h"
|
||||
#endif /* HAL_USART_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_WWDG_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_wwdg.h"
|
||||
#endif /* HAL_WWDG_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_XSPI_MODULE_ENABLED
|
||||
#include "stm32n6xx_hal_xspi.h"
|
||||
#endif /* HAL_XSPI_MODULE_ENABLED */
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
#ifdef USE_FULL_ASSERT
|
||||
/**
|
||||
* @brief The assert_param macro is used for function's parameters check.
|
||||
* @param expr: If expr is false, it calls assert_failed function
|
||||
* which reports the name of the source file and the source
|
||||
* line number of the call that failed.
|
||||
* If expr is true, it returns no value.
|
||||
* @retval None
|
||||
*/
|
||||
#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
void assert_failed(uint8_t *file, uint32_t line);
|
||||
#else
|
||||
#define assert_param(expr) ((void)0U)
|
||||
#endif /* USE_FULL_ASSERT */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32N6xx_HAL_CONF_H */
|
||||
Reference in New Issue
Block a user