Initial project setup
This commit is contained in:
@@ -0,0 +1,11 @@
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set(MCU_VARIANT LPC18S37)
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set(JLINK_DEVICE LPC18S37)
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set(PYOCD_TARGET LPC18S37)
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set(NXPLINK_DEVICE LPC18S37:LPCXPRESSO18S37)
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set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/lpc1837.ld)
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function(update_board TARGET)
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# nothing to do
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endfunction()
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@@ -0,0 +1,83 @@
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/*
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* The MIT License (MIT)
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*
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* Copyright (c) 2021, Ha Thach (tinyusb.org)
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*
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* This file is part of the TinyUSB stack.
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*/
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/* metadata:
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name: LPCXpresso18s37
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url: https://www.nxp.com/design/design-center/software/development-software/mcuxpresso-software-and-tools-/lpcxpresso-boards/lpcxpresso18s37-development-board:OM13076
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*/
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#ifndef BOARD_H_
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#define BOARD_H_
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// Note: For USB Host demo, install JP4
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// WARNING: don't install JP4 when running as device
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#ifdef __cplusplus
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extern "C" {
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#endif
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// LED Red
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#define LED_PORT 3
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#define LED_PIN 7
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// ISP Button
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#define BUTTON_PORT 0
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#define BUTTON_PIN 7
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#define UART_DEV LPC_USART0
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static inline void board_lpc18_pinmux(void)
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{
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const PINMUX_GRP_T pinmuxing[] =
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{
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// LEDs
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{ 0x6, 9 , SCU_MODE_INBUFF_EN | SCU_MODE_PULLUP | SCU_MODE_FUNC0 },
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{ 0x6, 11, SCU_MODE_INBUFF_EN | SCU_MODE_PULLUP | SCU_MODE_FUNC0 },
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// Button
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{ 0x2, 7, SCU_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC0 },
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// UART
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{ 0x06, 4, SCU_MODE_PULLDOWN | SCU_MODE_FUNC2 },
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{ 0x02, 1, SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC1 },
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// USB0
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//{ 0x6, 3, SCU_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_FUNC1 }, // P6_3 USB0_PWR_EN, USB0 VBus function
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// USB1
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//{ 0x9, 5, SCU_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_FUNC2 }, // P9_5 USB1_VBUS_EN, USB1 VBus function
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//{ 0x2, 5, SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC2 }, // P2_5 USB1_VBUS, MUST CONFIGURE THIS SIGNAL FOR USB1 NORMAL OPERATION
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{0x2, 5, SCU_MODE_INBUFF_EN | SCU_MODE_PULLUP | SCU_MODE_FUNC4 },
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};
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Chip_SCU_SetPinMuxing(pinmuxing, sizeof(pinmuxing) / sizeof(PINMUX_GRP_T));
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}
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#ifdef __cplusplus
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}
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#endif
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#endif
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@@ -0,0 +1,6 @@
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LD_FILE = $(BOARD_PATH)/lpc1837.ld
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# For flash-jlink target
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JLINK_DEVICE = LPC18S37
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flash: flash-jlink
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@@ -0,0 +1,421 @@
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/*
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* GENERATED FILE - DO NOT EDIT
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* Copyright (c) 2008-2013 Code Red Technologies Ltd,
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* Copyright 2015, 2018-2019 NXP
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* (c) NXP Semiconductors 2013-2021
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* Generated linker script file for LPC1837
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* Created from linkscript.ldt by FMCreateLinkLibraries
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* Using Freemarker v2.3.23
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* MCUXpresso IDE v11.2.0 [Build 4120] [2020-07-09] on Mar 3, 2021 4:22:49 PM
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*/
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MEMORY
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{
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/* Define each memory region */
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MFlashA512 (rx) : ORIGIN = 0x1a000000, LENGTH = 0x80000 /* 512K bytes (alias Flash) */
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MFlashB512 (rx) : ORIGIN = 0x1b000000, LENGTH = 0x80000 /* 512K bytes (alias Flash2) */
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RamLoc32 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x8000 /* 32K bytes (alias RAM) */
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RamLoc40 (rwx) : ORIGIN = 0x10080000, LENGTH = 0xa000 /* 40K bytes (alias RAM2) */
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RamAHB32 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x8000 /* 32K bytes (alias RAM3) */
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RamAHB16 (rwx) : ORIGIN = 0x20008000, LENGTH = 0x4000 /* 16K bytes (alias RAM4) */
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RamAHB_ETB16 (rwx) : ORIGIN = 0x2000c000, LENGTH = 0x4000 /* 16K bytes (alias RAM5) */
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}
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/* Define a symbol for the top of each memory region */
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__base_MFlashA512 = 0x1a000000 ; /* MFlashA512 */
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__base_Flash = 0x1a000000 ; /* Flash */
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__top_MFlashA512 = 0x1a000000 + 0x80000 ; /* 512K bytes */
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__top_Flash = 0x1a000000 + 0x80000 ; /* 512K bytes */
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__base_MFlashB512 = 0x1b000000 ; /* MFlashB512 */
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__base_Flash2 = 0x1b000000 ; /* Flash2 */
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__top_MFlashB512 = 0x1b000000 + 0x80000 ; /* 512K bytes */
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__top_Flash2 = 0x1b000000 + 0x80000 ; /* 512K bytes */
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__base_RamLoc32 = 0x10000000 ; /* RamLoc32 */
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__base_RAM = 0x10000000 ; /* RAM */
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__top_RamLoc32 = 0x10000000 + 0x8000 ; /* 32K bytes */
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__top_RAM = 0x10000000 + 0x8000 ; /* 32K bytes */
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__base_RamLoc40 = 0x10080000 ; /* RamLoc40 */
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__base_RAM2 = 0x10080000 ; /* RAM2 */
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__top_RamLoc40 = 0x10080000 + 0xa000 ; /* 40K bytes */
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__top_RAM2 = 0x10080000 + 0xa000 ; /* 40K bytes */
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__base_RamAHB32 = 0x20000000 ; /* RamAHB32 */
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__base_RAM3 = 0x20000000 ; /* RAM3 */
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__top_RamAHB32 = 0x20000000 + 0x8000 ; /* 32K bytes */
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__top_RAM3 = 0x20000000 + 0x8000 ; /* 32K bytes */
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__base_RamAHB16 = 0x20008000 ; /* RamAHB16 */
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__base_RAM4 = 0x20008000 ; /* RAM4 */
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__top_RamAHB16 = 0x20008000 + 0x4000 ; /* 16K bytes */
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__top_RAM4 = 0x20008000 + 0x4000 ; /* 16K bytes */
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__base_RamAHB_ETB16 = 0x2000c000 ; /* RamAHB_ETB16 */
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__base_RAM5 = 0x2000c000 ; /* RAM5 */
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__top_RamAHB_ETB16 = 0x2000c000 + 0x4000 ; /* 16K bytes */
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__top_RAM5 = 0x2000c000 + 0x4000 ; /* 16K bytes */
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ENTRY(ResetISR)
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SECTIONS
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{
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.text_Flash2 : ALIGN(4)
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{
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FILL(0xff)
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*(.text_Flash2) /* for compatibility with previous releases */
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*(.text_MFlashB512) /* for compatibility with previous releases */
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*(.text.$Flash2)
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*(.text.$MFlashB512)
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*(.text_Flash2.*) /* for compatibility with previous releases */
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*(.text_MFlashB512.*) /* for compatibility with previous releases */
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*(.text.$Flash2.*)
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*(.text.$MFlashB512.*)
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*(.rodata.$Flash2)
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*(.rodata.$MFlashB512)
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*(.rodata.$Flash2.*)
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*(.rodata.$MFlashB512.*) } > MFlashB512
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/* MAIN TEXT SECTION */
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.text : ALIGN(4)
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{
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FILL(0xff)
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__vectors_start__ = ABSOLUTE(.) ;
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KEEP(*(.isr_vector))
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/* Global Section Table */
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. = ALIGN(4) ;
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__section_table_start = .;
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__data_section_table = .;
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LONG(LOADADDR(.data));
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LONG( ADDR(.data));
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LONG( SIZEOF(.data));
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LONG(LOADADDR(.data_RAM2));
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LONG( ADDR(.data_RAM2));
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LONG( SIZEOF(.data_RAM2));
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LONG(LOADADDR(.data_RAM3));
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LONG( ADDR(.data_RAM3));
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LONG( SIZEOF(.data_RAM3));
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LONG(LOADADDR(.data_RAM4));
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LONG( ADDR(.data_RAM4));
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LONG( SIZEOF(.data_RAM4));
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LONG(LOADADDR(.data_RAM5));
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LONG( ADDR(.data_RAM5));
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LONG( SIZEOF(.data_RAM5));
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__data_section_table_end = .;
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__bss_section_table = .;
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LONG( ADDR(.bss));
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LONG( SIZEOF(.bss));
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LONG( ADDR(.bss_RAM2));
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LONG( SIZEOF(.bss_RAM2));
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LONG( ADDR(.bss_RAM3));
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LONG( SIZEOF(.bss_RAM3));
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LONG( ADDR(.bss_RAM4));
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LONG( SIZEOF(.bss_RAM4));
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LONG( ADDR(.bss_RAM5));
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LONG( SIZEOF(.bss_RAM5));
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__bss_section_table_end = .;
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__section_table_end = . ;
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/* End of Global Section Table */
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*(.after_vectors*)
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} > MFlashA512
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.text : ALIGN(4)
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{
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*(.text*)
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*(.rodata .rodata.* .constdata .constdata.*)
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. = ALIGN(4);
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} > MFlashA512
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/*
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* for exception handling/unwind - some Newlib functions (in common
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* with C++ and STDC++) use this.
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*/
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.ARM.extab : ALIGN(4)
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{
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*(.ARM.extab* .gnu.linkonce.armextab.*)
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} > MFlashA512
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.ARM.exidx : ALIGN(4)
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{
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__exidx_start = .;
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*(.ARM.exidx* .gnu.linkonce.armexidx.*)
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__exidx_end = .;
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} > MFlashA512
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_etext = .;
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/* DATA section for RamLoc40 */
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.data_RAM2 : ALIGN(4)
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{
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FILL(0xff)
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PROVIDE(__start_data_RAM2 = .) ;
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PROVIDE(__start_data_RamLoc40 = .) ;
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*(.ramfunc.$RAM2)
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*(.ramfunc.$RamLoc40)
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*(.data.$RAM2)
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||||
*(.data.$RamLoc40)
|
||||
*(.data.$RAM2.*)
|
||||
*(.data.$RamLoc40.*)
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. = ALIGN(4) ;
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PROVIDE(__end_data_RAM2 = .) ;
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PROVIDE(__end_data_RamLoc40 = .) ;
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||||
} > RamLoc40 AT>MFlashA512
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||||
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||||
/* DATA section for RamAHB32 */
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||||
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.data_RAM3 : ALIGN(4)
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||||
{
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||||
FILL(0xff)
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||||
PROVIDE(__start_data_RAM3 = .) ;
|
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PROVIDE(__start_data_RamAHB32 = .) ;
|
||||
*(.ramfunc.$RAM3)
|
||||
*(.ramfunc.$RamAHB32)
|
||||
*(.data.$RAM3)
|
||||
*(.data.$RamAHB32)
|
||||
*(.data.$RAM3.*)
|
||||
*(.data.$RamAHB32.*)
|
||||
. = ALIGN(4) ;
|
||||
PROVIDE(__end_data_RAM3 = .) ;
|
||||
PROVIDE(__end_data_RamAHB32 = .) ;
|
||||
} > RamAHB32 AT>MFlashA512
|
||||
|
||||
/* DATA section for RamAHB16 */
|
||||
|
||||
.data_RAM4 : ALIGN(4)
|
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{
|
||||
FILL(0xff)
|
||||
PROVIDE(__start_data_RAM4 = .) ;
|
||||
PROVIDE(__start_data_RamAHB16 = .) ;
|
||||
*(.ramfunc.$RAM4)
|
||||
*(.ramfunc.$RamAHB16)
|
||||
*(.data.$RAM4)
|
||||
*(.data.$RamAHB16)
|
||||
*(.data.$RAM4.*)
|
||||
*(.data.$RamAHB16.*)
|
||||
. = ALIGN(4) ;
|
||||
PROVIDE(__end_data_RAM4 = .) ;
|
||||
PROVIDE(__end_data_RamAHB16 = .) ;
|
||||
} > RamAHB16 AT>MFlashA512
|
||||
|
||||
/* DATA section for RamAHB_ETB16 */
|
||||
|
||||
.data_RAM5 : ALIGN(4)
|
||||
{
|
||||
FILL(0xff)
|
||||
PROVIDE(__start_data_RAM5 = .) ;
|
||||
PROVIDE(__start_data_RamAHB_ETB16 = .) ;
|
||||
*(.ramfunc.$RAM5)
|
||||
*(.ramfunc.$RamAHB_ETB16)
|
||||
*(.data.$RAM5)
|
||||
*(.data.$RamAHB_ETB16)
|
||||
*(.data.$RAM5.*)
|
||||
*(.data.$RamAHB_ETB16.*)
|
||||
. = ALIGN(4) ;
|
||||
PROVIDE(__end_data_RAM5 = .) ;
|
||||
PROVIDE(__end_data_RamAHB_ETB16 = .) ;
|
||||
} > RamAHB_ETB16 AT>MFlashA512
|
||||
|
||||
/* MAIN DATA SECTION */
|
||||
.uninit_RESERVED (NOLOAD) : ALIGN(4)
|
||||
{
|
||||
_start_uninit_RESERVED = .;
|
||||
KEEP(*(.bss.$RESERVED*))
|
||||
. = ALIGN(4) ;
|
||||
_end_uninit_RESERVED = .;
|
||||
} > RamLoc32 AT> RamLoc32
|
||||
|
||||
/* Main DATA section (RamLoc32) */
|
||||
.data : ALIGN(4)
|
||||
{
|
||||
FILL(0xff)
|
||||
_data = . ;
|
||||
PROVIDE(__start_data_RAM = .) ;
|
||||
PROVIDE(__start_data_RamLoc32 = .) ;
|
||||
*(vtable)
|
||||
*(.ramfunc*)
|
||||
KEEP(*(CodeQuickAccess))
|
||||
KEEP(*(DataQuickAccess))
|
||||
*(RamFunction)
|
||||
*(.data*)
|
||||
. = ALIGN(4) ;
|
||||
_edata = . ;
|
||||
PROVIDE(__end_data_RAM = .) ;
|
||||
PROVIDE(__end_data_RamLoc32 = .) ;
|
||||
} > RamLoc32 AT>MFlashA512
|
||||
|
||||
/* BSS section for RamLoc40 */
|
||||
.bss_RAM2 : ALIGN(4)
|
||||
{
|
||||
PROVIDE(__start_bss_RAM2 = .) ;
|
||||
PROVIDE(__start_bss_RamLoc40 = .) ;
|
||||
*(.bss.$RAM2)
|
||||
*(.bss.$RamLoc40)
|
||||
*(.bss.$RAM2.*)
|
||||
*(.bss.$RamLoc40.*)
|
||||
. = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
|
||||
PROVIDE(__end_bss_RAM2 = .) ;
|
||||
PROVIDE(__end_bss_RamLoc40 = .) ;
|
||||
} > RamLoc40 AT> RamLoc40
|
||||
|
||||
/* BSS section for RamAHB32 */
|
||||
.bss_RAM3 : ALIGN(4)
|
||||
{
|
||||
PROVIDE(__start_bss_RAM3 = .) ;
|
||||
PROVIDE(__start_bss_RamAHB32 = .) ;
|
||||
*(.bss.$RAM3)
|
||||
*(.bss.$RamAHB32)
|
||||
*(.bss.$RAM3.*)
|
||||
*(.bss.$RamAHB32.*)
|
||||
. = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
|
||||
PROVIDE(__end_bss_RAM3 = .) ;
|
||||
PROVIDE(__end_bss_RamAHB32 = .) ;
|
||||
} > RamAHB32 AT> RamAHB32
|
||||
|
||||
/* BSS section for RamAHB16 */
|
||||
.bss_RAM4 : ALIGN(4)
|
||||
{
|
||||
PROVIDE(__start_bss_RAM4 = .) ;
|
||||
PROVIDE(__start_bss_RamAHB16 = .) ;
|
||||
*(.bss.$RAM4)
|
||||
*(.bss.$RamAHB16)
|
||||
*(.bss.$RAM4.*)
|
||||
*(.bss.$RamAHB16.*)
|
||||
. = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
|
||||
PROVIDE(__end_bss_RAM4 = .) ;
|
||||
PROVIDE(__end_bss_RamAHB16 = .) ;
|
||||
} > RamAHB16 AT> RamAHB16
|
||||
|
||||
/* BSS section for RamAHB_ETB16 */
|
||||
.bss_RAM5 : ALIGN(4)
|
||||
{
|
||||
PROVIDE(__start_bss_RAM5 = .) ;
|
||||
PROVIDE(__start_bss_RamAHB_ETB16 = .) ;
|
||||
*(.bss.$RAM5)
|
||||
*(.bss.$RamAHB_ETB16)
|
||||
*(.bss.$RAM5.*)
|
||||
*(.bss.$RamAHB_ETB16.*)
|
||||
. = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
|
||||
PROVIDE(__end_bss_RAM5 = .) ;
|
||||
PROVIDE(__end_bss_RamAHB_ETB16 = .) ;
|
||||
} > RamAHB_ETB16 AT> RamAHB_ETB16
|
||||
|
||||
/* MAIN BSS SECTION: EDIT change to RamLoc40 */
|
||||
.bss : ALIGN(4)
|
||||
{
|
||||
_bss = .;
|
||||
PROVIDE(__start_bss_RAM = .) ;
|
||||
PROVIDE(__start_bss_RamLoc32 = .) ;
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4) ;
|
||||
_ebss = .;
|
||||
PROVIDE(__end_bss_RAM = .) ;
|
||||
PROVIDE(__end_bss_RamLoc32 = .) ;
|
||||
/* PROVIDE(end = .);*/
|
||||
} > RamLoc40 AT> RamLoc40 /* > RamLoc32 AT> RamLoc32 */
|
||||
|
||||
/* hathach add heap section for clang */
|
||||
.heap (NOLOAD): {
|
||||
__heap_start = .;
|
||||
__HeapBase = .;
|
||||
__heap_base = .;
|
||||
__end = .;
|
||||
PROVIDE(end = .);
|
||||
PROVIDE(_end = .);
|
||||
PROVIDE(__end__ = .);
|
||||
KEEP(*(.heap*))
|
||||
__HeapLimit = .;
|
||||
__heap_limit = .;
|
||||
__heap_end = .;
|
||||
} > RamLoc40
|
||||
|
||||
/* NOINIT section for RamLoc40 */
|
||||
.noinit_RAM2 (NOLOAD) : ALIGN(4)
|
||||
{
|
||||
PROVIDE(__start_noinit_RAM2 = .) ;
|
||||
PROVIDE(__start_noinit_RamLoc40 = .) ;
|
||||
*(.noinit.$RAM2)
|
||||
*(.noinit.$RamLoc40)
|
||||
*(.noinit.$RAM2.*)
|
||||
*(.noinit.$RamLoc40.*)
|
||||
. = ALIGN(4) ;
|
||||
PROVIDE(__end_noinit_RAM2 = .) ;
|
||||
PROVIDE(__end_noinit_RamLoc40 = .) ;
|
||||
} > RamLoc40 AT> RamLoc40
|
||||
|
||||
/* NOINIT section for RamAHB32 */
|
||||
.noinit_RAM3 (NOLOAD) : ALIGN(4)
|
||||
{
|
||||
PROVIDE(__start_noinit_RAM3 = .) ;
|
||||
PROVIDE(__start_noinit_RamAHB32 = .) ;
|
||||
*(.noinit.$RAM3)
|
||||
*(.noinit.$RamAHB32)
|
||||
*(.noinit.$RAM3.*)
|
||||
*(.noinit.$RamAHB32.*)
|
||||
. = ALIGN(4) ;
|
||||
PROVIDE(__end_noinit_RAM3 = .) ;
|
||||
PROVIDE(__end_noinit_RamAHB32 = .) ;
|
||||
} > RamAHB32 AT> RamAHB32
|
||||
|
||||
/* NOINIT section for RamAHB16 */
|
||||
.noinit_RAM4 (NOLOAD) : ALIGN(4)
|
||||
{
|
||||
PROVIDE(__start_noinit_RAM4 = .) ;
|
||||
PROVIDE(__start_noinit_RamAHB16 = .) ;
|
||||
*(.noinit.$RAM4)
|
||||
*(.noinit.$RamAHB16)
|
||||
*(.noinit.$RAM4.*)
|
||||
*(.noinit.$RamAHB16.*)
|
||||
. = ALIGN(4) ;
|
||||
PROVIDE(__end_noinit_RAM4 = .) ;
|
||||
PROVIDE(__end_noinit_RamAHB16 = .) ;
|
||||
} > RamAHB16 AT> RamAHB16
|
||||
|
||||
/* NOINIT section for RamAHB_ETB16 */
|
||||
.noinit_RAM5 (NOLOAD) : ALIGN(4)
|
||||
{
|
||||
PROVIDE(__start_noinit_RAM5 = .) ;
|
||||
PROVIDE(__start_noinit_RamAHB_ETB16 = .) ;
|
||||
*(.noinit.$RAM5)
|
||||
*(.noinit.$RamAHB_ETB16)
|
||||
*(.noinit.$RAM5.*)
|
||||
*(.noinit.$RamAHB_ETB16.*)
|
||||
. = ALIGN(4) ;
|
||||
PROVIDE(__end_noinit_RAM5 = .) ;
|
||||
PROVIDE(__end_noinit_RamAHB_ETB16 = .) ;
|
||||
} > RamAHB_ETB16 AT> RamAHB_ETB16
|
||||
|
||||
/* DEFAULT NOINIT SECTION */
|
||||
.noinit (NOLOAD): ALIGN(4)
|
||||
{
|
||||
_noinit = .;
|
||||
PROVIDE(__start_noinit_RAM = .) ;
|
||||
PROVIDE(__start_noinit_RamLoc32 = .) ;
|
||||
*(.noinit*)
|
||||
. = ALIGN(4) ;
|
||||
_end_noinit = .;
|
||||
PROVIDE(__end_noinit_RAM = .) ;
|
||||
PROVIDE(__end_noinit_RamLoc32 = .) ;
|
||||
} > RamLoc32 AT> RamLoc32
|
||||
/* PROVIDE(_pvHeapStart = DEFINED(__user_heap_base) ? __user_heap_base : .);*/
|
||||
PROVIDE(_vStackTop = DEFINED(__user_stack_top) ? __user_stack_top : __top_RamLoc32 - 0);
|
||||
|
||||
/* ## Create checksum value (used in startup) ## */
|
||||
/* This cause issue with clang linker, so it is disabled */
|
||||
/* MemManage_Handler, BusFault_Handler, UsageFault_Handler may not be defined */
|
||||
/* PROVIDE(__valid_user_code_checksum = 0 -*/
|
||||
/* (_vStackTop*/
|
||||
/* + (ResetISR + 1)*/
|
||||
/* + (NMI_Handler + 1)*/
|
||||
/* + (HardFault_Handler + 1)*/
|
||||
/* + (( DEFINED(MemManage_Handler) ? MemManage_Handler : 0 ) + 1)*/
|
||||
/* + (( DEFINED(BusFault_Handler) ? BusFault_Handler : 0 ) + 1)*/
|
||||
/* + (( DEFINED(UsageFault_Handler) ? UsageFault_Handler : 0 ) + 1)*/
|
||||
/* ) );*/
|
||||
|
||||
/* Provide basic symbols giving location and size of main text
|
||||
* block, including initial values of RW data sections. Note that
|
||||
* these will need extending to give a complete picture with
|
||||
* complex images (e.g multiple Flash banks).
|
||||
*/
|
||||
_image_start = LOADADDR(.text);
|
||||
_image_end = LOADADDR(.data) + SIZEOF(.data);
|
||||
_image_size = _image_end - _image_start;
|
||||
}
|
||||
@@ -0,0 +1,11 @@
|
||||
set(MCU_VARIANT LPC1857)
|
||||
|
||||
set(JLINK_DEVICE LPC1857)
|
||||
set(PYOCD_TARGET LPC1857)
|
||||
set(NXPLINK_DEVICE LPC1857:MCB1857)
|
||||
|
||||
set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/lpc1857.ld)
|
||||
|
||||
function(update_board TARGET)
|
||||
# nothing to do
|
||||
endfunction()
|
||||
@@ -0,0 +1,103 @@
|
||||
/*
|
||||
* The MIT License (MIT)
|
||||
*
|
||||
* Copyright (c) 2021, Ha Thach (tinyusb.org)
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
* THE SOFTWARE.
|
||||
*
|
||||
* This file is part of the TinyUSB stack.
|
||||
*/
|
||||
|
||||
/* metadata:
|
||||
name: Keil MCB1800
|
||||
url: https://www.keil.com/arm/mcb1800/
|
||||
*/
|
||||
|
||||
#ifndef BOARD_H_
|
||||
#define BOARD_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
// PD_10
|
||||
#define LED_PORT 6
|
||||
#define LED_PIN 24
|
||||
|
||||
// P4_0
|
||||
#define BUTTON_PORT 2
|
||||
#define BUTTON_PIN 0
|
||||
|
||||
#define UART_DEV LPC_USART3
|
||||
|
||||
static inline void board_lpc18_pinmux(void) {
|
||||
const PINMUX_GRP_T pinmuxing[] = {
|
||||
// ETM Trace
|
||||
#ifdef TRACE_ETM
|
||||
{ 0xF, 4, SCU_MODE_FUNC2 | SCU_MODE_HIGHSPEEDSLEW_EN },
|
||||
{ 0xF, 5, SCU_MODE_FUNC3 | SCU_MODE_HIGHSPEEDSLEW_EN },
|
||||
{ 0xF, 6, SCU_MODE_FUNC3 | SCU_MODE_HIGHSPEEDSLEW_EN },
|
||||
{ 0xF, 7, SCU_MODE_FUNC3 | SCU_MODE_HIGHSPEEDSLEW_EN },
|
||||
{ 0xF, 8, SCU_MODE_FUNC3 | SCU_MODE_HIGHSPEEDSLEW_EN },
|
||||
#endif
|
||||
|
||||
// LEDs
|
||||
{ 0xD, 10, (SCU_MODE_INBUFF_EN | SCU_MODE_INACT | SCU_MODE_FUNC4) },
|
||||
{ 0xD, 11, (SCU_MODE_INBUFF_EN | SCU_MODE_INACT | SCU_MODE_FUNC4 | SCU_MODE_PULLDOWN) },
|
||||
{ 0xD, 12, (SCU_MODE_INBUFF_EN | SCU_MODE_INACT | SCU_MODE_FUNC4 | SCU_MODE_PULLDOWN) },
|
||||
{ 0xD, 13, (SCU_MODE_INBUFF_EN | SCU_MODE_INACT | SCU_MODE_FUNC4 | SCU_MODE_PULLDOWN) },
|
||||
{ 0xD, 14, (SCU_MODE_INBUFF_EN | SCU_MODE_INACT | SCU_MODE_FUNC4 | SCU_MODE_PULLDOWN) },
|
||||
{ 0x9, 0, (SCU_MODE_INBUFF_EN | SCU_MODE_INACT | SCU_MODE_FUNC0 | SCU_MODE_PULLDOWN) },
|
||||
{ 0x9, 1, (SCU_MODE_INBUFF_EN | SCU_MODE_INACT | SCU_MODE_FUNC0 | SCU_MODE_PULLDOWN) },
|
||||
{ 0x9, 2, (SCU_MODE_INBUFF_EN | SCU_MODE_INACT | SCU_MODE_FUNC0 | SCU_MODE_PULLDOWN) },
|
||||
|
||||
// Button
|
||||
{ 0x4, 0, (SCU_MODE_INBUFF_EN | SCU_MODE_INACT | SCU_MODE_FUNC0 | SCU_MODE_PULLUP) },
|
||||
|
||||
// UART
|
||||
{ 2, 3, SCU_MODE_PULLDOWN | SCU_MODE_FUNC2 },
|
||||
{ 2, 4, SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC2 },
|
||||
|
||||
// USB0
|
||||
{ 0x6, 3, SCU_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_FUNC1 }, // P6_3 USB0_PWR_EN, USB0 VBus function
|
||||
{ 0x9, 5, SCU_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_FUNC2 }, // P9_5 USB1_VBUS_EN, USB1 VBus function
|
||||
{ 0x2, 5, SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC2 }, // P2_5 USB1_VBUS, MUST CONFIGURE THIS SIGNAL FOR USB1 NORMAL OPERATION
|
||||
};
|
||||
|
||||
Chip_SCU_SetPinMuxing(pinmuxing, sizeof(pinmuxing) / sizeof(PINMUX_GRP_T));
|
||||
|
||||
/* Pin clock mux values, re-used structure, value in first index is meaningless */
|
||||
const PINMUX_GRP_T pinclockmuxing[] = {
|
||||
{ 0, 0, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC0)},
|
||||
{ 0, 1, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC0)},
|
||||
{ 0, 2, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC0)},
|
||||
{ 0, 3, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC0)},
|
||||
};
|
||||
|
||||
/* Clock pins only, group field not used */
|
||||
for (uint32_t i = 0; i < (sizeof(pinclockmuxing) / sizeof(pinclockmuxing[0])); i++) {
|
||||
Chip_SCU_ClockPinMuxSet(pinclockmuxing[i].pinnum, pinclockmuxing[i].modefunc);
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,7 @@
|
||||
LD_FILE = $(BOARD_PATH)/lpc1857.ld
|
||||
|
||||
# For flash-jlink target
|
||||
JLINK_DEVICE = LPC1857
|
||||
|
||||
# flash using jlink
|
||||
flash: flash-jlink
|
||||
@@ -0,0 +1,340 @@
|
||||
/*
|
||||
* GENERATED FILE - DO NOT EDIT
|
||||
* (c) Code Red Technologies Ltd, 2008-2013
|
||||
* (c) NXP Semiconductors 2013-2019
|
||||
* Generated linker script file for LPC1857
|
||||
* Created from linkscript.ldt by FMCreateLinkLibraries
|
||||
* Using Freemarker v2.3.23
|
||||
* MCUXpresso IDE v10.2.1 [Build 795] [2018-07-25] on May 15, 2019 1:01:52 PM
|
||||
*/
|
||||
|
||||
MEMORY
|
||||
{
|
||||
/* Define each memory region */
|
||||
MFlashA512 (rx) : ORIGIN = 0x1a000000, LENGTH = 0x80000 /* 512K bytes (alias Flash) */
|
||||
MFlashB512 (rx) : ORIGIN = 0x1b000000, LENGTH = 0x80000 /* 512K bytes (alias Flash2) */
|
||||
RamLoc32 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x8000 /* 32K bytes (alias RAM) */
|
||||
RamLoc40 (rwx) : ORIGIN = 0x10080000, LENGTH = 0xa000 /* 40K bytes (alias RAM2) */
|
||||
RamAHB32 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x8000 /* 32K bytes (alias RAM3) */
|
||||
RamAHB16 (rwx) : ORIGIN = 0x20008000, LENGTH = 0x4000 /* 16K bytes (alias RAM4) */
|
||||
RamAHB_ETB16 (rwx) : ORIGIN = 0x2000c000, LENGTH = 0x4000 /* 16K bytes (alias RAM5) */
|
||||
}
|
||||
|
||||
/* Define a symbol for the top of each memory region */
|
||||
__base_MFlashA512 = 0x1a000000 ; /* MFlashA512 */
|
||||
__base_Flash = 0x1a000000 ; /* Flash */
|
||||
__top_MFlashA512 = 0x1a000000 + 0x80000 ; /* 512K bytes */
|
||||
__top_Flash = 0x1a000000 + 0x80000 ; /* 512K bytes */
|
||||
__base_MFlashB512 = 0x1b000000 ; /* MFlashB512 */
|
||||
__base_Flash2 = 0x1b000000 ; /* Flash2 */
|
||||
__top_MFlashB512 = 0x1b000000 + 0x80000 ; /* 512K bytes */
|
||||
__top_Flash2 = 0x1b000000 + 0x80000 ; /* 512K bytes */
|
||||
__base_RamLoc32 = 0x10000000 ; /* RamLoc32 */
|
||||
__base_RAM = 0x10000000 ; /* RAM */
|
||||
__top_RamLoc32 = 0x10000000 + 0x8000 ; /* 32K bytes */
|
||||
__top_RAM = 0x10000000 + 0x8000 ; /* 32K bytes */
|
||||
__base_RamLoc40 = 0x10080000 ; /* RamLoc40 */
|
||||
__base_RAM2 = 0x10080000 ; /* RAM2 */
|
||||
__top_RamLoc40 = 0x10080000 + 0xa000 ; /* 40K bytes */
|
||||
__top_RAM2 = 0x10080000 + 0xa000 ; /* 40K bytes */
|
||||
__base_RamAHB32 = 0x20000000 ; /* RamAHB32 */
|
||||
__base_RAM3 = 0x20000000 ; /* RAM3 */
|
||||
__top_RamAHB32 = 0x20000000 + 0x8000 ; /* 32K bytes */
|
||||
__top_RAM3 = 0x20000000 + 0x8000 ; /* 32K bytes */
|
||||
__base_RamAHB16 = 0x20008000 ; /* RamAHB16 */
|
||||
__base_RAM4 = 0x20008000 ; /* RAM4 */
|
||||
__top_RamAHB16 = 0x20008000 + 0x4000 ; /* 16K bytes */
|
||||
__top_RAM4 = 0x20008000 + 0x4000 ; /* 16K bytes */
|
||||
__base_RamAHB_ETB16 = 0x2000c000 ; /* RamAHB_ETB16 */
|
||||
__base_RAM5 = 0x2000c000 ; /* RAM5 */
|
||||
__top_RamAHB_ETB16 = 0x2000c000 + 0x4000 ; /* 16K bytes */
|
||||
__top_RAM5 = 0x2000c000 + 0x4000 ; /* 16K bytes */
|
||||
|
||||
ENTRY(ResetISR)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
.text_Flash2 : ALIGN(4)
|
||||
{
|
||||
FILL(0xff)
|
||||
*(.text_Flash2*) /* for compatibility with previous releases */
|
||||
*(.text_MFlashB512*) /* for compatibility with previous releases */
|
||||
*(.text.$Flash2*)
|
||||
*(.text.$MFlashB512*)
|
||||
*(.rodata.$Flash2*)
|
||||
*(.rodata.$MFlashB512*)
|
||||
} > MFlashB512
|
||||
|
||||
/* MAIN TEXT SECTION */
|
||||
.text : ALIGN(4)
|
||||
{
|
||||
FILL(0xff)
|
||||
__vectors_start__ = ABSOLUTE(.) ;
|
||||
KEEP(*(.isr_vector))
|
||||
/* Global Section Table */
|
||||
. = ALIGN(4) ;
|
||||
__section_table_start = .;
|
||||
__data_section_table = .;
|
||||
LONG(LOADADDR(.data));
|
||||
LONG( ADDR(.data));
|
||||
LONG( SIZEOF(.data));
|
||||
LONG(LOADADDR(.data_RAM2));
|
||||
LONG( ADDR(.data_RAM2));
|
||||
LONG( SIZEOF(.data_RAM2));
|
||||
LONG(LOADADDR(.data_RAM3));
|
||||
LONG( ADDR(.data_RAM3));
|
||||
LONG( SIZEOF(.data_RAM3));
|
||||
LONG(LOADADDR(.data_RAM4));
|
||||
LONG( ADDR(.data_RAM4));
|
||||
LONG( SIZEOF(.data_RAM4));
|
||||
LONG(LOADADDR(.data_RAM5));
|
||||
LONG( ADDR(.data_RAM5));
|
||||
LONG( SIZEOF(.data_RAM5));
|
||||
__data_section_table_end = .;
|
||||
__bss_section_table = .;
|
||||
LONG( ADDR(.bss));
|
||||
LONG( SIZEOF(.bss));
|
||||
LONG( ADDR(.bss_RAM2));
|
||||
LONG( SIZEOF(.bss_RAM2));
|
||||
LONG( ADDR(.bss_RAM3));
|
||||
LONG( SIZEOF(.bss_RAM3));
|
||||
LONG( ADDR(.bss_RAM4));
|
||||
LONG( SIZEOF(.bss_RAM4));
|
||||
LONG( ADDR(.bss_RAM5));
|
||||
LONG( SIZEOF(.bss_RAM5));
|
||||
__bss_section_table_end = .;
|
||||
__section_table_end = . ;
|
||||
/* End of Global Section Table */
|
||||
|
||||
*(.after_vectors*)
|
||||
|
||||
} > MFlashA512
|
||||
|
||||
.text : ALIGN(4)
|
||||
{
|
||||
*(.text*)
|
||||
*(.rodata .rodata.* .constdata .constdata.*)
|
||||
. = ALIGN(4);
|
||||
} > MFlashA512
|
||||
/*
|
||||
* for exception handling/unwind - some Newlib functions (in common
|
||||
* with C++ and STDC++) use this.
|
||||
*/
|
||||
.ARM.extab : ALIGN(4)
|
||||
{
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
} > MFlashA512
|
||||
|
||||
__exidx_start = .;
|
||||
|
||||
.ARM.exidx : ALIGN(4)
|
||||
{
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
} > MFlashA512
|
||||
__exidx_end = .;
|
||||
|
||||
_etext = .;
|
||||
|
||||
/* DATA section for RamLoc40 */
|
||||
|
||||
.data_RAM2 : ALIGN(4)
|
||||
{
|
||||
FILL(0xff)
|
||||
PROVIDE(__start_data_RAM2 = .) ;
|
||||
*(.ramfunc.$RAM2)
|
||||
*(.ramfunc.$RamLoc40)
|
||||
*(.data.$RAM2*)
|
||||
*(.data.$RamLoc40*)
|
||||
. = ALIGN(4) ;
|
||||
PROVIDE(__end_data_RAM2 = .) ;
|
||||
} > RamLoc40 AT>MFlashA512
|
||||
/* DATA section for RamAHB32 */
|
||||
|
||||
.data_RAM3 : ALIGN(4)
|
||||
{
|
||||
FILL(0xff)
|
||||
PROVIDE(__start_data_RAM3 = .) ;
|
||||
*(.ramfunc.$RAM3)
|
||||
*(.ramfunc.$RamAHB32)
|
||||
*(.data.$RAM3*)
|
||||
*(.data.$RamAHB32*)
|
||||
. = ALIGN(4) ;
|
||||
PROVIDE(__end_data_RAM3 = .) ;
|
||||
} > RamAHB32 AT>MFlashA512
|
||||
/* DATA section for RamAHB16 */
|
||||
|
||||
.data_RAM4 : ALIGN(4)
|
||||
{
|
||||
FILL(0xff)
|
||||
PROVIDE(__start_data_RAM4 = .) ;
|
||||
*(.ramfunc.$RAM4)
|
||||
*(.ramfunc.$RamAHB16)
|
||||
*(.data.$RAM4*)
|
||||
*(.data.$RamAHB16*)
|
||||
. = ALIGN(4) ;
|
||||
PROVIDE(__end_data_RAM4 = .) ;
|
||||
} > RamAHB16 AT>MFlashA512
|
||||
/* DATA section for RamAHB_ETB16 */
|
||||
|
||||
.data_RAM5 : ALIGN(4)
|
||||
{
|
||||
FILL(0xff)
|
||||
PROVIDE(__start_data_RAM5 = .) ;
|
||||
*(.ramfunc.$RAM5)
|
||||
*(.ramfunc.$RamAHB_ETB16)
|
||||
*(.data.$RAM5*)
|
||||
*(.data.$RamAHB_ETB16*)
|
||||
. = ALIGN(4) ;
|
||||
PROVIDE(__end_data_RAM5 = .) ;
|
||||
} > RamAHB_ETB16 AT>MFlashA512
|
||||
/* MAIN DATA SECTION */
|
||||
.uninit_RESERVED : ALIGN(4)
|
||||
{
|
||||
KEEP(*(.bss.$RESERVED*))
|
||||
. = ALIGN(4) ;
|
||||
_end_uninit_RESERVED = .;
|
||||
} > RamLoc32
|
||||
|
||||
/* Main DATA section (RamLoc32) */
|
||||
.data : ALIGN(4)
|
||||
{
|
||||
FILL(0xff)
|
||||
_data = . ;
|
||||
*(vtable)
|
||||
*(.ramfunc*)
|
||||
*(.data*)
|
||||
. = ALIGN(4) ;
|
||||
_edata = . ;
|
||||
} > RamLoc32 AT>MFlashA512
|
||||
|
||||
/* BSS section for RamLoc40 */
|
||||
.bss_RAM2 : ALIGN(4)
|
||||
{
|
||||
PROVIDE(__start_bss_RAM2 = .) ;
|
||||
*(.bss.$RAM2*)
|
||||
*(.bss.$RamLoc40*)
|
||||
. = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
|
||||
PROVIDE(__end_bss_RAM2 = .) ;
|
||||
} > RamLoc40
|
||||
|
||||
/* BSS section for RamAHB32 */
|
||||
.bss_RAM3 : ALIGN(4)
|
||||
{
|
||||
PROVIDE(__start_bss_RAM3 = .) ;
|
||||
*(.bss.$RAM3*)
|
||||
*(.bss.$RamAHB32*)
|
||||
. = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
|
||||
PROVIDE(__end_bss_RAM3 = .) ;
|
||||
} > RamAHB32
|
||||
|
||||
/* BSS section for RamAHB16 */
|
||||
.bss_RAM4 : ALIGN(4)
|
||||
{
|
||||
PROVIDE(__start_bss_RAM4 = .) ;
|
||||
*(.bss.$RAM4*)
|
||||
*(.bss.$RamAHB16*)
|
||||
. = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
|
||||
PROVIDE(__end_bss_RAM4 = .) ;
|
||||
} > RamAHB16
|
||||
|
||||
/* BSS section for RamAHB_ETB16 */
|
||||
.bss_RAM5 : ALIGN(4)
|
||||
{
|
||||
PROVIDE(__start_bss_RAM5 = .) ;
|
||||
*(.bss.$RAM5*)
|
||||
*(.bss.$RamAHB_ETB16*)
|
||||
. = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
|
||||
PROVIDE(__end_bss_RAM5 = .) ;
|
||||
} > RamAHB_ETB16
|
||||
|
||||
/* MAIN BSS SECTION: EDIT change to RamLoc40 */
|
||||
.bss : ALIGN(4)
|
||||
{
|
||||
_bss = .;
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4) ;
|
||||
_ebss = .;
|
||||
/* PROVIDE(end = .); */
|
||||
} > RamLoc40 /* RamLoc32 */
|
||||
|
||||
/* NOINIT section for RamLoc40 */
|
||||
.noinit_RAM2 (NOLOAD) : ALIGN(4)
|
||||
{
|
||||
*(.noinit.$RAM2*)
|
||||
*(.noinit.$RamLoc40*)
|
||||
. = ALIGN(4) ;
|
||||
} > RamLoc40
|
||||
|
||||
/* hathach add heap section for clang */
|
||||
.heap (NOLOAD): {
|
||||
__heap_start = .;
|
||||
__HeapBase = .;
|
||||
__heap_base = .;
|
||||
__end = .;
|
||||
PROVIDE(end = .);
|
||||
PROVIDE(_end = .);
|
||||
PROVIDE(__end__ = .);
|
||||
KEEP(*(.heap*))
|
||||
__HeapLimit = .;
|
||||
__heap_limit = .;
|
||||
__heap_end = .;
|
||||
} > RamLoc40
|
||||
|
||||
/* NOINIT section for RamAHB32 */
|
||||
.noinit_RAM3 (NOLOAD) : ALIGN(4)
|
||||
{
|
||||
*(.noinit.$RAM3*)
|
||||
*(.noinit.$RamAHB32*)
|
||||
. = ALIGN(4) ;
|
||||
} > RamAHB32
|
||||
|
||||
/* NOINIT section for RamAHB16 */
|
||||
.noinit_RAM4 (NOLOAD) : ALIGN(4)
|
||||
{
|
||||
*(.noinit.$RAM4*)
|
||||
*(.noinit.$RamAHB16*)
|
||||
. = ALIGN(4) ;
|
||||
} > RamAHB16
|
||||
|
||||
/* NOINIT section for RamAHB_ETB16 */
|
||||
.noinit_RAM5 (NOLOAD) : ALIGN(4)
|
||||
{
|
||||
*(.noinit.$RAM5*)
|
||||
*(.noinit.$RamAHB_ETB16*)
|
||||
. = ALIGN(4) ;
|
||||
} > RamAHB_ETB16
|
||||
|
||||
/* DEFAULT NOINIT SECTION */
|
||||
.noinit (NOLOAD): ALIGN(4)
|
||||
{
|
||||
_noinit = .;
|
||||
*(.noinit*)
|
||||
. = ALIGN(4) ;
|
||||
_end_noinit = .;
|
||||
} > RamLoc32
|
||||
/* PROVIDE(_pvHeapStart = DEFINED(__user_heap_base) ? __user_heap_base : .);*/
|
||||
PROVIDE(_vStackTop = DEFINED(__user_stack_top) ? __user_stack_top : __top_RamLoc32 - 0);
|
||||
|
||||
/* ## Create checksum value (used in startup) ## */
|
||||
/* This cause issue with clang linker, so it is disabled */
|
||||
/* MemManage_Handler, BusFault_Handler, UsageFault_Handler may not be defined */
|
||||
/* PROVIDE(__valid_user_code_checksum = 0 -*/
|
||||
/* (_vStackTop*/
|
||||
/* + (ResetISR + 1)*/
|
||||
/* + (NMI_Handler + 1)*/
|
||||
/* + (HardFault_Handler + 1)*/
|
||||
/* + (( DEFINED(MemManage_Handler) ? MemManage_Handler : 0 ) + 1)*/
|
||||
/* + (( DEFINED(BusFault_Handler) ? BusFault_Handler : 0 ) + 1)*/
|
||||
/* + (( DEFINED(UsageFault_Handler) ? UsageFault_Handler : 0 ) + 1)*/
|
||||
/* ) );*/
|
||||
|
||||
/* Provide basic symbols giving location and size of main text
|
||||
* block, including initial values of RW data sections. Note that
|
||||
* these will need extending to give a complete picture with
|
||||
* complex images (e.g multiple Flash banks).
|
||||
*/
|
||||
_image_start = LOADADDR(.text);
|
||||
_image_end = LOADADDR(.data) + SIZEOF(.data);
|
||||
_image_size = _image_end - _image_start;
|
||||
}
|
||||
@@ -0,0 +1,37 @@
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* OnProjectLoad
|
||||
*
|
||||
* Function description
|
||||
* Project load routine. Required.
|
||||
*
|
||||
**********************************************************************
|
||||
*/
|
||||
void OnProjectLoad (void) {
|
||||
Project.AddSvdFile ("Cortex-M3.svd");
|
||||
Project.AddSvdFile ("../../../../../../../cmsis-svd/data/NXP/LPC18xx.svd");
|
||||
|
||||
Project.SetDevice ("LPC1857");
|
||||
Project.SetHostIF ("USB", "");
|
||||
Project.SetTargetIF ("SWD");
|
||||
Project.SetTIFSpeed ("50 MHz");
|
||||
|
||||
Project.SetTraceSource ("Trace Pins");
|
||||
Project.SetTracePortWidth (4);
|
||||
|
||||
//File.Open ("../../../../../../examples/cmake-build-mcb1800/device/cdc_msc/cdc_msc.elf");
|
||||
File.Open ("../../../../../../examples/cmake-build-mcb1800/host/cdc_msc_hid/cdc_msc_hid.elf");
|
||||
}
|
||||
/*********************************************************************
|
||||
*
|
||||
* BeforeTargetConnect
|
||||
*
|
||||
**********************************************************************
|
||||
*/
|
||||
void BeforeTargetConnect (void) {
|
||||
//
|
||||
// Trace pin init is done by J-Link script file as J-Link script files are IDE independent
|
||||
//
|
||||
// Project.SetJLinkScript("./NXP_LPC1857JET256_TraceExample.pex");
|
||||
}
|
||||
Reference in New Issue
Block a user