Initial project setup
This commit is contained in:
@@ -0,0 +1,11 @@
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set(JLINK_DEVICE LPC1347)
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set(PYOCD_TARGET LPC1347)
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set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/lpc1347.ld)
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function(update_board TARGET)
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target_compile_definitions(${TARGET} PUBLIC
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CFG_EXAMPLE_MSC_READONLY
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CFG_EXAMPLE_VIDEO_READONLY
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)
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endfunction()
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@@ -0,0 +1,51 @@
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/* metadata:
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name: LPCXpresso1347
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url: https://www.nxp.com/products/no-longer-manufactured/lpcxpresso-board-for-lpc1347:OM13045
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*/
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#ifndef BOARD_H
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#define BOARD_H
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//--------------------------------------------------------------------+
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// MACRO TYPEDEF CONSTANT ENUM
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//--------------------------------------------------------------------+
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#define LED_PORT 0
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#define LED_PIN 7
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// Joytick Down if connected to LPCXpresso Base board
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#define BUTTON_PORT 1
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#define BUTTON_PIN 20
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//static const struct {
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// uint8_t port;
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// uint8_t pin;
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//} buttons[] =
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//{
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// {1, 22 }, // Joystick up
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// {1, 20 }, // Joystick down
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// {1, 23 }, // Joystick left
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// {1, 21 }, // Joystick right
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// {1, 19 }, // Joystick press
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// {0, 1 }, // SW3
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//};
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/* System oscillator rate and RTC oscillator rate */
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const uint32_t OscRateIn = 12000000;
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const uint32_t ExtRateIn = 0;
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/* Pin muxing table, only items that need changing from their default pin
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state are in this table. */
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static const PINMUX_GRP_T pinmuxing[] = {
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{0, 1, (IOCON_FUNC1 | IOCON_RESERVED_BIT_7 | IOCON_MODE_INACT)}, /* PIO0_1 used for CLKOUT */
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{0, 2, (IOCON_FUNC1 | IOCON_RESERVED_BIT_7 | IOCON_MODE_PULLUP)}, /* PIO0_2 used for SSEL */
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{0, 3, (IOCON_FUNC1 | IOCON_RESERVED_BIT_7 | IOCON_MODE_INACT)}, /* PIO0_3 used for USB_VBUS */
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{0, 6, (IOCON_FUNC1 | IOCON_RESERVED_BIT_7 | IOCON_MODE_INACT)}, /* PIO0_6 used for USB_CONNECT */
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{0, 8, (IOCON_FUNC1 | IOCON_RESERVED_BIT_7 | IOCON_MODE_INACT)}, /* PIO0_8 used for MISO0 */
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{0, 9, (IOCON_FUNC1 | IOCON_RESERVED_BIT_7 | IOCON_MODE_INACT)}, /* PIO0_9 used for MOSI0 */
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{0, 11, (IOCON_FUNC2 | IOCON_ADMODE_EN | IOCON_FILT_DIS)}, /* PIO0_11 used for AD0 */
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{0, 18, (IOCON_FUNC1 | IOCON_RESERVED_BIT_7 | IOCON_MODE_INACT)}, /* PIO0_18 used for RXD */
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{0, 19, (IOCON_FUNC1 | IOCON_RESERVED_BIT_7 | IOCON_MODE_INACT)}, /* PIO0_19 used for TXD */
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{1, 29, (IOCON_FUNC1 | IOCON_RESERVED_BIT_7 | IOCON_MODE_INACT)}, /* PIO1_29 used for SCK0 */
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};
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#endif
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@@ -0,0 +1,11 @@
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CFLAGS += \
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-DCFG_TUSB_MEM_SECTION='__attribute__((section(".data.$$RAM2")))'
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# All source paths should be relative to the top level.
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LD_FILE = $(BOARD_PATH)/lpc1347.ld
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# For flash-jlink target
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JLINK_DEVICE = LPC1347
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# flash using jlink
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flash: flash-jlink
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@@ -0,0 +1,225 @@
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/*
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* GENERATED FILE - DO NOT EDIT
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* (c) Code Red Technologies Ltd, 2008-2013
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* (c) NXP Semiconductors 2013-2019
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* Generated linker script file for LPC1347
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* Created from linkscript.ldt by FMCreateLinkLibraries
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* Using Freemarker v2.3.23
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* MCUXpresso IDE v10.2.1 [Build 795] [2018-07-25] on May 14, 2019 6:01:58 PM
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*/
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MEMORY
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{
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/* Define each memory region */
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MFlash64 (rx) : ORIGIN = 0x0, LENGTH = 0x10000 /* 64K bytes (alias Flash) */
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RamLoc8 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x2000 /* 8K bytes (alias RAM) */
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RamUsb2 (rwx) : ORIGIN = 0x20004000, LENGTH = 0x800 /* 2K bytes (alias RAM2) */
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RamPeriph2 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x800 /* 2K bytes (alias RAM3) */
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}
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/* Define a symbol for the top of each memory region */
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__base_MFlash64 = 0x0 ; /* MFlash64 */
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__base_Flash = 0x0 ; /* Flash */
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__top_MFlash64 = 0x0 + 0x10000 ; /* 64K bytes */
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__top_Flash = 0x0 + 0x10000 ; /* 64K bytes */
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__base_RamLoc8 = 0x10000000 ; /* RamLoc8 */
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__base_RAM = 0x10000000 ; /* RAM */
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__top_RamLoc8 = 0x10000000 + 0x2000 ; /* 8K bytes */
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__top_RAM = 0x10000000 + 0x2000 ; /* 8K bytes */
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__base_RamUsb2 = 0x20004000 ; /* RamUsb2 */
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__base_RAM2 = 0x20004000 ; /* RAM2 */
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__top_RamUsb2 = 0x20004000 + 0x800 ; /* 2K bytes */
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__top_RAM2 = 0x20004000 + 0x800 ; /* 2K bytes */
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__base_RamPeriph2 = 0x20000000 ; /* RamPeriph2 */
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__base_RAM3 = 0x20000000 ; /* RAM3 */
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__top_RamPeriph2 = 0x20000000 + 0x800 ; /* 2K bytes */
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__top_RAM3 = 0x20000000 + 0x800 ; /* 2K bytes */
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ENTRY(ResetISR)
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SECTIONS
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{
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/* MAIN TEXT SECTION */
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.text : ALIGN(4)
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{
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FILL(0xff)
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__vectors_start__ = ABSOLUTE(.) ;
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KEEP(*(.isr_vector))
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/* Global Section Table */
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. = ALIGN(4) ;
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__section_table_start = .;
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__data_section_table = .;
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LONG(LOADADDR(.data));
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LONG( ADDR(.data));
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LONG( SIZEOF(.data));
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LONG(LOADADDR(.data_RAM2));
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LONG( ADDR(.data_RAM2));
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LONG( SIZEOF(.data_RAM2));
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LONG(LOADADDR(.data_RAM3));
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LONG( ADDR(.data_RAM3));
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LONG( SIZEOF(.data_RAM3));
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__data_section_table_end = .;
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__bss_section_table = .;
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LONG( ADDR(.bss));
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LONG( SIZEOF(.bss));
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LONG( ADDR(.bss_RAM2));
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LONG( SIZEOF(.bss_RAM2));
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LONG( ADDR(.bss_RAM3));
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LONG( SIZEOF(.bss_RAM3));
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__bss_section_table_end = .;
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__section_table_end = . ;
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/* End of Global Section Table */
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*(.after_vectors*)
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} > MFlash64
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.text : ALIGN(4)
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{
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*(.text*)
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*(.rodata .rodata.* .constdata .constdata.*)
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. = ALIGN(4);
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} > MFlash64
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/*
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* for exception handling/unwind - some Newlib functions (in common
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* with C++ and STDC++) use this.
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*/
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.ARM.extab : ALIGN(4)
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{
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*(.ARM.extab* .gnu.linkonce.armextab.*)
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} > MFlash64
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__exidx_start = .;
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.ARM.exidx : ALIGN(4)
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{
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*(.ARM.exidx* .gnu.linkonce.armexidx.*)
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} > MFlash64
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__exidx_end = .;
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_etext = .;
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/* DATA section for RamUsb2 */
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.data_RAM2 : ALIGN(4)
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{
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FILL(0xff)
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PROVIDE(__start_data_RAM2 = .) ;
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*(.ramfunc.$RAM2)
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*(.ramfunc.$RamUsb2)
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*(.data.$RAM2*)
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*(.data.$RamUsb2*)
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. = ALIGN(4) ;
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PROVIDE(__end_data_RAM2 = .) ;
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} > RamUsb2 AT>MFlash64
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/* DATA section for RamPeriph2 */
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.data_RAM3 : ALIGN(4)
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{
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FILL(0xff)
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PROVIDE(__start_data_RAM3 = .) ;
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*(.ramfunc.$RAM3)
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*(.ramfunc.$RamPeriph2)
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*(.data.$RAM3*)
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*(.data.$RamPeriph2*)
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. = ALIGN(4) ;
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PROVIDE(__end_data_RAM3 = .) ;
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} > RamPeriph2 AT>MFlash64
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/* MAIN DATA SECTION */
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.uninit_RESERVED : ALIGN(4)
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{
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KEEP(*(.bss.$RESERVED*))
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. = ALIGN(4) ;
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_end_uninit_RESERVED = .;
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} > RamLoc8
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/* Main DATA section (RamLoc8) */
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.data : ALIGN(4)
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{
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FILL(0xff)
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_data = . ;
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*(vtable)
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*(.ramfunc*)
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*(.data*)
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. = ALIGN(4) ;
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_edata = . ;
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} > RamLoc8 AT>MFlash64
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/* BSS section for RamUsb2 */
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.bss_RAM2 : ALIGN(4)
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{
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PROVIDE(__start_bss_RAM2 = .) ;
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*(.bss.$RAM2*)
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*(.bss.$RamUsb2*)
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. = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
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PROVIDE(__end_bss_RAM2 = .) ;
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} > RamUsb2
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/* BSS section for RamPeriph2 */
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.bss_RAM3 : ALIGN(4)
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{
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PROVIDE(__start_bss_RAM3 = .) ;
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*(.bss.$RAM3*)
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*(.bss.$RamPeriph2*)
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. = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
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PROVIDE(__end_bss_RAM3 = .) ;
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} > RamPeriph2
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/* MAIN BSS SECTION */
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.bss : ALIGN(4)
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{
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_bss = .;
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*(.bss*)
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*(COMMON)
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. = ALIGN(4) ;
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_ebss = .;
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PROVIDE(end = .);
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} > RamLoc8
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/* NOINIT section for RamUsb2 */
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.noinit_RAM2 (NOLOAD) : ALIGN(4)
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{
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*(.noinit.$RAM2*)
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*(.noinit.$RamUsb2*)
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. = ALIGN(4) ;
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} > RamUsb2
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/* NOINIT section for RamPeriph2 */
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.noinit_RAM3 (NOLOAD) : ALIGN(4)
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{
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*(.noinit.$RAM3*)
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*(.noinit.$RamPeriph2*)
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. = ALIGN(4) ;
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} > RamPeriph2
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/* DEFAULT NOINIT SECTION */
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.noinit (NOLOAD): ALIGN(4)
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{
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_noinit = .;
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*(.noinit*)
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. = ALIGN(4) ;
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_end_noinit = .;
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} > RamLoc8
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PROVIDE(_pvHeapStart = DEFINED(__user_heap_base) ? __user_heap_base : .);
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PROVIDE(_vStackTop = DEFINED(__user_stack_top) ? __user_stack_top : __top_RamLoc8 - 0);
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/* ## Create checksum value (used in startup) ## */
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PROVIDE(__valid_user_code_checksum = 0 -
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(_vStackTop
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+ (ResetISR + 1)
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+ (NMI_Handler + 1)
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+ (HardFault_Handler + 1)
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+ (( DEFINED(MemManage_Handler) ? MemManage_Handler : 0 ) + 1) /* MemManage_Handler may not be defined */
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+ (( DEFINED(BusFault_Handler) ? BusFault_Handler : 0 ) + 1) /* BusFault_Handler may not be defined */
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+ (( DEFINED(UsageFault_Handler) ? UsageFault_Handler : 0 ) + 1) /* UsageFault_Handler may not be defined */
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) );
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/* Provide basic symbols giving location and size of main text
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* block, including initial values of RW data sections. Note that
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* these will need extending to give a complete picture with
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* complex images (e.g multiple Flash banks).
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*/
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_image_start = LOADADDR(.text);
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_image_end = LOADADDR(.data) + SIZEOF(.data);
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_image_size = _image_end - _image_start;
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}
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