Initial project setup
This commit is contained in:
@@ -0,0 +1,15 @@
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set(MCU_VARIANT K32L2A41A)
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set(JLINK_DEVICE K32L2A41xxxxA)
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set(PYOCD_TARGET K32L2A)
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set(LD_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/K32L2A41xxxxA_flash.ld)
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function(update_board TARGET)
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target_sources(${TARGET} PUBLIC
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${CMAKE_CURRENT_FUNCTION_LIST_DIR}/clock_config.c
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)
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target_compile_definitions(${TARGET} PUBLIC
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CPU_K32L2A41VLH1A
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)
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endfunction()
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@@ -0,0 +1,96 @@
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/*
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* The MIT License (MIT)
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*
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* Copyright (c) 2019, Ha Thach (tinyusb.org)
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*
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* This file is part of the TinyUSB stack.
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*/
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/* metadata:
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name: Freedom K32L2A4S
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url: https://www.nxp.com/design/design-center/development-boards-and-designs/FRDM-K32L2A4S
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*/
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#ifndef BOARD_H_
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#define BOARD_H_
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#include "fsl_device_registers.h"
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#define USB_CLOCK_SOURCE kCLOCK_IpSrcFircAsync
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// LED
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// The Red LED is on PTE29.
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// The Green LED is on PTC4.
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// The Blue LED is on PTE31.
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#define LED_PIN_CLOCK kCLOCK_PortC
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#define LED_GPIO GPIOC
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#define LED_PORT PORTC
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#define LED_PIN 4
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#define LED_STATE_ON 0
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// SW3 button1
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#define BUTTON_PIN_CLOCK kCLOCK_PortE
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#define BUTTON_GPIO GPIOE
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#define BUTTON_PORT PORTE
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#define BUTTON_PIN 4
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#define BUTTON_STATE_ACTIVE 0
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// UART
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#define UART_PORT LPUART0
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#define UART_PIN_CLOCK kCLOCK_PortB
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#define UART_PIN_GPIO GPIOB
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#define UART_PIN_PORT PORTB
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#define UART_PIN_RX 16u
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#define UART_PIN_TX 17u
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#define UART_CLOCK_SOURCE_HZ CLOCK_GetFreq(kCLOCK_ScgFircClk)
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static inline void BOARD_InitBootPins(void) {
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/*
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Enable LPUART0 clock and configure port pins.
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FIR clock is being used so the USB examples work.
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*/
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PCC_LPUART0 = 0U; /* Clock must be off to set PCS */
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PCC_LPUART0 = PCC_CLKCFG_PCS(
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3U); /* Select the clock. 1:OSCCLK/Bus Clock, 2:Slow IRC, 3: Fast IRC, 6: System PLL */
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PCC_LPUART0 |= PCC_CLKCFG_CGC(1U); /* Enable LPUART */
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/* PORTB16 (pin 62) is configured as LPUART0_RX */
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gpio_pin_config_t const lpuart_config_rx = {kGPIO_DigitalInput, 0};
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GPIO_PinInit(UART_PIN_GPIO, UART_PIN_RX, &lpuart_config_rx);
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const port_pin_config_t UART_CFG = {
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kPORT_PullUp,
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kPORT_FastSlewRate,
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kPORT_PassiveFilterDisable,
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kPORT_OpenDrainDisable,
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kPORT_LowDriveStrength,
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kPORT_MuxAsGpio,
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kPORT_UnlockRegister
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};
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PORT_SetPinConfig(UART_PIN_PORT, UART_PIN_RX, &UART_CFG);
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PORT_SetPinMux(UART_PIN_PORT, UART_PIN_RX, kPORT_MuxAlt3);
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/* PORTB17 (pin 63) is configured as LPUART0_TX */
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gpio_pin_config_t const lpuart_config_tx = {kGPIO_DigitalOutput, 0};
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GPIO_PinInit(UART_PIN_GPIO, UART_PIN_TX, &lpuart_config_tx);
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PORT_SetPinMux(UART_PIN_PORT, UART_PIN_TX, kPORT_MuxAlt3);
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}
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#endif /* BOARD_H_ */
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@@ -0,0 +1,18 @@
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MCU = K32L2A41A
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CFLAGS += -DCPU_K32L2A41VLH1A
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# mcu driver cause following warnings
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CFLAGS_GCC += -Wno-error=unused-parameter -Wno-error=redundant-decls -Wno-error=cast-qual
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# All source paths should be relative to the top level.
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LD_FILE = $(MCU_DIR)/gcc/K32L2A41xxxxA_flash.ld
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# For flash-jlink target
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JLINK_DEVICE = K32L2A41xxxxA
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# For flash-pyocd target
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PYOCD_TARGET = K32L2A
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# flash using pyocd
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flash: flash-pyocd
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@@ -0,0 +1,491 @@
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/*
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* Copyright 2019 ,2021 NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/***********************************************************************************************************************
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* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
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* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
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**********************************************************************************************************************/
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/*
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* How to setup clock using clock driver functions:
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*
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* 1. Call CLOCK_InitXXX() to configure corresponding SCG clock source.
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* Note: The clock could not be set when it is being used as system clock.
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* In default out of reset, the CPU is clocked from FIRC(IRC48M),
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* so before setting FIRC, change to use another available clock source.
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*
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* 2. Call CLOCK_SetXtal0Freq() to set XTAL0 frequency based on board settings.
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*
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* 3. Call CLOCK_SetXxxModeSysClkConfig() to set SCG mode for Xxx run mode.
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* Wait until the system clock source is changed to target source.
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*
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* 4. If power mode change is needed, call SMC_SetPowerModeProtection() to allow
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* corresponding power mode and SMC_SetPowerModeXxx() to change to Xxx mode.
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* Supported run mode and clock restrictions could be found in Reference Manual.
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*/
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/* clang-format off */
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/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
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!!GlobalInfo
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product: Clocks v7.0
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processor: K32L2A41xxxxA
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package_id: K32L2A41VLL1A
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mcu_data: ksdk2_0
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processor_version: 9.0.0
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* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
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/* clang-format on */
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#include "fsl_smc.h"
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#include "clock_config.h"
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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#define SCG_CLKOUTCNFG_SIRC 2U /*!< SCG CLKOUT clock select: Slow IRC */
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#define SCG_SOSC_DISABLE 0U /*!< System OSC disabled */
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#define SCG_SPLL_DISABLE 0U /*!< System PLL disabled */
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#define SCG_SYS_OSC_CAP_0P 0U /*!< Oscillator 0pF capacitor load */
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/*******************************************************************************
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* Variables
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******************************************************************************/
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/* System clock frequency. */
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//extern uint32_t SystemCoreClock;
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/*******************************************************************************
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* Code
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******************************************************************************/
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/*FUNCTION**********************************************************************
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*
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* Function Name : CLOCK_CONFIG_SetScgOutSel
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* Description : Set the SCG clock out select (CLKOUTSEL).
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* Param setting : The selected clock source.
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*
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*END**************************************************************************/
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static void CLOCK_CONFIG_SetScgOutSel(uint8_t setting)
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{
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SCG->CLKOUTCNFG = SCG_CLKOUTCNFG_CLKOUTSEL(setting);
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}
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/*FUNCTION**********************************************************************
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*
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* Function Name : CLOCK_CONFIG_FircSafeConfig
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* Description : This function is used to safely configure FIRC clock.
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* In default out of reset, the CPU is clocked from FIRC(IRC48M).
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* Before setting FIRC, change to use SIRC as system clock,
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* then configure FIRC. After FIRC is set, change back to use FIRC
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* in case SIRC need to be configured.
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* Param fircConfig : FIRC configuration.
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*
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*END**************************************************************************/
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static void CLOCK_CONFIG_FircSafeConfig(const scg_firc_config_t *fircConfig)
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{
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scg_sys_clk_config_t curConfig;
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const scg_sirc_config_t scgSircConfig = {.enableMode = kSCG_SircEnable,
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.div1 = kSCG_AsyncClkDisable,
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.div3 = kSCG_AsyncClkDivBy2,
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.range = kSCG_SircRangeHigh};
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scg_sys_clk_config_t sysClkSafeConfigSource = {
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.divSlow = kSCG_SysClkDivBy4, /* Slow clock divider */
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#if FSL_CLOCK_DRIVER_VERSION < MAKE_VERSION(2, 1, 1)
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.reserved1 = 0,
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.reserved2 = 0,
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.reserved3 = 0,
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#endif
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.divCore = kSCG_SysClkDivBy1, /* Core clock divider */
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#if FSL_CLOCK_DRIVER_VERSION < MAKE_VERSION(2, 1, 1)
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.reserved4 = 0,
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#endif
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.src = kSCG_SysClkSrcSirc, /* System clock source */
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#if FSL_CLOCK_DRIVER_VERSION < MAKE_VERSION(2, 1, 1)
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.reserved5 = 0,
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#endif
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};
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/* Init Sirc. */
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CLOCK_InitSirc(&scgSircConfig);
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/* Change to use SIRC as system clock source to prepare to change FIRCCFG register. */
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CLOCK_SetRunModeSysClkConfig(&sysClkSafeConfigSource);
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/* Wait for clock source switch finished. */
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do
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{
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CLOCK_GetCurSysClkConfig(&curConfig);
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} while (curConfig.src != sysClkSafeConfigSource.src);
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/* Init Firc. */
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CLOCK_InitFirc(fircConfig);
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/* Change back to use FIRC as system clock source in order to configure SIRC if needed. */
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sysClkSafeConfigSource.src = kSCG_SysClkSrcFirc;
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CLOCK_SetRunModeSysClkConfig(&sysClkSafeConfigSource);
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/* Wait for clock source switch finished. */
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do
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{
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CLOCK_GetCurSysClkConfig(&curConfig);
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} while (curConfig.src != sysClkSafeConfigSource.src);
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}
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/*******************************************************************************
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************************ BOARD_InitBootClocks function ************************
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******************************************************************************/
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void BOARD_InitBootClocks(void)
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{
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BOARD_BootClockRUN();
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}
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/*******************************************************************************
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********************** Configuration BOARD_BootClockRUN ***********************
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******************************************************************************/
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/* clang-format off */
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/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
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!!Configuration
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name: BOARD_BootClockRUN
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called_from_default_init: true
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outputs:
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- {id: Core_clock.outFreq, value: 48 MHz}
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- {id: FIRCDIV1_CLK.outFreq, value: 48 MHz}
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- {id: FIRCDIV3_CLK.outFreq, value: 48 MHz}
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- {id: LPO_clock.outFreq, value: 1 kHz}
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- {id: OSC32KCLK.outFreq, value: 32.768 kHz}
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- {id: SIRCDIV3_CLK.outFreq, value: 4 MHz}
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- {id: SIRC_CLK.outFreq, value: 8 MHz}
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- {id: SOSCDIV3_CLK.outFreq, value: 32.768 kHz}
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- {id: SOSCER_CLK.outFreq, value: 32.768 kHz}
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- {id: SOSC_CLK.outFreq, value: 32.768 kHz}
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- {id: Slow_clock.outFreq, value: 24 MHz}
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- {id: System_clock.outFreq, value: 48 MHz}
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settings:
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- {id: SCG.FIRCDIV1.scale, value: '1', locked: true}
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- {id: SCG.FIRCDIV3.scale, value: '1', locked: true}
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- {id: SCG.SIRCDIV3.scale, value: '2', locked: true}
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- {id: SCG.SOSCDIV3.scale, value: '1', locked: true}
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- {id: SCG_SOSCCFG_OSC_MODE_CFG, value: ModeOscLowPower}
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- {id: SCG_SOSCCSR_SOSCEN_CFG, value: Enabled}
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- {id: SCG_SOSCCSR_SOSCERCLKEN_CFG, value: Enabled}
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sources:
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- {id: SCG.SOSC.outFreq, value: 32.768 kHz, enabled: true}
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* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
|
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/* clang-format on */
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/*******************************************************************************
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* Variables for BOARD_BootClockRUN configuration
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******************************************************************************/
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const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockRUN =
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{
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.divSlow = kSCG_SysClkDivBy2, /* Slow Clock Divider: divided by 2 */
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#if FSL_CLOCK_DRIVER_VERSION < MAKE_VERSION(2, 1, 1)
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.reserved1 = 0,
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.reserved2 = 0,
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.reserved3 = 0,
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#endif
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.divCore = kSCG_SysClkDivBy1, /* Core Clock Divider: divided by 1 */
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#if FSL_CLOCK_DRIVER_VERSION < MAKE_VERSION(2, 1, 1)
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.reserved4 = 0,
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#endif
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.src = kSCG_SysClkSrcFirc, /* Fast IRC is selected as System Clock Source */
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#if FSL_CLOCK_DRIVER_VERSION < MAKE_VERSION(2, 1, 1)
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.reserved5 = 0,
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#endif
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};
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const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockRUN =
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{
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.freq = 32768U, /* System Oscillator frequency: 32768Hz */
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.enableMode = kSCG_SysOscEnable | kSCG_SysOscEnableErClk,/* Enable System OSC clock, Enable OSCERCLK */
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.monitorMode = kSCG_SysOscMonitorDisable, /* Monitor disabled */
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.div1 = kSCG_AsyncClkDisable, /* System OSC Clock Divider 1: Clock output is disabled */
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.div3 = kSCG_AsyncClkDivBy1, /* System OSC Clock Divider 3: divided by 1 */
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.capLoad = SCG_SYS_OSC_CAP_0P, /* Oscillator capacity load: 0pF */
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.workMode = kSCG_SysOscModeOscLowPower, /* Oscillator low power */
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};
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const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockRUN =
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{
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.enableMode = kSCG_SircEnable | kSCG_SircEnableInLowPower,/* Enable SIRC clock, Enable SIRC in low power mode */
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.div1 = kSCG_AsyncClkDisable, /* Slow IRC Clock Divider 1: Clock output is disabled */
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.div3 = kSCG_AsyncClkDivBy2, /* Slow IRC Clock Divider 3: divided by 2 */
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.range = kSCG_SircRangeHigh, /* Slow IRC high range clock (8 MHz) */
|
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};
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const scg_firc_config_t g_scgFircConfig_BOARD_BootClockRUN =
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{
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.enableMode = kSCG_FircEnable, /* Enable FIRC clock */
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.div1 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 1: divided by 1 */
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.div3 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 3: divided by 1 */
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||||
.range = kSCG_FircRange48M, /* Fast IRC is trimmed to 48MHz */
|
||||
.trimConfig = NULL, /* Fast IRC Trim disabled */
|
||||
};
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||||
const scg_spll_config_t g_scgSysPllConfig_BOARD_BootClockRUN =
|
||||
{
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||||
.enableMode = SCG_SPLL_DISABLE, /* System PLL disabled */
|
||||
.monitorMode = kSCG_SysPllMonitorDisable, /* Monitor disabled */
|
||||
.div1 = kSCG_AsyncClkDisable, /* System PLL Clock Divider 1: Clock output is disabled */
|
||||
.div3 = kSCG_AsyncClkDisable, /* System PLL Clock Divider 3: Clock output is disabled */
|
||||
.src = kSCG_SysPllSrcSysOsc, /* System PLL clock source is System OSC */
|
||||
.prediv = 0, /* Divided by 1 */
|
||||
.mult = 0, /* Multiply Factor is 16 */
|
||||
};
|
||||
/*******************************************************************************
|
||||
* Code for BOARD_BootClockRUN configuration
|
||||
******************************************************************************/
|
||||
void BOARD_BootClockRUN(void)
|
||||
{
|
||||
scg_sys_clk_config_t curConfig;
|
||||
|
||||
/* Init SOSC according to board configuration. */
|
||||
CLOCK_InitSysOsc(&g_scgSysOscConfig_BOARD_BootClockRUN);
|
||||
/* Set the XTAL0 frequency based on board settings. */
|
||||
CLOCK_SetXtal0Freq(g_scgSysOscConfig_BOARD_BootClockRUN.freq);
|
||||
/* Init FIRC. */
|
||||
CLOCK_CONFIG_FircSafeConfig(&g_scgFircConfig_BOARD_BootClockRUN);
|
||||
/* Init SIRC. */
|
||||
CLOCK_InitSirc(&g_scgSircConfig_BOARD_BootClockRUN);
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||||
/* Set SCG to FIRC mode. */
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CLOCK_SetRunModeSysClkConfig(&g_sysClkConfig_BOARD_BootClockRUN);
|
||||
/* Wait for clock source switch finished. */
|
||||
do
|
||||
{
|
||||
CLOCK_GetCurSysClkConfig(&curConfig);
|
||||
} while (curConfig.src != g_sysClkConfig_BOARD_BootClockRUN.src);
|
||||
/* Set SystemCoreClock variable. */
|
||||
SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
********************* Configuration BOARD_BootClockHSRUN **********************
|
||||
******************************************************************************/
|
||||
/* clang-format off */
|
||||
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
!!Configuration
|
||||
name: BOARD_BootClockHSRUN
|
||||
outputs:
|
||||
- {id: CLKOUT.outFreq, value: 8 MHz}
|
||||
- {id: Core_clock.outFreq, value: 96 MHz, locked: true, accuracy: '0.001'}
|
||||
- {id: FIRCDIV1_CLK.outFreq, value: 48 MHz}
|
||||
- {id: FIRCDIV3_CLK.outFreq, value: 48 MHz}
|
||||
- {id: LPO_clock.outFreq, value: 1 kHz}
|
||||
- {id: OSC32KCLK.outFreq, value: 32.768 kHz}
|
||||
- {id: PLLDIV1_CLK.outFreq, value: 96 MHz}
|
||||
- {id: PLLDIV3_CLK.outFreq, value: 96 MHz}
|
||||
- {id: SIRCDIV1_CLK.outFreq, value: 8 MHz}
|
||||
- {id: SIRCDIV3_CLK.outFreq, value: 8 MHz}
|
||||
- {id: SIRC_CLK.outFreq, value: 8 MHz}
|
||||
- {id: SOSCDIV1_CLK.outFreq, value: 32.768 kHz}
|
||||
- {id: SOSCDIV3_CLK.outFreq, value: 32.768 kHz}
|
||||
- {id: SOSCER_CLK.outFreq, value: 32.768 kHz}
|
||||
- {id: SOSC_CLK.outFreq, value: 32.768 kHz}
|
||||
- {id: Slow_clock.outFreq, value: 24 MHz, locked: true, accuracy: '0.001'}
|
||||
- {id: System_clock.outFreq, value: 96 MHz}
|
||||
settings:
|
||||
- {id: SCGMode, value: SPLL}
|
||||
- {id: powerMode, value: HSRUN}
|
||||
- {id: CLKOUTConfig, value: 'yes'}
|
||||
- {id: SCG.DIVSLOW.scale, value: '4'}
|
||||
- {id: SCG.FIRCDIV1.scale, value: '1', locked: true}
|
||||
- {id: SCG.FIRCDIV3.scale, value: '1', locked: true}
|
||||
- {id: SCG.PREDIV.scale, value: '4'}
|
||||
- {id: SCG.SCSSEL.sel, value: SCG.SPLL_DIV2_CLK}
|
||||
- {id: SCG.SIRCDIV1.scale, value: '1', locked: true}
|
||||
- {id: SCG.SIRCDIV3.scale, value: '1', locked: true}
|
||||
- {id: SCG.SOSCDIV1.scale, value: '1', locked: true}
|
||||
- {id: SCG.SOSCDIV3.scale, value: '1', locked: true}
|
||||
- {id: SCG.SPLLDIV1.scale, value: '1', locked: true}
|
||||
- {id: SCG.SPLLDIV3.scale, value: '1', locked: true}
|
||||
- {id: SCG.SPLLSRCSEL.sel, value: SCG.FIRC}
|
||||
- {id: SCG_SOSCCFG_OSC_MODE_CFG, value: ModeOscLowPower}
|
||||
- {id: SCG_SOSCCSR_SOSCEN_CFG, value: Enabled}
|
||||
- {id: SCG_SOSCCSR_SOSCERCLKEN_CFG, value: Enabled}
|
||||
- {id: SCG_SPLLCSR_SPLLEN_CFG, value: Enabled}
|
||||
sources:
|
||||
- {id: SCG.SOSC.outFreq, value: 32.768 kHz, enabled: true}
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
|
||||
/* clang-format on */
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables for BOARD_BootClockHSRUN configuration
|
||||
******************************************************************************/
|
||||
const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockHSRUN =
|
||||
{
|
||||
.divSlow = kSCG_SysClkDivBy4, /* Slow Clock Divider: divided by 4 */
|
||||
#if FSL_CLOCK_DRIVER_VERSION < MAKE_VERSION(2, 1, 1)
|
||||
.reserved1 = 0,
|
||||
.reserved2 = 0,
|
||||
.reserved3 = 0,
|
||||
#endif
|
||||
.divCore = kSCG_SysClkDivBy1, /* Core Clock Divider: divided by 1 */
|
||||
#if FSL_CLOCK_DRIVER_VERSION < MAKE_VERSION(2, 1, 1)
|
||||
.reserved4 = 0,
|
||||
#endif
|
||||
.src = kSCG_SysClkSrcSysPll, /* System PLL is selected as System Clock Source */
|
||||
#if FSL_CLOCK_DRIVER_VERSION < MAKE_VERSION(2, 1, 1)
|
||||
.reserved5 = 0,
|
||||
#endif
|
||||
};
|
||||
const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockHSRUN =
|
||||
{
|
||||
.freq = 32768U, /* System Oscillator frequency: 32768Hz */
|
||||
.enableMode = kSCG_SysOscEnable | kSCG_SysOscEnableErClk,/* Enable System OSC clock, Enable OSCERCLK */
|
||||
.monitorMode = kSCG_SysOscMonitorDisable, /* Monitor disabled */
|
||||
.div1 = kSCG_AsyncClkDivBy1, /* System OSC Clock Divider 1: divided by 1 */
|
||||
.div3 = kSCG_AsyncClkDivBy1, /* System OSC Clock Divider 3: divided by 1 */
|
||||
.capLoad = SCG_SYS_OSC_CAP_0P, /* Oscillator capacity load: 0pF */
|
||||
.workMode = kSCG_SysOscModeOscLowPower, /* Oscillator low power */
|
||||
};
|
||||
const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockHSRUN =
|
||||
{
|
||||
.enableMode = kSCG_SircEnable | kSCG_SircEnableInLowPower,/* Enable SIRC clock, Enable SIRC in low power mode */
|
||||
.div1 = kSCG_AsyncClkDivBy1, /* Slow IRC Clock Divider 1: divided by 1 */
|
||||
.div3 = kSCG_AsyncClkDivBy1, /* Slow IRC Clock Divider 3: divided by 1 */
|
||||
.range = kSCG_SircRangeHigh, /* Slow IRC high range clock (8 MHz) */
|
||||
};
|
||||
const scg_firc_config_t g_scgFircConfig_BOARD_BootClockHSRUN =
|
||||
{
|
||||
.enableMode = kSCG_FircEnable, /* Enable FIRC clock */
|
||||
.div1 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 1: divided by 1 */
|
||||
.div3 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 3: divided by 1 */
|
||||
.range = kSCG_FircRange48M, /* Fast IRC is trimmed to 48MHz */
|
||||
.trimConfig = NULL, /* Fast IRC Trim disabled */
|
||||
};
|
||||
const scg_spll_config_t g_scgSysPllConfig_BOARD_BootClockHSRUN =
|
||||
{
|
||||
.enableMode = kSCG_SysPllEnable, /* Enable SPLL clock */
|
||||
.monitorMode = kSCG_SysPllMonitorDisable, /* Monitor disabled */
|
||||
.div1 = kSCG_AsyncClkDivBy1, /* System PLL Clock Divider 1: divided by 1 */
|
||||
.div3 = kSCG_AsyncClkDivBy1, /* System PLL Clock Divider 3: divided by 1 */
|
||||
.src = kSCG_SysPllSrcFirc, /* System PLL clock source is Fast IRC */
|
||||
.prediv = 3, /* Divided by 4 */
|
||||
.mult = 0, /* Multiply Factor is 16 */
|
||||
};
|
||||
/*******************************************************************************
|
||||
* Code for BOARD_BootClockHSRUN configuration
|
||||
******************************************************************************/
|
||||
void BOARD_BootClockHSRUN(void)
|
||||
{
|
||||
scg_sys_clk_config_t curConfig;
|
||||
|
||||
/* Init SOSC according to board configuration. */
|
||||
CLOCK_InitSysOsc(&g_scgSysOscConfig_BOARD_BootClockHSRUN);
|
||||
/* Set the XTAL0 frequency based on board settings. */
|
||||
CLOCK_SetXtal0Freq(g_scgSysOscConfig_BOARD_BootClockHSRUN.freq);
|
||||
/* Init FIRC. */
|
||||
CLOCK_CONFIG_FircSafeConfig(&g_scgFircConfig_BOARD_BootClockHSRUN);
|
||||
/* Init SIRC. */
|
||||
CLOCK_InitSirc(&g_scgSircConfig_BOARD_BootClockHSRUN);
|
||||
/* Init SysPll. */
|
||||
CLOCK_InitSysPll(&g_scgSysPllConfig_BOARD_BootClockHSRUN);
|
||||
/* Set HSRUN power mode. */
|
||||
SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
|
||||
SMC_SetPowerModeHsrun(SMC);
|
||||
while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateHsrun)
|
||||
{
|
||||
}
|
||||
|
||||
/* Set SCG to SPLL mode. */
|
||||
CLOCK_SetHsrunModeSysClkConfig(&g_sysClkConfig_BOARD_BootClockHSRUN);
|
||||
/* Wait for clock source switch finished. */
|
||||
do
|
||||
{
|
||||
CLOCK_GetCurSysClkConfig(&curConfig);
|
||||
} while (curConfig.src != g_sysClkConfig_BOARD_BootClockHSRUN.src);
|
||||
/* Set SystemCoreClock variable. */
|
||||
SystemCoreClock = BOARD_BOOTCLOCKHSRUN_CORE_CLOCK;
|
||||
/* Set SCG CLKOUT selection. */
|
||||
CLOCK_CONFIG_SetScgOutSel(SCG_CLKOUTCNFG_SIRC);
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
********************* Configuration BOARD_BootClockVLPR ***********************
|
||||
******************************************************************************/
|
||||
/* clang-format off */
|
||||
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
!!Configuration
|
||||
name: BOARD_BootClockVLPR
|
||||
outputs:
|
||||
- {id: Core_clock.outFreq, value: 8 MHz, locked: true, accuracy: '0.001'}
|
||||
- {id: LPO_clock.outFreq, value: 1 kHz}
|
||||
- {id: SIRC_CLK.outFreq, value: 8 MHz}
|
||||
- {id: Slow_clock.outFreq, value: 1 MHz, locked: true, accuracy: '0.001'}
|
||||
- {id: System_clock.outFreq, value: 8 MHz}
|
||||
settings:
|
||||
- {id: SCGMode, value: SIRC}
|
||||
- {id: powerMode, value: VLPR}
|
||||
- {id: SCG.DIVSLOW.scale, value: '8'}
|
||||
- {id: SCG.SCSSEL.sel, value: SCG.SIRC}
|
||||
- {id: SCG_FIRCCSR_FIRCLPEN_CFG, value: Enabled}
|
||||
sources:
|
||||
- {id: SCG.SOSC.outFreq, value: 32.768 kHz, enabled: true}
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
|
||||
/* clang-format on */
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables for BOARD_BootClockVLPR configuration
|
||||
******************************************************************************/
|
||||
const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockVLPR =
|
||||
{
|
||||
.divSlow = kSCG_SysClkDivBy8, /* Slow Clock Divider: divided by 8 */
|
||||
#if FSL_CLOCK_DRIVER_VERSION < MAKE_VERSION(2, 1, 1)
|
||||
.reserved1 = 0,
|
||||
.reserved2 = 0,
|
||||
.reserved3 = 0,
|
||||
#endif
|
||||
.divCore = kSCG_SysClkDivBy1, /* Core Clock Divider: divided by 1 */
|
||||
#if FSL_CLOCK_DRIVER_VERSION < MAKE_VERSION(2, 1, 1)
|
||||
.reserved4 = 0,
|
||||
#endif
|
||||
.src = kSCG_SysClkSrcSirc, /* Slow IRC is selected as System Clock Source */
|
||||
#if FSL_CLOCK_DRIVER_VERSION < MAKE_VERSION(2, 1, 1)
|
||||
.reserved5 = 0,
|
||||
#endif
|
||||
};
|
||||
const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockVLPR =
|
||||
{
|
||||
.freq = 0U, /* System Oscillator frequency: 0Hz */
|
||||
.enableMode = SCG_SOSC_DISABLE, /* System OSC disabled */
|
||||
.monitorMode = kSCG_SysOscMonitorDisable, /* Monitor disabled */
|
||||
.div1 = kSCG_AsyncClkDisable, /* System OSC Clock Divider 1: Clock output is disabled */
|
||||
.div3 = kSCG_AsyncClkDisable, /* System OSC Clock Divider 3: Clock output is disabled */
|
||||
.capLoad = SCG_SYS_OSC_CAP_0P, /* Oscillator capacity load: 0pF */
|
||||
.workMode = kSCG_SysOscModeExt, /* Use external clock */
|
||||
};
|
||||
const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockVLPR =
|
||||
{
|
||||
.enableMode = kSCG_SircEnable | kSCG_SircEnableInLowPower,/* Enable SIRC clock, Enable SIRC in low power mode */
|
||||
.div1 = kSCG_AsyncClkDisable, /* Slow IRC Clock Divider 1: Clock output is disabled */
|
||||
.div3 = kSCG_AsyncClkDisable, /* Slow IRC Clock Divider 3: Clock output is disabled */
|
||||
.range = kSCG_SircRangeHigh, /* Slow IRC high range clock (8 MHz) */
|
||||
};
|
||||
const scg_firc_config_t g_scgFircConfig_BOARD_BootClockVLPR =
|
||||
{
|
||||
.enableMode = kSCG_FircEnable | kSCG_FircEnableInLowPower,/* Enable FIRC clock, Enable FIRC in low power mode */
|
||||
.div1 = kSCG_AsyncClkDisable, /* Fast IRC Clock Divider 1: Clock output is disabled */
|
||||
.div3 = kSCG_AsyncClkDisable, /* Fast IRC Clock Divider 3: Clock output is disabled */
|
||||
.range = kSCG_FircRange48M, /* Fast IRC is trimmed to 48MHz */
|
||||
.trimConfig = NULL, /* Fast IRC Trim disabled */
|
||||
};
|
||||
const scg_spll_config_t g_scgSysPllConfig_BOARD_BootClockVLPR =
|
||||
{
|
||||
.enableMode = SCG_SPLL_DISABLE, /* System PLL disabled */
|
||||
.monitorMode = kSCG_SysPllMonitorDisable, /* Monitor disabled */
|
||||
.div1 = kSCG_AsyncClkDisable, /* System PLL Clock Divider 1: Clock output is disabled */
|
||||
.div3 = kSCG_AsyncClkDisable, /* System PLL Clock Divider 3: Clock output is disabled */
|
||||
.src = kSCG_SysPllSrcSysOsc, /* System PLL clock source is System OSC */
|
||||
.prediv = 0, /* Divided by 1 */
|
||||
.mult = 0, /* Multiply Factor is 16 */
|
||||
};
|
||||
/*******************************************************************************
|
||||
* Code for BOARD_BootClockVLPR configuration
|
||||
******************************************************************************/
|
||||
void BOARD_BootClockVLPR(void)
|
||||
{
|
||||
/* Init FIRC. */
|
||||
CLOCK_CONFIG_FircSafeConfig(&g_scgFircConfig_BOARD_BootClockVLPR);
|
||||
/* Init SIRC. */
|
||||
CLOCK_InitSirc(&g_scgSircConfig_BOARD_BootClockVLPR);
|
||||
/* Allow SMC all power modes. */
|
||||
SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
|
||||
/* Set VLPR power mode. */
|
||||
SMC_SetPowerModeVlpr(SMC);
|
||||
while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr)
|
||||
{
|
||||
}
|
||||
/* Set SystemCoreClock variable. */
|
||||
SystemCoreClock = BOARD_BOOTCLOCKVLPR_CORE_CLOCK;
|
||||
}
|
||||
@@ -0,0 +1,164 @@
|
||||
/*
|
||||
* Copyright 2019 ,2021 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
|
||||
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
#ifndef _CLOCK_CONFIG_H_
|
||||
#define _CLOCK_CONFIG_H_
|
||||
|
||||
#include "fsl_common.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
#define BOARD_XTAL0_CLK_HZ 32768U /*!< Board xtal0 frequency in Hz */
|
||||
|
||||
/*******************************************************************************
|
||||
************************ BOARD_InitBootClocks function ************************
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*!
|
||||
* @brief This function executes default configuration of clocks.
|
||||
*
|
||||
*/
|
||||
void BOARD_InitBootClocks(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*******************************************************************************
|
||||
********************** Configuration BOARD_BootClockRUN ***********************
|
||||
******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* Definitions for BOARD_BootClockRUN configuration
|
||||
******************************************************************************/
|
||||
#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 48000000U /*!< Core clock frequency: 48000000Hz */
|
||||
|
||||
/*! @brief SCG set for BOARD_BootClockRUN configuration.
|
||||
*/
|
||||
extern const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockRUN;
|
||||
/*! @brief System OSC set for BOARD_BootClockRUN configuration.
|
||||
*/
|
||||
extern const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockRUN;
|
||||
/*! @brief SIRC set for BOARD_BootClockRUN configuration.
|
||||
*/
|
||||
extern const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockRUN;
|
||||
/*! @brief FIRC set for BOARD_BootClockRUN configuration.
|
||||
*/
|
||||
extern const scg_firc_config_t g_scgFircConfigBOARD_BootClockRUN;
|
||||
extern const scg_spll_config_t g_scgSysPllConfigBOARD_BootClockRUN;
|
||||
/*! @brief Low Power FLL set for BOARD_BootClockRUN configuration.
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* API for BOARD_BootClockRUN configuration
|
||||
******************************************************************************/
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*!
|
||||
* @brief This function executes configuration of clocks.
|
||||
*
|
||||
*/
|
||||
void BOARD_BootClockRUN(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*******************************************************************************
|
||||
********************* Configuration BOARD_BootClockHSRUN **********************
|
||||
******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* Definitions for BOARD_BootClockHSRUN configuration
|
||||
******************************************************************************/
|
||||
#define BOARD_BOOTCLOCKHSRUN_CORE_CLOCK 96000000U /*!< Core clock frequency: 96000000Hz */
|
||||
|
||||
/*! @brief SCG set for BOARD_BootClockHSRUN configuration.
|
||||
*/
|
||||
extern const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockHSRUN;
|
||||
/*! @brief System OSC set for BOARD_BootClockHSRUN configuration.
|
||||
*/
|
||||
extern const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockHSRUN;
|
||||
/*! @brief SIRC set for BOARD_BootClockHSRUN configuration.
|
||||
*/
|
||||
extern const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockHSRUN;
|
||||
/*! @brief FIRC set for BOARD_BootClockHSRUN configuration.
|
||||
*/
|
||||
extern const scg_firc_config_t g_scgFircConfigBOARD_BootClockHSRUN;
|
||||
extern const scg_spll_config_t g_scgSysPllConfigBOARD_BootClockHSRUN;
|
||||
/*! @brief Low Power FLL set for BOARD_BootClockHSRUN configuration.
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* API for BOARD_BootClockHSRUN configuration
|
||||
******************************************************************************/
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*!
|
||||
* @brief This function executes configuration of clocks.
|
||||
*
|
||||
*/
|
||||
void BOARD_BootClockHSRUN(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*******************************************************************************
|
||||
********************* Configuration BOARD_BootClockVLPR ***********************
|
||||
******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* Definitions for BOARD_BootClockVLPR configuration
|
||||
******************************************************************************/
|
||||
#define BOARD_BOOTCLOCKVLPR_CORE_CLOCK 8000000U /*!< Core clock frequency: 8000000Hz */
|
||||
|
||||
/*! @brief SCG set for BOARD_BootClockVLPR configuration.
|
||||
*/
|
||||
extern const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockVLPR;
|
||||
/*! @brief System OSC set for BOARD_BootClockVLPR configuration.
|
||||
*/
|
||||
extern const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockVLPR;
|
||||
/*! @brief SIRC set for BOARD_BootClockVLPR configuration.
|
||||
*/
|
||||
extern const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockVLPR;
|
||||
/*! @brief FIRC set for BOARD_BootClockVLPR configuration.
|
||||
*/
|
||||
extern const scg_firc_config_t g_scgFircConfigBOARD_BootClockVLPR;
|
||||
extern const scg_spll_config_t g_scgSysPllConfigBOARD_BootClockVLPR;
|
||||
/*! @brief Low Power FLL set for BOARD_BootClockVLPR configuration.
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* API for BOARD_BootClockVLPR configuration
|
||||
******************************************************************************/
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*!
|
||||
* @brief This function executes configuration of clocks.
|
||||
*
|
||||
*/
|
||||
void BOARD_BootClockVLPR(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
#endif /* _CLOCK_CONFIG_H_ */
|
||||
@@ -0,0 +1,15 @@
|
||||
set(MCU_VARIANT K32L2B31A)
|
||||
|
||||
set(JLINK_DEVICE K32L2B31xxxxA)
|
||||
set(PYOCD_TARGET K32L2B)
|
||||
|
||||
set(LD_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/K32L2B31xxxxA_flash.ld)
|
||||
|
||||
function(update_board TARGET)
|
||||
target_sources(${TARGET} PUBLIC
|
||||
${CMAKE_CURRENT_FUNCTION_LIST_DIR}/clock_config.c
|
||||
)
|
||||
target_compile_definitions(${TARGET} PUBLIC
|
||||
CPU_K32L2B31VLH0A
|
||||
)
|
||||
endfunction()
|
||||
@@ -0,0 +1,82 @@
|
||||
/*
|
||||
* The MIT License (MIT)
|
||||
*
|
||||
* Copyright (c) 2019, Ha Thach (tinyusb.org)
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
* THE SOFTWARE.
|
||||
*
|
||||
* This file is part of the TinyUSB stack.
|
||||
*/
|
||||
|
||||
/* metadata:
|
||||
name: Freedom K32L2B3
|
||||
url: https://www.nxp.com/design/design-center/development-boards-and-designs/general-purpose-mcus/nxp-freedom-development-platform-for-k32-l2b-mcus:FRDM-K32L2B3
|
||||
*/
|
||||
|
||||
#ifndef BOARD_H_
|
||||
#define BOARD_H_
|
||||
|
||||
#include "fsl_device_registers.h"
|
||||
|
||||
#define USB_CLOCK_SOURCE kCLOCK_UsbSrcIrc48M
|
||||
|
||||
// LED
|
||||
#define LED_PIN_CLOCK kCLOCK_PortD
|
||||
#define LED_GPIO GPIOD
|
||||
#define LED_PORT PORTD
|
||||
#define LED_PIN 5
|
||||
#define LED_STATE_ON 0
|
||||
|
||||
// SW3 button1
|
||||
#define BUTTON_PIN_CLOCK kCLOCK_PortC
|
||||
#define BUTTON_GPIO GPIOC
|
||||
#define BUTTON_PORT PORTC
|
||||
#define BUTTON_PIN 3
|
||||
#define BUTTON_STATE_ACTIVE 0
|
||||
|
||||
// UART
|
||||
#define UART_PORT LPUART0
|
||||
#define UART_PIN_CLOCK kCLOCK_PortA
|
||||
#define UART_PIN_PORT PORTA
|
||||
#define UART_PIN_RX 1u
|
||||
#define UART_PIN_TX 2u
|
||||
#define SOPT5_LPUART0RXSRC_LPUART_RX 0x00u /*!<@brief LPUART0 Receive Data Source Select: LPUART_RX pin */
|
||||
#define SOPT5_LPUART0TXSRC_LPUART_TX 0x00u /*!<@brief LPUART0 Transmit Data Source Select: LPUART0_TX pin */
|
||||
#define UART_CLOCK_SOURCE_HZ CLOCK_GetFreq(kCLOCK_McgIrc48MClk)
|
||||
|
||||
static inline void BOARD_InitBootPins(void) {
|
||||
/* PORTA1 (pin 23) is configured as LPUART0_RX */
|
||||
PORT_SetPinMux(PORTA, 1U, kPORT_MuxAlt2);
|
||||
/* PORTA2 (pin 24) is configured as LPUART0_TX */
|
||||
PORT_SetPinMux(PORTA, 2U, kPORT_MuxAlt2);
|
||||
|
||||
SIM->SOPT5 = ((SIM->SOPT5 &
|
||||
/* Mask bits to zero which are setting */
|
||||
(~(SIM_SOPT5_LPUART0TXSRC_MASK | SIM_SOPT5_LPUART0RXSRC_MASK)))
|
||||
/* LPUART0 Transmit Data Source Select: LPUART0_TX pin. */
|
||||
| SIM_SOPT5_LPUART0TXSRC(SOPT5_LPUART0TXSRC_LPUART_TX)
|
||||
/* LPUART0 Receive Data Source Select: LPUART_RX pin. */
|
||||
| SIM_SOPT5_LPUART0RXSRC(SOPT5_LPUART0RXSRC_LPUART_RX));
|
||||
|
||||
BOARD_BootClockRUN();
|
||||
SystemCoreClockUpdate();
|
||||
CLOCK_SetLpuart0Clock(1);
|
||||
}
|
||||
|
||||
#endif /* BOARD_H_ */
|
||||
@@ -0,0 +1,18 @@
|
||||
MCU = K32L2B31A
|
||||
|
||||
CFLAGS += -DCPU_K32L2B31VLH0A
|
||||
|
||||
# mcu driver cause following warnings
|
||||
CFLAGS += -Wno-error=unused-parameter -Wno-error=redundant-decls
|
||||
|
||||
# All source paths should be relative to the top level.
|
||||
LD_FILE = $(MCU_DIR)/gcc/K32L2B31xxxxA_flash.ld
|
||||
|
||||
# For flash-jlink target
|
||||
JLINK_DEVICE = K32L2B31xxxxA
|
||||
|
||||
# For flash-pyocd target
|
||||
PYOCD_TARGET = K32L2B
|
||||
|
||||
# flash using pyocd
|
||||
flash: flash-pyocd
|
||||
@@ -0,0 +1,220 @@
|
||||
/*
|
||||
* Copyright 2019 ,2021 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
|
||||
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
|
||||
**********************************************************************************************************************/
|
||||
/*
|
||||
* How to setup clock using clock driver functions:
|
||||
*
|
||||
* 1. CLOCK_SetSimSafeDivs, to make sure core clock, bus clock, flexbus clock
|
||||
* and flash clock are in allowed range during clock mode switch.
|
||||
*
|
||||
* 2. Call CLOCK_Osc0Init to setup OSC clock, if it is used in target mode.
|
||||
*
|
||||
* 3. Call CLOCK_SetMcgliteConfig to set MCG_Lite configuration.
|
||||
*
|
||||
* 4. Call CLOCK_SetSimConfig to set the clock configuration in SIM.
|
||||
*/
|
||||
|
||||
/* clang-format off */
|
||||
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
!!GlobalInfo
|
||||
product: Clocks v7.0
|
||||
processor: K32L2B31xxxxA
|
||||
package_id: K32L2B31VLH0A
|
||||
mcu_data: ksdk2_0
|
||||
processor_version: 9.0.0
|
||||
board: FRDM-K32L2B
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
|
||||
/* clang-format on */
|
||||
|
||||
#include "fsl_smc.h"
|
||||
#include "clock_config.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
#define OSC_CAP0P 0U /*!< Oscillator 0pF capacitor load */
|
||||
#define OSC_ER_CLK_DISABLE 0U /*!< Disable external reference clock */
|
||||
#define SIM_OSC32KSEL_OSC32KCLK_CLK 0U /*!< OSC32KSEL select: OSC32KCLK clock */
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables
|
||||
******************************************************************************/
|
||||
/* System clock frequency. */
|
||||
//extern uint32_t SystemCoreClock;
|
||||
|
||||
/*******************************************************************************
|
||||
************************ BOARD_InitBootClocks function ************************
|
||||
******************************************************************************/
|
||||
void BOARD_InitBootClocks(void)
|
||||
{
|
||||
BOARD_BootClockRUN();
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
********************** Configuration BOARD_BootClockRUN ***********************
|
||||
******************************************************************************/
|
||||
/* clang-format off */
|
||||
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
!!Configuration
|
||||
name: BOARD_BootClockRUN
|
||||
called_from_default_init: true
|
||||
outputs:
|
||||
- {id: Bus_clock.outFreq, value: 24 MHz}
|
||||
- {id: Core_clock.outFreq, value: 48 MHz}
|
||||
- {id: Flash_clock.outFreq, value: 24 MHz}
|
||||
- {id: LPO_clock.outFreq, value: 1 kHz}
|
||||
- {id: MCGIRCLK.outFreq, value: 8 MHz}
|
||||
- {id: MCGPCLK.outFreq, value: 48 MHz}
|
||||
- {id: System_clock.outFreq, value: 48 MHz}
|
||||
settings:
|
||||
- {id: MCGMode, value: HIRC}
|
||||
- {id: MCG.CLKS.sel, value: MCG.HIRC}
|
||||
- {id: MCG_C2_OSC_MODE_CFG, value: ModeOscLowPower}
|
||||
- {id: MCG_C2_RANGE0_CFG, value: Very_high}
|
||||
- {id: MCG_MC_HIRCEN_CFG, value: Enabled}
|
||||
- {id: OSC0_CR_ERCLKEN_CFG, value: Enabled}
|
||||
- {id: OSC_CR_ERCLKEN_CFG, value: Enabled}
|
||||
- {id: SIM.CLKOUTSEL.sel, value: MCG.MCGPCLK}
|
||||
- {id: SIM.COPCLKSEL.sel, value: OSC.OSCERCLK}
|
||||
- {id: SIM.FLEXIOSRCSEL.sel, value: MCG.MCGPCLK}
|
||||
- {id: SIM.LPUART0SRCSEL.sel, value: MCG.MCGPCLK}
|
||||
- {id: SIM.LPUART1SRCSEL.sel, value: MCG.MCGPCLK}
|
||||
- {id: SIM.RTCCLKOUTSEL.sel, value: OSC.OSCERCLK}
|
||||
- {id: SIM.TPMSRCSEL.sel, value: MCG.MCGPCLK}
|
||||
- {id: SIM.USBSRCSEL.sel, value: MCG.MCGPCLK}
|
||||
sources:
|
||||
- {id: MCG.HIRC.outFreq, value: 48 MHz}
|
||||
- {id: OSC.OSC.outFreq, value: 32 MHz}
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
|
||||
/* clang-format on */
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables for BOARD_BootClockRUN configuration
|
||||
******************************************************************************/
|
||||
const mcglite_config_t mcgliteConfig_BOARD_BootClockRUN =
|
||||
{
|
||||
.outSrc = kMCGLITE_ClkSrcHirc, /* MCGOUTCLK source is HIRC */
|
||||
.irclkEnableMode = kMCGLITE_IrclkEnable, /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
|
||||
.ircs = kMCGLITE_Lirc8M, /* Slow internal reference (LIRC) 8 MHz clock selected */
|
||||
.fcrdiv = kMCGLITE_LircDivBy1, /* Low-frequency Internal Reference Clock Divider: divided by 1 */
|
||||
.lircDiv2 = kMCGLITE_LircDivBy1, /* Second Low-frequency Internal Reference Clock Divider: divided by 1 */
|
||||
.hircEnableInNotHircMode = true, /* HIRC source is enabled */
|
||||
};
|
||||
const sim_clock_config_t simConfig_BOARD_BootClockRUN =
|
||||
{
|
||||
.er32kSrc = SIM_OSC32KSEL_OSC32KCLK_CLK, /* OSC32KSEL select: OSC32KCLK clock */
|
||||
.clkdiv1 = 0x10000U, /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV4: /2 */
|
||||
};
|
||||
const osc_config_t oscConfig_BOARD_BootClockRUN =
|
||||
{
|
||||
.freq = 0U, /* Oscillator frequency: 0Hz */
|
||||
.capLoad = (OSC_CAP0P), /* Oscillator capacity load: 0pF */
|
||||
.workMode = kOSC_ModeOscLowPower, /* Oscillator low power */
|
||||
.oscerConfig =
|
||||
{
|
||||
.enableMode = kOSC_ErClkEnable, /* Enable external reference clock, disable external reference clock in STOP mode */
|
||||
}
|
||||
};
|
||||
|
||||
/*******************************************************************************
|
||||
* Code for BOARD_BootClockRUN configuration
|
||||
******************************************************************************/
|
||||
void BOARD_BootClockRUN(void)
|
||||
{
|
||||
/* Set the system clock dividers in SIM to safe value. */
|
||||
CLOCK_SetSimSafeDivs();
|
||||
/* Set MCG to HIRC mode. */
|
||||
CLOCK_SetMcgliteConfig(&mcgliteConfig_BOARD_BootClockRUN);
|
||||
/* Set the clock configuration in SIM module. */
|
||||
CLOCK_SetSimConfig(&simConfig_BOARD_BootClockRUN);
|
||||
/* Set SystemCoreClock variable. */
|
||||
SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
********************* Configuration BOARD_BootClockVLPR ***********************
|
||||
******************************************************************************/
|
||||
/* clang-format off */
|
||||
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
!!Configuration
|
||||
name: BOARD_BootClockVLPR
|
||||
outputs:
|
||||
- {id: Bus_clock.outFreq, value: 1 MHz}
|
||||
- {id: Core_clock.outFreq, value: 2 MHz}
|
||||
- {id: Flash_clock.outFreq, value: 1 MHz}
|
||||
- {id: LPO_clock.outFreq, value: 1 kHz}
|
||||
- {id: MCGIRCLK.outFreq, value: 2 MHz}
|
||||
- {id: System_clock.outFreq, value: 2 MHz}
|
||||
settings:
|
||||
- {id: MCGMode, value: LIRC2M}
|
||||
- {id: powerMode, value: VLPR}
|
||||
- {id: MCG_C2_OSC_MODE_CFG, value: ModeOscLowPower}
|
||||
- {id: RTCCLKOUTConfig, value: 'yes'}
|
||||
- {id: SIM.OUTDIV4.scale, value: '2', locked: true}
|
||||
- {id: SIM.RTCCLKOUTSEL.sel, value: OSC.OSCERCLK}
|
||||
sources:
|
||||
- {id: MCG.LIRC.outFreq, value: 2 MHz}
|
||||
- {id: OSC.OSC.outFreq, value: 32.768 kHz}
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
|
||||
/* clang-format on */
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables for BOARD_BootClockVLPR configuration
|
||||
******************************************************************************/
|
||||
const mcglite_config_t mcgliteConfig_BOARD_BootClockVLPR =
|
||||
{
|
||||
.outSrc = kMCGLITE_ClkSrcLirc, /* MCGOUTCLK source is LIRC */
|
||||
.irclkEnableMode = kMCGLITE_IrclkEnable, /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
|
||||
.ircs = kMCGLITE_Lirc2M, /* Slow internal reference (LIRC) 2 MHz clock selected */
|
||||
.fcrdiv = kMCGLITE_LircDivBy1, /* Low-frequency Internal Reference Clock Divider: divided by 1 */
|
||||
.lircDiv2 = kMCGLITE_LircDivBy1, /* Second Low-frequency Internal Reference Clock Divider: divided by 1 */
|
||||
.hircEnableInNotHircMode = false, /* HIRC source is not enabled */
|
||||
};
|
||||
const sim_clock_config_t simConfig_BOARD_BootClockVLPR =
|
||||
{
|
||||
.er32kSrc = SIM_OSC32KSEL_OSC32KCLK_CLK, /* OSC32KSEL select: OSC32KCLK clock */
|
||||
.clkdiv1 = 0x10000U, /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV4: /2 */
|
||||
};
|
||||
const osc_config_t oscConfig_BOARD_BootClockVLPR =
|
||||
{
|
||||
.freq = 0U, /* Oscillator frequency: 0Hz */
|
||||
.capLoad = (OSC_CAP0P), /* Oscillator capacity load: 0pF */
|
||||
.workMode = kOSC_ModeOscLowPower, /* Oscillator low power */
|
||||
.oscerConfig =
|
||||
{
|
||||
.enableMode = OSC_ER_CLK_DISABLE, /* Disable external reference clock */
|
||||
}
|
||||
};
|
||||
|
||||
/*******************************************************************************
|
||||
* Code for BOARD_BootClockVLPR configuration
|
||||
******************************************************************************/
|
||||
void BOARD_BootClockVLPR(void)
|
||||
{
|
||||
/* Set the system clock dividers in SIM to safe value. */
|
||||
CLOCK_SetSimSafeDivs();
|
||||
/* Set MCG to LIRC2M mode. */
|
||||
CLOCK_SetMcgliteConfig(&mcgliteConfig_BOARD_BootClockVLPR);
|
||||
/* Set the clock configuration in SIM module. */
|
||||
CLOCK_SetSimConfig(&simConfig_BOARD_BootClockVLPR);
|
||||
/* Set VLPR power mode. */
|
||||
SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
|
||||
#if (defined(FSL_FEATURE_SMC_HAS_LPWUI) && FSL_FEATURE_SMC_HAS_LPWUI)
|
||||
SMC_SetPowerModeVlpr(SMC, false);
|
||||
#else
|
||||
SMC_SetPowerModeVlpr(SMC);
|
||||
#endif
|
||||
while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr)
|
||||
{
|
||||
}
|
||||
/* Set SystemCoreClock variable. */
|
||||
SystemCoreClock = BOARD_BOOTCLOCKVLPR_CORE_CLOCK;
|
||||
}
|
||||
@@ -0,0 +1,110 @@
|
||||
/*
|
||||
* Copyright 2019 ,2021 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
|
||||
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
#ifndef _CLOCK_CONFIG_H_
|
||||
#define _CLOCK_CONFIG_H_
|
||||
|
||||
#include "fsl_common.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
************************ BOARD_InitBootClocks function ************************
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*!
|
||||
* @brief This function executes default configuration of clocks.
|
||||
*
|
||||
*/
|
||||
void BOARD_InitBootClocks(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*******************************************************************************
|
||||
********************** Configuration BOARD_BootClockRUN ***********************
|
||||
******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* Definitions for BOARD_BootClockRUN configuration
|
||||
******************************************************************************/
|
||||
#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 48000000U /*!< Core clock frequency: 48000000Hz */
|
||||
|
||||
/*! @brief MCG lite set for BOARD_BootClockRUN configuration.
|
||||
*/
|
||||
extern const mcglite_config_t mcgliteConfig_BOARD_BootClockRUN;
|
||||
/*! @brief SIM module set for BOARD_BootClockRUN configuration.
|
||||
*/
|
||||
extern const sim_clock_config_t simConfig_BOARD_BootClockRUN;
|
||||
/*! @brief OSC set for BOARD_BootClockRUN configuration.
|
||||
*/
|
||||
extern const osc_config_t oscConfig_BOARD_BootClockRUN;
|
||||
|
||||
/*******************************************************************************
|
||||
* API for BOARD_BootClockRUN configuration
|
||||
******************************************************************************/
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*!
|
||||
* @brief This function executes configuration of clocks.
|
||||
*
|
||||
*/
|
||||
void BOARD_BootClockRUN(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*******************************************************************************
|
||||
********************* Configuration BOARD_BootClockVLPR ***********************
|
||||
******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* Definitions for BOARD_BootClockVLPR configuration
|
||||
******************************************************************************/
|
||||
#define BOARD_BOOTCLOCKVLPR_CORE_CLOCK 2000000U /*!< Core clock frequency: 2000000Hz */
|
||||
|
||||
/*! @brief MCG lite set for BOARD_BootClockVLPR configuration.
|
||||
*/
|
||||
extern const mcglite_config_t mcgliteConfig_BOARD_BootClockVLPR;
|
||||
/*! @brief SIM module set for BOARD_BootClockVLPR configuration.
|
||||
*/
|
||||
extern const sim_clock_config_t simConfig_BOARD_BootClockVLPR;
|
||||
/*! @brief OSC set for BOARD_BootClockVLPR configuration.
|
||||
*/
|
||||
extern const osc_config_t oscConfig_BOARD_BootClockVLPR;
|
||||
|
||||
/*******************************************************************************
|
||||
* API for BOARD_BootClockVLPR configuration
|
||||
******************************************************************************/
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*!
|
||||
* @brief This function executes configuration of clocks.
|
||||
*
|
||||
*/
|
||||
void BOARD_BootClockVLPR(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
#endif /* _CLOCK_CONFIG_H_ */
|
||||
@@ -0,0 +1,15 @@
|
||||
set(MCU_VARIANT K32L2B31A)
|
||||
|
||||
set(JLINK_DEVICE K32L2B31xxxxA)
|
||||
set(PYOCD_TARGET K32L2B)
|
||||
|
||||
set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/kuiic.ld)
|
||||
|
||||
function(update_board TARGET)
|
||||
target_sources(${TARGET} PUBLIC
|
||||
${CMAKE_CURRENT_FUNCTION_LIST_DIR}/clock_config.c
|
||||
)
|
||||
target_compile_definitions(${TARGET} PUBLIC
|
||||
CPU_K32L2B31VLH0A
|
||||
)
|
||||
endfunction()
|
||||
@@ -0,0 +1,69 @@
|
||||
/*
|
||||
* The MIT License (MIT)
|
||||
*
|
||||
* Copyright (c) 2019, Ha Thach (tinyusb.org)
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
* THE SOFTWARE.
|
||||
*
|
||||
* This file is part of the TinyUSB stack.
|
||||
*/
|
||||
|
||||
/* metadata:
|
||||
name: Kuiic
|
||||
url: https://github.com/nxf58843/kuiic
|
||||
*/
|
||||
|
||||
#ifndef BOARD_H_
|
||||
#define BOARD_H_
|
||||
|
||||
#include "fsl_device_registers.h"
|
||||
|
||||
#define USB_CLOCK_SOURCE kCLOCK_UsbSrcIrc48M
|
||||
|
||||
// LED
|
||||
#define LED_PIN_CLOCK kCLOCK_PortA
|
||||
#define LED_GPIO GPIOA
|
||||
#define LED_PORT PORTA
|
||||
#define LED_PIN 2
|
||||
#define LED_STATE_ON 1
|
||||
|
||||
// UART
|
||||
#define UART_PORT LPUART1
|
||||
#define UART_PIN_RX 3u
|
||||
#define UART_PIN_TX 0u
|
||||
|
||||
#define UART_CLOCK_SOURCE_HZ CLOCK_GetFreq(kCLOCK_McgIrc48MClk)
|
||||
|
||||
static inline void BOARD_InitBootPins(void) {
|
||||
/* PORTC3 is configured as LPUART0_RX */
|
||||
PORT_SetPinMux(PORTC, 3U, kPORT_MuxAlt3);
|
||||
/* PORTA2 (pin 24) is configured as LPUART0_TX */
|
||||
PORT_SetPinMux(PORTE, 0U, kPORT_MuxAlt3);
|
||||
|
||||
SIM->SOPT5 = ((SIM->SOPT5 &
|
||||
/* Mask bits to zero which are setting */
|
||||
(~(SIM_SOPT5_LPUART1TXSRC_MASK | SIM_SOPT5_LPUART1RXSRC_MASK)))
|
||||
/* LPUART0 Transmit Data Source Select: LPUART0_TX pin. */
|
||||
| SIM_SOPT5_LPUART1TXSRC(SOPT5_LPUART1TXSRC_LPUART_TX)
|
||||
/* LPUART0 Receive Data Source Select: LPUART_RX pin. */
|
||||
| SIM_SOPT5_LPUART1RXSRC(SOPT5_LPUART1RXSRC_LPUART_RX));
|
||||
CLOCK_SetLpuart1Clock(1);
|
||||
}
|
||||
|
||||
#endif /* BOARD_H_ */
|
||||
@@ -0,0 +1,18 @@
|
||||
MCU = K32L2B31A
|
||||
|
||||
CFLAGS += -DCPU_K32L2B31VLH0A
|
||||
|
||||
# mcu driver cause following warnings
|
||||
CFLAGS += -Wno-error=unused-parameter -Wno-error=redundant-decls
|
||||
|
||||
# All source paths should be relative to the top level.
|
||||
LD_FILE = $(BOARD_PATH)/kuiic.ld
|
||||
|
||||
# For flash-jlink target
|
||||
JLINK_DEVICE = K32L2B31xxxxA
|
||||
|
||||
# For flash-pyocd target
|
||||
PYOCD_TARGET = K32L2B
|
||||
|
||||
# flash using pyocd
|
||||
flash: flash-pyocd
|
||||
@@ -0,0 +1,39 @@
|
||||
#include "clock_config.h"
|
||||
#include "fsl_clock.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables
|
||||
******************************************************************************/
|
||||
/* System clock frequency. */
|
||||
// extern uint32_t SystemCoreClock;
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables for BOARD_BootClockRUN configuration
|
||||
******************************************************************************/
|
||||
const mcglite_config_t mcgliteConfig_BOARD_BootClockRUN = {
|
||||
.outSrc = kMCGLITE_ClkSrcHirc, /* MCGOUTCLK source is HIRC */
|
||||
.irclkEnableMode = kMCGLITE_IrclkEnable, /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
|
||||
.ircs = kMCGLITE_Lirc8M, /* Slow internal reference (LIRC) 8 MHz clock selected */
|
||||
.fcrdiv = kMCGLITE_LircDivBy1, /* Low-frequency Internal Reference Clock Divider: divided by 1 */
|
||||
.lircDiv2 = kMCGLITE_LircDivBy1, /* Second Low-frequency Internal Reference Clock Divider: divided by 1 */
|
||||
.hircEnableInNotHircMode = true, /* HIRC source is enabled */
|
||||
};
|
||||
const sim_clock_config_t simConfig_BOARD_BootClockRUN = {
|
||||
.er32kSrc = SIM_OSC32KSEL_LPO_CLK, /* OSC32KSEL select: LPO clock */
|
||||
.clkdiv1 = 0x10000U, /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV4: /2 */
|
||||
};
|
||||
|
||||
/*******************************************************************************
|
||||
* Code for BOARD_BootClockRUN configuration
|
||||
******************************************************************************/
|
||||
void BOARD_BootClockRUN(void)
|
||||
{
|
||||
/* Set the system clock dividers in SIM to safe value. */
|
||||
CLOCK_SetSimSafeDivs();
|
||||
/* Set MCG to HIRC mode. */
|
||||
CLOCK_SetMcgliteConfig(&mcgliteConfig_BOARD_BootClockRUN);
|
||||
/* Set the clock configuration in SIM module. */
|
||||
CLOCK_SetSimConfig(&simConfig_BOARD_BootClockRUN);
|
||||
/* Set SystemCoreClock variable. */
|
||||
SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
|
||||
}
|
||||
@@ -0,0 +1,14 @@
|
||||
#ifndef CLOCK_CONFIG_H
|
||||
#define CLOCK_CONFIG_H
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
#define SIM_OSC32KSEL_LPO_CLK 3U /*!< OSC32KSEL select: LPO clock */
|
||||
#define SOPT5_LPUART1RXSRC_LPUART_RX 0x00u /*!<@brief LPUART1 Receive Data Source Select: LPUART_RX pin */
|
||||
#define SOPT5_LPUART1TXSRC_LPUART_TX 0x00u /*!<@brief LPUART1 Transmit Data Source Select: LPUART_TX pin */
|
||||
#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 48000000U /*!< Core clock frequency: 48000000Hz */
|
||||
|
||||
void BOARD_BootClockRUN(void);
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,216 @@
|
||||
/*
|
||||
** ###################################################################
|
||||
** Processors: K32L2B31VFM0A
|
||||
** K32L2B31VFT0A
|
||||
** K32L2B31VLH0A
|
||||
** K32L2B31VMP0A
|
||||
**
|
||||
** Compiler: GNU C Compiler
|
||||
** Reference manual: K32L2B3xRM, Rev.0, July 2019
|
||||
** Version: rev. 1.0, 2019-07-30
|
||||
** Build: b190930
|
||||
**
|
||||
** Abstract:
|
||||
** Linker file for the GNU C Compiler
|
||||
**
|
||||
** Copyright 2016 Freescale Semiconductor, Inc.
|
||||
** Copyright 2016-2019 NXP
|
||||
** All rights reserved.
|
||||
**
|
||||
** SPDX-License-Identifier: BSD-3-Clause
|
||||
**
|
||||
** http: www.nxp.com
|
||||
** mail: support@nxp.com
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
|
||||
/* Entry Point */
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
|
||||
STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
|
||||
|
||||
/* Specify the memory areas */
|
||||
MEMORY
|
||||
{
|
||||
m_interrupts (RX) : ORIGIN = 0x00008000, LENGTH = 0x00000200
|
||||
m_flash_config (RX) : ORIGIN = 0x00008400, LENGTH = 0x00000010
|
||||
m_text (RX) : ORIGIN = 0x00008410, LENGTH = 0x00037BF0
|
||||
m_data (RW) : ORIGIN = 0x1FFFE000, LENGTH = 0x00008000
|
||||
}
|
||||
|
||||
/* Define output sections */
|
||||
SECTIONS
|
||||
{
|
||||
/* The startup code goes first into internal flash */
|
||||
.interrupts :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.isr_vector)) /* Startup code */
|
||||
. = ALIGN(4);
|
||||
} > m_interrupts
|
||||
|
||||
.flash_config :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.FlashConfig)) /* Flash Configuration Field (FCF) */
|
||||
. = ALIGN(4);
|
||||
} > m_flash_config
|
||||
|
||||
/* The program code and other data goes into internal flash */
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.text) /* .text sections (code) */
|
||||
*(.text*) /* .text* sections (code) */
|
||||
*(.rodata) /* .rodata sections (constants, strings, etc.) */
|
||||
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
|
||||
*(.glue_7) /* glue arm to thumb code */
|
||||
*(.glue_7t) /* glue thumb to arm code */
|
||||
*(.eh_frame)
|
||||
KEEP (*(.init))
|
||||
KEEP (*(.fini))
|
||||
. = ALIGN(4);
|
||||
} > m_text
|
||||
|
||||
.ARM.extab :
|
||||
{
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
} > m_text
|
||||
|
||||
.ARM :
|
||||
{
|
||||
__exidx_start = .;
|
||||
*(.ARM.exidx*)
|
||||
__exidx_end = .;
|
||||
} > m_text
|
||||
|
||||
.ctors :
|
||||
{
|
||||
__CTOR_LIST__ = .;
|
||||
/* gcc uses crtbegin.o to find the start of
|
||||
the constructors, so we make sure it is
|
||||
first. Because this is a wildcard, it
|
||||
doesn't matter if the user does not
|
||||
actually link against crtbegin.o; the
|
||||
linker won't look for a file to match a
|
||||
wildcard. The wildcard also means that it
|
||||
doesn't matter which directory crtbegin.o
|
||||
is in. */
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*crtbegin?.o(.ctors))
|
||||
/* We don't want to include the .ctor section from
|
||||
from the crtend.o file until after the sorted ctors.
|
||||
The .ctor section from the crtend file contains the
|
||||
end of ctors marker and it must be last */
|
||||
KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*(.ctors))
|
||||
__CTOR_END__ = .;
|
||||
} > m_text
|
||||
|
||||
.dtors :
|
||||
{
|
||||
__DTOR_LIST__ = .;
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*crtbegin?.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*(.dtors))
|
||||
__DTOR_END__ = .;
|
||||
} > m_text
|
||||
|
||||
.preinit_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array*))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
} > m_text
|
||||
|
||||
.init_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array*))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
} > m_text
|
||||
|
||||
.fini_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
KEEP (*(.fini_array*))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
} > m_text
|
||||
|
||||
__etext = .; /* define a global symbol at end of code */
|
||||
__DATA_ROM = .; /* Symbol is used by startup for data initialization */
|
||||
|
||||
/* reserve MTB memory at the beginning of m_data */
|
||||
.mtb : /* MTB buffer address as defined by the hardware */
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_mtb_start = .;
|
||||
KEEP(*(.mtb_buf)) /* need to KEEP Micro Trace Buffer as not referenced by application */
|
||||
. = ALIGN(8);
|
||||
_mtb_end = .;
|
||||
} > m_data
|
||||
|
||||
.data : AT(__DATA_ROM)
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__DATA_RAM = .;
|
||||
__data_start__ = .; /* create a global symbol at data start */
|
||||
*(.data) /* .data sections */
|
||||
*(.data*) /* .data* sections */
|
||||
KEEP(*(.jcr*))
|
||||
. = ALIGN(4);
|
||||
__data_end__ = .; /* define a global symbol at data end */
|
||||
} > m_data
|
||||
|
||||
__DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
|
||||
text_end = ORIGIN(m_text) + LENGTH(m_text);
|
||||
ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
|
||||
|
||||
/* Uninitialized data section */
|
||||
.bss :
|
||||
{
|
||||
/* This is used by the startup in order to initialize the .bss section */
|
||||
. = ALIGN(4);
|
||||
__START_BSS = .;
|
||||
__bss_start__ = .;
|
||||
*(.bss)
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
__bss_end__ = .;
|
||||
__END_BSS = .;
|
||||
} > m_data
|
||||
|
||||
.heap :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
__end__ = .;
|
||||
PROVIDE(end = .);
|
||||
__HeapBase = .;
|
||||
. += HEAP_SIZE;
|
||||
__HeapLimit = .;
|
||||
__heap_limit = .; /* Add for _sbrk */
|
||||
} > m_data
|
||||
|
||||
.stack :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
. += STACK_SIZE;
|
||||
} > m_data
|
||||
|
||||
/* Initializes stack on the end of block */
|
||||
__StackTop = ORIGIN(m_data) + LENGTH(m_data);
|
||||
__StackLimit = __StackTop - STACK_SIZE;
|
||||
PROVIDE(__stack = __StackTop);
|
||||
|
||||
.ARM.attributes 0 : { *(.ARM.attributes) }
|
||||
|
||||
ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
|
||||
}
|
||||
Reference in New Issue
Block a user