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Initial project setup

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This commit is contained in:
Taras Syvash
2025-12-13 11:59:11 +02:00
commit 3218e6039f
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149
managed_components/espressif__tinyusb/hw/bsp/imxrt/FreeRTOSConfig/FreeRTOSConfig.h Normal file
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/*
* FreeRTOS Kernel V10.0.0
* Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software. If you wish to use our Amazon
* FreeRTOS name, please do so in a fair use way that does not cause confusion.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* http://www.FreeRTOS.org
* http://aws.amazon.com/freertos
*
* 1 tab == 4 spaces!
*/
#ifndef FREERTOS_CONFIG_H
#define FREERTOS_CONFIG_H
/*-----------------------------------------------------------
* Application specific definitions.
*
* These definitions should be adjusted for your particular hardware and
* application requirements.
*
* THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
* FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
*
* See http://www.freertos.org/a00110.html.
*----------------------------------------------------------*/
// skip if included from IAR assembler
#ifndef __IASMARM__
#include "fsl_device_registers.h"
#endif
/* Cortex M23/M33 port configuration. */
#define configENABLE_MPU 0
#define configENABLE_FPU 1
#define configENABLE_TRUSTZONE 0
#define configMINIMAL_SECURE_STACK_SIZE (1024)
#define configUSE_PREEMPTION 1
#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
#define configCPU_CLOCK_HZ SystemCoreClock
#define configTICK_RATE_HZ ( 1000 )
#define configMAX_PRIORITIES ( 5 )
#define configMINIMAL_STACK_SIZE ( 128 )
#define configTOTAL_HEAP_SIZE ( configSUPPORT_DYNAMIC_ALLOCATION*8*1024 )
#define configMAX_TASK_NAME_LEN 16
#define configUSE_16_BIT_TICKS 0
#define configIDLE_SHOULD_YIELD 1
#define configUSE_MUTEXES 1
#define configUSE_RECURSIVE_MUTEXES 1
#define configUSE_COUNTING_SEMAPHORES 1
#define configQUEUE_REGISTRY_SIZE 4
#define configUSE_QUEUE_SETS 0
#define configUSE_TIME_SLICING 0
#define configUSE_NEWLIB_REENTRANT 0
#define configENABLE_BACKWARD_COMPATIBILITY 1
#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0
#define configSUPPORT_STATIC_ALLOCATION 1
#define configSUPPORT_DYNAMIC_ALLOCATION 0
/* Hook function related definitions. */
#define configUSE_IDLE_HOOK 0
#define configUSE_TICK_HOOK 0
#define configUSE_MALLOC_FAILED_HOOK 0 // cause nested extern warning
#define configCHECK_FOR_STACK_OVERFLOW 2
#define configCHECK_HANDLER_INSTALLATION 0
/* Run time and task stats gathering related definitions. */
#define configGENERATE_RUN_TIME_STATS 0
#define configRECORD_STACK_HIGH_ADDRESS 1
#define configUSE_TRACE_FACILITY 1 // legacy trace
#define configUSE_STATS_FORMATTING_FUNCTIONS 0
/* Co-routine definitions. */
#define configUSE_CO_ROUTINES 0
#define configMAX_CO_ROUTINE_PRIORITIES 2
/* Software timer related definitions. */
#define configUSE_TIMERS 1
#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES-2)
#define configTIMER_QUEUE_LENGTH 32
#define configTIMER_TASK_STACK_DEPTH configMINIMAL_STACK_SIZE
/* Optional functions - most linkers will remove unused functions anyway. */
#define INCLUDE_vTaskPrioritySet 0
#define INCLUDE_uxTaskPriorityGet 0
#define INCLUDE_vTaskDelete 0
#define INCLUDE_vTaskSuspend 1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
#define INCLUDE_xResumeFromISR 0
#define INCLUDE_vTaskDelayUntil 1
#define INCLUDE_vTaskDelay 1
#define INCLUDE_xTaskGetSchedulerState 0
#define INCLUDE_xTaskGetCurrentTaskHandle 1
#define INCLUDE_uxTaskGetStackHighWaterMark 0
#define INCLUDE_xTaskGetIdleTaskHandle 0
#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
#define INCLUDE_pcTaskGetTaskName 0
#define INCLUDE_eTaskGetState 0
#define INCLUDE_xEventGroupSetBitFromISR 0
#define INCLUDE_xTimerPendFunctionCall 0
/* FreeRTOS hooks to NVIC vectors */
#define xPortPendSVHandler PendSV_Handler
#define xPortSysTickHandler SysTick_Handler
#define vPortSVCHandler SVC_Handler
//--------------------------------------------------------------------+
// Interrupt nesting behavior configuration.
//--------------------------------------------------------------------+
// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
#define configPRIO_BITS 4
/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1<<configPRIO_BITS) - 1)
/* The highest interrupt priority that can be used by any interrupt service
routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL
INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
PRIORITY THAN THIS! (higher priorities are lower numeric values. */
#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 2
/* Interrupt priorities used by the kernel port layer itself. These are generic
to all Cortex-M ports, and do not rely on any particular library functions. */
#define configKERNEL_INTERRUPT_PRIORITY ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
#endif /* __FREERTOS_CONFIG__H */

15
managed_components/espressif__tinyusb/hw/bsp/imxrt/boards/metro_m7_1011/board.cmake Normal file
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set(MCU_VARIANT MIMXRT1011)
set(JLINK_DEVICE MIMXRT1011xxx5A)
set(PYOCD_TARGET mimxrt1010)
set(NXPLINK_DEVICE MIMXRT1011xxxxx:EVK-MIMXRT1010)
function(update_board TARGET)
target_sources(${TARGET} PUBLIC
${CMAKE_CURRENT_FUNCTION_LIST_DIR}/evkmimxrt1010_flexspi_nor_config.c
)
target_compile_definitions(${TARGET} PUBLIC
CPU_MIMXRT1011DAE5A
CFG_EXAMPLE_VIDEO_READONLY
)
endfunction()

55
managed_components/espressif__tinyusb/hw/bsp/imxrt/boards/metro_m7_1011/board.h Normal file
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/*
* The MIT License (MIT)
*
* Copyright (c) 2019, Ha Thach (tinyusb.org)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* This file is part of the TinyUSB stack.
*/
/* metadata:
name: Adafruit Metro M7 1011
url: https://www.adafruit.com/product/5600
*/
#ifndef BOARD_M7_1011_H_
#define BOARD_M7_1011_H_
// required since iMXRT MCUX-SDK include this file for board size
#define BOARD_FLASH_SIZE (8*1024*1024)
// LED: IOMUXC_GPIO_03_GPIOMUX_IO03
#define LED_PORT BOARD_INITPINS_USER_LED_PERIPHERAL
#define LED_PIN BOARD_INITPINS_USER_LED_CHANNEL
#define LED_STATE_ON 1
// D8 as button: GPIO8
#define BUTTON_PORT BOARD_INITPINS_USER_BUTTON_PERIPHERAL
#define BUTTON_PIN BOARD_INITPINS_USER_BUTTON_CHANNEL
#define BUTTON_STATE_ACTIVE 0
// UART: IOMUXC_GPIO_09_LPUART1_RXD, IOMUXC_GPIO_10_LPUART1_TXD
#define UART_PORT LPUART1
#define UART_CLK_ROOT BOARD_BOOTCLOCKRUN_UART_CLK_ROOT
static inline void BOARD_ConfigMPU(void) {
}
#endif

17
managed_components/espressif__tinyusb/hw/bsp/imxrt/boards/metro_m7_1011/board.mk Normal file
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CFLAGS += -DCPU_MIMXRT1011DAE5A -DCFG_EXAMPLE_VIDEO_READONLY
MCU_VARIANT = MIMXRT1011
# LD file with uf2
LD_FILE = $(BOARD_PATH)/$(BOARD).ld
# For flash-jlink target
JLINK_DEVICE = MIMXRT1011xxx5A
# For flash-pyocd target
PYOCD_TARGET = mimxrt1010
# flash using pyocd
flash: flash-uf2
flash-uf2: $(BUILD)/$(PROJECT).uf2
@echo copying $<
@$(CP) $< /media/$(USER)/METROM7BOOT

340
managed_components/espressif__tinyusb/hw/bsp/imxrt/boards/metro_m7_1011/board/clock_config.c Normal file
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/*
* How to setup clock using clock driver functions:
*
* 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock.
*
* 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock.
*
* 3. Call CLOCK_SetMux() to configure corresponding clock source for target clock out.
*
* 4. Call CLOCK_SetDiv() to configure corresponding clock divider for target clock out.
*
* 5. Call CLOCK_SetXtalFreq() to set XTAL frequency based on board settings.
*
*/
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!GlobalInfo
product: Clocks v12.0
processor: MIMXRT1011xxxxx
package_id: MIMXRT1011DAE5A
mcu_data: ksdk2_0
processor_version: 14.0.0
board: MIMXRT1010-EVK
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
#include "clock_config.h"
#include "fsl_iomuxc.h"
/*******************************************************************************
* Definitions
******************************************************************************/
/*******************************************************************************
* Variables
******************************************************************************/
/*******************************************************************************
************************ BOARD_InitBootClocks function ************************
******************************************************************************/
void BOARD_InitBootClocks(void)
{
BOARD_BootClockRUN();
}
/*******************************************************************************
********************** Configuration BOARD_BootClockRUN ***********************
******************************************************************************/
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!Configuration
name: BOARD_BootClockRUN
called_from_default_init: true
outputs:
- {id: ADC_ALT_CLK.outFreq, value: 40 MHz}
- {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz}
- {id: CLK_1M.outFreq, value: 1 MHz}
- {id: CLK_24M.outFreq, value: 24 MHz}
- {id: CORE_CLK_ROOT.outFreq, value: 500 MHz}
- {id: ENET_500M_REF_CLK.outFreq, value: 500 MHz}
- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz}
- {id: FLEXSPI_CLK_ROOT.outFreq, value: 132 MHz}
- {id: GPT1_ipg_clk_highfreq.outFreq, value: 62.5 MHz}
- {id: GPT2_ipg_clk_highfreq.outFreq, value: 62.5 MHz}
- {id: IPG_CLK_ROOT.outFreq, value: 125 MHz}
- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz}
- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz}
- {id: MQS_MCLK.outFreq, value: 1080/17 MHz}
- {id: PERCLK_CLK_ROOT.outFreq, value: 62.5 MHz}
- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz}
- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz}
- {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz}
- {id: SAI1_MCLK3.outFreq, value: 30 MHz}
- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz}
- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz}
- {id: SAI3_MCLK3.outFreq, value: 30 MHz}
- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz}
- {id: TRACE_CLK_ROOT.outFreq, value: 132 MHz}
- {id: UART_CLK_ROOT.outFreq, value: 80 MHz}
- {id: USBPHY_CLK.outFreq, value: 480 MHz}
settings:
- {id: CCM.ADC_ACLK_PODF.scale, value: '12', locked: true}
- {id: CCM.AHB_PODF.scale, value: '1', locked: true}
- {id: CCM.FLEXSPI_PODF.scale, value: '4', locked: true}
- {id: CCM.IPG_PODF.scale, value: '4'}
- {id: CCM.LPSPI_PODF.scale, value: '5'}
- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true}
- {id: CCM.PRE_PERIPH_CLK_SEL.sel, value: CCM_ANALOG.ENET_500M_REF_CLK}
- {id: CCM.SAI1_CLK_SEL.sel, value: CCM_ANALOG.PLL3_PFD2_CLK}
- {id: CCM.SAI3_CLK_SEL.sel, value: CCM_ANALOG.PLL3_PFD2_CLK}
- {id: CCM.TRACE_CLK_SEL.sel, value: CCM_ANALOG.PLL2_MAIN_CLK}
- {id: CCM_ANALOG.PLL2.denom, value: '1'}
- {id: CCM_ANALOG.PLL2.num, value: '0'}
- {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK}
- {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0}
- {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1}
- {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2}
- {id: CCM_ANALOG.PLL2_PFD2_DIV.scale, value: '18', locked: true}
- {id: CCM_ANALOG.PLL2_PFD2_MUL.scale, value: '18', locked: true}
- {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3}
- {id: CCM_ANALOG.PLL2_PFD3_DIV.scale, value: '18', locked: true}
- {id: CCM_ANALOG.PLL2_PFD3_MUL.scale, value: '18', locked: true}
- {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3}
- {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0}
- {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '22', locked: true}
- {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true}
- {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1}
- {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2}
- {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3}
- {id: CCM_ANALOG.PLL3_PFD3_DIV.scale, value: '18', locked: true}
- {id: CCM_ANALOG.PLL3_PFD3_MUL.scale, value: '18', locked: true}
- {id: CCM_ANALOG.PLL6_BYPASS.sel, value: CCM_ANALOG.PLL6}
- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_CFG, value: Enabled}
- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_OUT_CFG, value: Enabled}
- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'}
sources:
- {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/*******************************************************************************
* Variables for BOARD_BootClockRUN configuration
******************************************************************************/
const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN =
{
.loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */
.numerator = 0, /* 30 bit numerator of fractional loop divider */
.denominator = 1, /* 30 bit denominator of fractional loop divider */
.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
};
const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN =
{
.loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */
.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
};
const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN =
{
.enableClkOutput500M = true, /* Enable the PLL providing the ENET 500MHz reference clock */
.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
};
/*******************************************************************************
* Code for BOARD_BootClockRUN configuration
******************************************************************************/
void BOARD_BootClockRUN(void)
{
/* Init RTC OSC clock frequency. */
CLOCK_SetRtcXtalFreq(32768U);
/* Enable 1MHz clock output. */
XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK;
/* Use free 1MHz clock output. */
XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK;
/* Set XTAL 24MHz clock frequency. */
CLOCK_SetXtalFreq(24000000U);
/* Enable XTAL 24MHz clock source. */
CLOCK_InitExternalClk(0);
/* Enable internal RC. */
CLOCK_InitRcOsc24M();
/* Switch clock source to external OSC. */
CLOCK_SwitchOsc(kCLOCK_XtalOsc);
/* Set Oscillator ready counter value. */
CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127);
/* Setting the VDD_SOC to 1.25V. It is necessary to config CORE to 500Mhz. */
DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x12);
/* Waiting for DCDC_STS_DC_OK bit is asserted */
while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0))
{
}
/* Disable IPG clock gate. */
CLOCK_DisableClock(kCLOCK_Adc1);
CLOCK_DisableClock(kCLOCK_Xbar1);
/* Set IPG_PODF. */
CLOCK_SetDiv(kCLOCK_IpgDiv, 3);
/* Init Enet PLL. */
CLOCK_InitEnetPll(&enetPllConfig_BOARD_BootClockRUN);
/* Disable PERCLK clock gate. */
CLOCK_DisableClock(kCLOCK_Gpt1);
CLOCK_DisableClock(kCLOCK_Gpt1S);
CLOCK_DisableClock(kCLOCK_Gpt2);
CLOCK_DisableClock(kCLOCK_Gpt2S);
CLOCK_DisableClock(kCLOCK_Pit);
/* Set PERCLK_PODF. */
CLOCK_SetDiv(kCLOCK_PerclkDiv, 1);
/* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
* With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
* Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
/* Disable Flexspi clock gate. */
CLOCK_DisableClock(kCLOCK_FlexSpi);
/* Set FLEXSPI_PODF. */
CLOCK_SetDiv(kCLOCK_FlexspiDiv, 3);
/* Set Flexspi clock source. */
CLOCK_SetMux(kCLOCK_FlexspiMux, 0);
CLOCK_SetMux(kCLOCK_FlexspiSrcMux, 0);
#endif
/* Disable ADC_ACLK_EN clock gate. */
CCM->CSCMR2 &= ~CCM_CSCMR2_ADC_ACLK_EN_MASK;
/* Set ADC_ACLK_PODF. */
CLOCK_SetDiv(kCLOCK_AdcDiv, 11);
/* Disable LPSPI clock gate. */
CLOCK_DisableClock(kCLOCK_Lpspi1);
CLOCK_DisableClock(kCLOCK_Lpspi2);
/* Set LPSPI_PODF. */
CLOCK_SetDiv(kCLOCK_LpspiDiv, 4);
/* Set Lpspi clock source. */
CLOCK_SetMux(kCLOCK_LpspiMux, 2);
/* Disable TRACE clock gate. */
CLOCK_DisableClock(kCLOCK_Trace);
/* Set TRACE_PODF. */
CLOCK_SetDiv(kCLOCK_TraceDiv, 3);
/* Set Trace clock source. */
CLOCK_SetMux(kCLOCK_TraceMux, 0);
/* Disable SAI1 clock gate. */
CLOCK_DisableClock(kCLOCK_Sai1);
/* Set SAI1_CLK_PRED. */
CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3);
/* Set SAI1_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_Sai1Div, 1);
/* Set Sai1 clock source. */
CLOCK_SetMux(kCLOCK_Sai1Mux, 0);
/* Disable SAI3 clock gate. */
CLOCK_DisableClock(kCLOCK_Sai3);
/* Set SAI3_CLK_PRED. */
CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3);
/* Set SAI3_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_Sai3Div, 1);
/* Set Sai3 clock source. */
CLOCK_SetMux(kCLOCK_Sai3Mux, 0);
/* Disable Lpi2c clock gate. */
CLOCK_DisableClock(kCLOCK_Lpi2c1);
CLOCK_DisableClock(kCLOCK_Lpi2c2);
/* Set LPI2C_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0);
/* Set Lpi2c clock source. */
CLOCK_SetMux(kCLOCK_Lpi2cMux, 0);
/* Disable UART clock gate. */
CLOCK_DisableClock(kCLOCK_Lpuart1);
CLOCK_DisableClock(kCLOCK_Lpuart2);
CLOCK_DisableClock(kCLOCK_Lpuart3);
CLOCK_DisableClock(kCLOCK_Lpuart4);
/* Set UART_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_UartDiv, 0);
/* Set Uart clock source. */
CLOCK_SetMux(kCLOCK_UartMux, 0);
/* Disable SPDIF clock gate. */
CLOCK_DisableClock(kCLOCK_Spdif);
/* Set SPDIF0_CLK_PRED. */
CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1);
/* Set SPDIF0_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_Spdif0Div, 7);
/* Set Spdif clock source. */
CLOCK_SetMux(kCLOCK_SpdifMux, 3);
/* Disable Flexio1 clock gate. */
CLOCK_DisableClock(kCLOCK_Flexio1);
/* Set FLEXIO1_CLK_PRED. */
CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1);
/* Set FLEXIO1_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_Flexio1Div, 7);
/* Set Flexio1 clock source. */
CLOCK_SetMux(kCLOCK_Flexio1Mux, 3);
/* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
* With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
* Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
/* Init Usb1 PLL. */
CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN);
/* Init Usb1 pfd0. */
CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 22);
/* Init Usb1 pfd1. */
CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16);
/* Init Usb1 pfd2. */
CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17);
/* Init Usb1 pfd3. */
CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 18);
#endif
/* Set periph clock source to use the USB1 PLL output (PLL3_SW_CLK) temporarily. */
/* Set Pll3 SW clock source to use the USB1 PLL output. */
CLOCK_SetMux(kCLOCK_Pll3SwMux, 0);
/* Set safe value of the AHB_PODF. */
CLOCK_SetDiv(kCLOCK_AhbDiv, 1);
/* Set periph clock2 clock source to use the PLL3_SW_CLK. */
CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
/* Set peripheral clock source (glitchless mux) to select the temporary core clock. */
CLOCK_SetMux(kCLOCK_PeriphMux, 1);
/* Set per clock source. */
CLOCK_SetMux(kCLOCK_PerclkMux, 0);
/* Init System PLL. */
CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN);
/* Init System pfd0. */
CLOCK_InitSysPfd(kCLOCK_Pfd0, 27);
/* Init System pfd1. */
CLOCK_InitSysPfd(kCLOCK_Pfd1, 16);
/* Init System pfd2. */
CLOCK_InitSysPfd(kCLOCK_Pfd2, 18);
/* Init System pfd3. */
CLOCK_InitSysPfd(kCLOCK_Pfd3, 18);
/* DeInit Audio PLL. */
CLOCK_DeinitAudioPll();
/* Bypass Audio PLL. */
CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1);
/* Set divider for Audio PLL. */
CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK;
CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK;
/* Enable Audio PLL output. */
CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK;
/* Set preperiph clock source. */
CLOCK_SetMux(kCLOCK_PrePeriphMux, 3);
/* Set periph clock source. */
CLOCK_SetMux(kCLOCK_PeriphMux, 0);
/* Set periph clock2 clock source. */
CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
/* Set AHB_PODF. */
CLOCK_SetDiv(kCLOCK_AhbDiv, 0);
/* Set clock out1 divider. */
CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0);
/* Set clock out1 source. */
CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1);
/* Set clock out2 divider. */
CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0);
/* Set clock out2 source. */
CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(18);
/* Set clock out1 drives clock out1. */
CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK;
/* Disable clock out1. */
CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK;
/* Disable clock out2. */
CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK;
/* Set SAI1 MCLK1 clock source. */
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0);
/* Set SAI1 MCLK2 clock source. */
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0);
/* Set SAI1 MCLK3 clock source. */
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0);
/* Set SAI3 MCLK3 clock source. */
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
/* Set MQS configuration. */
IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0);
/* Set GPT1 High frequency reference clock source. */
IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK;
/* Set GPT2 High frequency reference clock source. */
IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK;
/* Set SystemCoreClock variable. */
SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
}

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#ifndef _CLOCK_CONFIG_H_
#define _CLOCK_CONFIG_H_
#include "fsl_common.h"
/*******************************************************************************
* Definitions
******************************************************************************/
#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */
#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */
/*******************************************************************************
************************ BOARD_InitBootClocks function ************************
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/
/*!
* @brief This function executes default configuration of clocks.
*
*/
void BOARD_InitBootClocks(void);
#if defined(__cplusplus)
}
#endif /* __cplusplus*/
/*******************************************************************************
********************** Configuration BOARD_BootClockRUN ***********************
******************************************************************************/
/*******************************************************************************
* Definitions for BOARD_BootClockRUN configuration
******************************************************************************/
#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 500000000U /*!< Core clock frequency: 500000000Hz */
/* Clock outputs (values are in Hz): */
#define BOARD_BOOTCLOCKRUN_ADC_ALT_CLK 40000000UL /* Clock consumers of ADC_ALT_CLK output : N/A */
#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL /* Clock consumers of CKIL_SYNC_CLK_ROOT output : CSU, EWM, GPT1, GPT2, KPP, PIT, RTWDOG, SNVS, SPDIF, TEMPMON, USB, WDOG1, WDOG2 */
#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL /* Clock consumers of CLKO1_CLK output : N/A */
#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL /* Clock consumers of CLKO2_CLK output : N/A */
#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL /* Clock consumers of CLK_1M output : EWM, RTWDOG */
#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL /* Clock consumers of CLK_24M output : GPT1, GPT2 */
#define BOARD_BOOTCLOCKRUN_CORE_CLK_ROOT 500000000UL /* Clock consumers of CORE_CLK_ROOT output : ARM, FLEXSPI */
#define BOARD_BOOTCLOCKRUN_ENET_500M_REF_CLK 500000000UL /* Clock consumers of ENET_500M_REF_CLK output : N/A */
#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL /* Clock consumers of FLEXIO1_CLK_ROOT output : FLEXIO1 */
#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 132000000UL /* Clock consumers of FLEXSPI_CLK_ROOT output : FLEXSPI */
#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 62500000UL /* Clock consumers of GPT1_ipg_clk_highfreq output : GPT1 */
#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 62500000UL /* Clock consumers of GPT2_ipg_clk_highfreq output : GPT2 */
#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 125000000UL /* Clock consumers of IPG_CLK_ROOT output : ADC1, ADC_ETC, AIPSTZ1, AIPSTZ2, AOI, ARM, CCM, CSU, DCDC, DCP, DMA0, DMAMUX, EWM, FLEXIO1, FLEXRAM, FLEXSPI, GPC, GPIO1, GPIO2, GPIO5, IOMUXC, KPP, LPI2C1, LPI2C2, LPSPI1, LPSPI2, LPUART1, LPUART2, LPUART3, LPUART4, OCOTP, PWM1, RTWDOG, SAI1, SAI3, SNVS, SPDIF, SRC, TEMPMON, TRNG, USB, WDOG1, WDOG2, XBARA */
#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL /* Clock consumers of LPI2C_CLK_ROOT output : LPI2C1, LPI2C2 */
#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL /* Clock consumers of LPSPI_CLK_ROOT output : LPSPI1, LPSPI2 */
#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL /* Clock consumers of MQS_MCLK output : N/A */
#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 62500000UL /* Clock consumers of PERCLK_CLK_ROOT output : GPT1, GPT2, PIT */
#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL /* Clock consumers of SAI1_CLK_ROOT output : N/A */
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL /* Clock consumers of SAI1_MCLK1 output : SAI1 */
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL /* Clock consumers of SAI1_MCLK2 output : SAI1 */
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL /* Clock consumers of SAI1_MCLK3 output : SAI1 */
#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL /* Clock consumers of SAI3_CLK_ROOT output : N/A */
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL /* Clock consumers of SAI3_MCLK1 output : SAI3 */
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL /* Clock consumers of SAI3_MCLK2 output : SAI3 */
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL /* Clock consumers of SAI3_MCLK3 output : SAI3 */
#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL /* Clock consumers of SPDIF0_CLK_ROOT output : SPDIF */
#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL /* Clock consumers of SPDIF0_EXTCLK_OUT output : SPDIF */
#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 132000000UL /* Clock consumers of TRACE_CLK_ROOT output : ARM */
#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL /* Clock consumers of UART_CLK_ROOT output : LPUART1, LPUART2, LPUART3, LPUART4 */
#define BOARD_BOOTCLOCKRUN_USBPHY_CLK 480000000UL /* Clock consumers of USBPHY_CLK output : TEMPMON, USB */
/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration.
*/
extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN;
/*! @brief Sys PLL for BOARD_BootClockRUN configuration.
*/
extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN;
/*! @brief Enet PLL set for BOARD_BootClockRUN configuration.
*/
extern const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN;
/*******************************************************************************
* API for BOARD_BootClockRUN configuration
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/
/*!
* @brief This function executes configuration of clocks.
*
*/
void BOARD_BootClockRUN(void);
#if defined(__cplusplus)
}
#endif /* __cplusplus*/
#endif /* _CLOCK_CONFIG_H_ */

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/***********************************************************************************************************************
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
**********************************************************************************************************************/
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!GlobalInfo
product: Pins v14.0
processor: MIMXRT1011xxxxx
package_id: MIMXRT1011DAE5A
mcu_data: ksdk2_0
processor_version: 14.0.0
board: MIMXRT1010-EVK
external_user_signals: {}
pin_labels:
- {pin_num: '1', pin_signal: GPIO_11, label: GPIO_11, identifier: GPIO_11}
- {pin_num: '10', pin_signal: GPIO_03, label: 'SAI1_RXD0/U10[16]', identifier: LED;USER_LED}
- {pin_num: '4', pin_signal: GPIO_08, label: 'SAI1_MCLK/U10[11]', identifier: USER_BUTTON}
power_domains: {NVCC_GPIO: '3.3'}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
#include "fsl_common.h"
#include "fsl_iomuxc.h"
#include "fsl_gpio.h"
#include "pin_mux.h"
/* FUNCTION ************************************************************************************************************
*
* Function Name : BOARD_InitBootPins
* Description : Calls initialization functions.
*
* END ****************************************************************************************************************/
void BOARD_InitBootPins(void) {
BOARD_InitPins();
}
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
BOARD_InitPins:
- options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'}
- pin_list:
- {pin_num: '3', peripheral: LPUART1, signal: RXD, pin_signal: GPIO_09}
- {pin_num: '2', peripheral: LPUART1, signal: TXD, pin_signal: GPIO_10}
- {pin_num: '10', peripheral: GPIO1, signal: 'gpiomux_io, 03', pin_signal: GPIO_03, identifier: USER_LED, direction: OUTPUT}
- {pin_num: '4', peripheral: GPIO1, signal: 'gpiomux_io, 08', pin_signal: GPIO_08, direction: INPUT, pull_keeper_select: Pull, pull_up_down_config: Pull_Up_100K_Ohm}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
/* FUNCTION ************************************************************************************************************
*
* Function Name : BOARD_InitPins
* Description : Configures pin routing and optionally pin electrical features.
*
* END ****************************************************************************************************************/
void BOARD_InitPins(void) {
CLOCK_EnableClock(kCLOCK_Iomuxc);
/* GPIO configuration of USER_LED on GPIO_03 (pin 10) */
gpio_pin_config_t USER_LED_config = {
.direction = kGPIO_DigitalOutput,
.outputLogic = 0U,
.interruptMode = kGPIO_NoIntmode
};
/* Initialize GPIO functionality on GPIO_03 (pin 10) */
GPIO_PinInit(GPIO1, 3U, &USER_LED_config);
/* GPIO configuration of USER_BUTTON on GPIO_08 (pin 4) */
gpio_pin_config_t USER_BUTTON_config = {
.direction = kGPIO_DigitalInput,
.outputLogic = 0U,
.interruptMode = kGPIO_NoIntmode
};
/* Initialize GPIO functionality on GPIO_08 (pin 4) */
GPIO_PinInit(GPIO1, 8U, &USER_BUTTON_config);
IOMUXC_SetPinMux(IOMUXC_GPIO_03_GPIOMUX_IO03, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_08_GPIOMUX_IO08, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_09_LPUART1_RXD, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_10_LPUART1_TXD, 0U);
IOMUXC_GPR->GPR26 = ((IOMUXC_GPR->GPR26 &
(~(BOARD_INITPINS_IOMUXC_GPR_GPR26_GPIO_SEL_MASK)))
| IOMUXC_GPR_GPR26_GPIO_SEL(0x00U)
);
IOMUXC_SetPinConfig(IOMUXC_GPIO_08_GPIOMUX_IO08, 0xB0A0U);
}
/***********************************************************************************************************************
* EOF
**********************************************************************************************************************/

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/***********************************************************************************************************************
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
**********************************************************************************************************************/
#ifndef _PIN_MUX_H_
#define _PIN_MUX_H_
/***********************************************************************************************************************
* Definitions
**********************************************************************************************************************/
/*! @brief Direction type */
typedef enum _pin_mux_direction
{
kPIN_MUX_DirectionInput = 0U, /* Input direction */
kPIN_MUX_DirectionOutput = 1U, /* Output direction */
kPIN_MUX_DirectionInputOrOutput = 2U /* Input or output direction */
} pin_mux_direction_t;
/*!
* @addtogroup pin_mux
* @{
*/
/***********************************************************************************************************************
* API
**********************************************************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif
/*!
* @brief Calls initialization functions.
*
*/
void BOARD_InitBootPins(void);
#define BOARD_INITPINS_IOMUXC_GPR_GPR26_GPIO_SEL_MASK 0x08U /*!< Select GPIO1 or GPIO2: affected bits mask */
/* GPIO_09 (number 3), LPUART1_RXD/J56[2] */
/* Routed pin properties */
#define BOARD_INITPINS_UART1_RXD_PERIPHERAL LPUART1 /*!< Peripheral name */
#define BOARD_INITPINS_UART1_RXD_SIGNAL RXD /*!< Signal name */
/* GPIO_10 (number 2), LPUART1_TXD/J56[4] */
/* Routed pin properties */
#define BOARD_INITPINS_UART1_TXD_PERIPHERAL LPUART1 /*!< Peripheral name */
#define BOARD_INITPINS_UART1_TXD_SIGNAL TXD /*!< Signal name */
/* GPIO_03 (number 10), SAI1_RXD0/U10[16] */
/* Routed pin properties */
#define BOARD_INITPINS_USER_LED_PERIPHERAL GPIO1 /*!< Peripheral name */
#define BOARD_INITPINS_USER_LED_SIGNAL gpiomux_io /*!< Signal name */
#define BOARD_INITPINS_USER_LED_CHANNEL 3U /*!< Signal channel */
/* GPIO_08 (number 4), SAI1_MCLK/U10[11] */
/* Routed pin properties */
#define BOARD_INITPINS_USER_BUTTON_PERIPHERAL GPIO1 /*!< Peripheral name */
#define BOARD_INITPINS_USER_BUTTON_SIGNAL gpiomux_io /*!< Signal name */
#define BOARD_INITPINS_USER_BUTTON_CHANNEL 8U /*!< Signal channel */
/*!
* @brief Configures pin routing and optionally pin electrical features.
*
*/
void BOARD_InitPins(void);
#if defined(__cplusplus)
}
#endif
/*!
* @}
*/
#endif /* _PIN_MUX_H_ */
/***********************************************************************************************************************
* EOF
**********************************************************************************************************************/

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/*
* Copyright 2019 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "evkmimxrt1010_flexspi_nor_config.h"
/* Component ID definition, used by tools. */
#ifndef FSL_COMPONENT_ID
#define FSL_COMPONENT_ID "platform.drivers.xip_board"
#endif
/*******************************************************************************
* Code
******************************************************************************/
#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
__attribute__((section(".boot_hdr.conf")))
#elif defined(__ICCARM__)
#pragma location = ".boot_hdr.conf"
#endif
const flexspi_nor_config_t qspiflash_config = {
.memConfig =
{
.tag = FLEXSPI_CFG_BLK_TAG,
.version = FLEXSPI_CFG_BLK_VERSION,
.readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad,
.csHoldTime = 3u,
.csSetupTime = 3u,
.sflashPadType = kSerialFlash_4Pads,
.serialClkFreq = kFlexSpiSerialClk_100MHz,
.sflashA1Size = 16u * 1024u * 1024u,
.lookupTable =
{
// Read LUTs
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 24),
FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04),
},
},
.pageSize = 256u,
.sectorSize = 4u * 1024u,
.blockSize = 64u * 1024u,
.isUniformBlockSize = false,
};
#endif /* XIP_BOOT_HEADER_ENABLE */

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/*
* Copyright 2019 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __EVKMIMXRT1011_FLEXSPI_NOR_CONFIG__
#define __EVKMIMXRT1011_FLEXSPI_NOR_CONFIG__
#include <stdint.h>
#include <stdbool.h>
#include "fsl_common.h"
/*! @name Driver version */
/*@{*/
/*! @brief XIP_BOARD driver version 2.0.0. */
#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
/*@}*/
/* FLEXSPI memory config block related definitions */
#define FLEXSPI_CFG_BLK_TAG (0x42464346UL) // ascii "FCFB" Big Endian
#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0
#define FLEXSPI_CFG_BLK_SIZE (512)
/* FLEXSPI Feature related definitions */
#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1
/* Lookup table related definitions */
#define CMD_INDEX_READ 0
#define CMD_INDEX_READSTATUS 1
#define CMD_INDEX_WRITEENABLE 2
#define CMD_INDEX_WRITE 4
#define CMD_LUT_SEQ_IDX_READ 0
#define CMD_LUT_SEQ_IDX_READSTATUS 1
#define CMD_LUT_SEQ_IDX_WRITEENABLE 3
#define CMD_LUT_SEQ_IDX_WRITE 9
#define CMD_SDR 0x01
#define CMD_DDR 0x21
#define RADDR_SDR 0x02
#define RADDR_DDR 0x22
#define CADDR_SDR 0x03
#define CADDR_DDR 0x23
#define MODE1_SDR 0x04
#define MODE1_DDR 0x24
#define MODE2_SDR 0x05
#define MODE2_DDR 0x25
#define MODE4_SDR 0x06
#define MODE4_DDR 0x26
#define MODE8_SDR 0x07
#define MODE8_DDR 0x27
#define WRITE_SDR 0x08
#define WRITE_DDR 0x28
#define READ_SDR 0x09
#define READ_DDR 0x29
#define LEARN_SDR 0x0A
#define LEARN_DDR 0x2A
#define DATSZ_SDR 0x0B
#define DATSZ_DDR 0x2B
#define DUMMY_SDR 0x0C
#define DUMMY_DDR 0x2C
#define DUMMY_RWDS_SDR 0x0D
#define DUMMY_RWDS_DDR 0x2D
#define JMP_ON_CS 0x1F
#define STOP 0
#define FLEXSPI_1PAD 0
#define FLEXSPI_2PAD 1
#define FLEXSPI_4PAD 2
#define FLEXSPI_8PAD 3
#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \
(FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \
FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))
//!@brief Definitions for FlexSPI Serial Clock Frequency
typedef enum _FlexSpiSerialClockFreq
{
kFlexSpiSerialClk_30MHz = 1,
kFlexSpiSerialClk_50MHz = 2,
kFlexSpiSerialClk_60MHz = 3,
kFlexSpiSerialClk_75MHz = 4,
kFlexSpiSerialClk_80MHz = 5,
kFlexSpiSerialClk_100MHz = 6,
kFlexSpiSerialClk_120MHz = 7,
kFlexSpiSerialClk_133MHz = 8,
} flexspi_serial_clk_freq_t;
//!@brief FlexSPI clock configuration type
enum
{
kFlexSpiClk_SDR, //!< Clock configure for SDR mode
kFlexSpiClk_DDR, //!< Clock configurat for DDR mode
};
//!@brief FlexSPI Read Sample Clock Source definition
typedef enum _FlashReadSampleClkSource
{
kFlexSPIReadSampleClk_LoopbackInternally = 0,
kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1,
kFlexSPIReadSampleClk_LoopbackFromSckPad = 2,
kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3,
} flexspi_read_sample_clk_t;
//!@brief Misc feature bit definitions
enum
{
kFlexSpiMiscOffset_DiffClkEnable = 0, //!< Bit for Differential clock enable
kFlexSpiMiscOffset_Ck2Enable = 1, //!< Bit for CK2 enable
kFlexSpiMiscOffset_ParallelEnable = 2, //!< Bit for Parallel mode enable
kFlexSpiMiscOffset_WordAddressableEnable = 3, //!< Bit for Word Addressable enable
kFlexSpiMiscOffset_SafeConfigFreqEnable = 4, //!< Bit for Safe Configuration Frequency enable
kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, //!< Bit for Pad setting override enable
kFlexSpiMiscOffset_DdrModeEnable = 6, //!< Bit for DDR clock confiuration indication.
};
//!@brief Flash Type Definition
enum
{
kFlexSpiDeviceType_SerialNOR = 1, //!< Flash devices are Serial NOR
kFlexSpiDeviceType_SerialNAND = 2, //!< Flash devices are Serial NAND
kFlexSpiDeviceType_SerialRAM = 3, //!< Flash devices are Serial RAM/HyperFLASH
kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND
kFlexSpiDeviceType_MCP_NOR_RAM = 0x13, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial RAMs
};
//!@brief Flash Pad Definitions
enum
{
kSerialFlash_1Pad = 1,
kSerialFlash_2Pads = 2,
kSerialFlash_4Pads = 4,
kSerialFlash_8Pads = 8,
};
//!@brief FlexSPI LUT Sequence structure
typedef struct _lut_sequence
{
uint8_t seqNum; //!< Sequence Number, valid number: 1-16
uint8_t seqId; //!< Sequence Index, valid number: 0-15
uint16_t reserved;
} flexspi_lut_seq_t;
//!@brief Flash Configuration Command Type
enum
{
kDeviceConfigCmdType_Generic, //!< Generic command, for example: configure dummy cycles, drive strength, etc
kDeviceConfigCmdType_QuadEnable, //!< Quad Enable command
kDeviceConfigCmdType_Spi2Xpi, //!< Switch from SPI to DPI/QPI/OPI mode
kDeviceConfigCmdType_Xpi2Spi, //!< Switch from DPI/QPI/OPI to SPI mode
kDeviceConfigCmdType_Spi2NoCmd, //!< Switch to 0-4-4/0-8-8 mode
kDeviceConfigCmdType_Reset, //!< Reset device command
};
//!@brief FlexSPI Memory Configuration Block
typedef struct _FlexSPIConfig
{
uint32_t tag; //!< [0x000-0x003] Tag, fixed value 0x42464346UL
uint32_t version; //!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix
uint32_t reserved0; //!< [0x008-0x00b] Reserved for future use
uint8_t readSampleClkSrc; //!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3
uint8_t csHoldTime; //!< [0x00d-0x00d] CS hold time, default value: 3
uint8_t csSetupTime; //!< [0x00e-0x00e] CS setup time, default value: 3
uint8_t columnAddressWidth; //!< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For
//! Serial NAND, need to refer to datasheet
uint8_t deviceModeCfgEnable; //!< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable
uint8_t deviceModeType; //!< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch,
//! Generic configuration, etc.
uint16_t waitTimeCfgCommands; //!< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for
//! DPI/QPI/OPI switch or reset command
flexspi_lut_seq_t deviceModeSeq; //!< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt
//! sequence number, [31:16] Reserved
uint32_t deviceModeArg; //!< [0x018-0x01b] Argument/Parameter for device configuration
uint8_t configCmdEnable; //!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable
uint8_t configModeType[3]; //!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe
flexspi_lut_seq_t
configCmdSeqs[3]; //!< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq
uint32_t reserved1; //!< [0x02c-0x02f] Reserved for future use
uint32_t configCmdArgs[3]; //!< [0x030-0x03b] Arguments/Parameters for device Configuration commands
uint32_t reserved2; //!< [0x03c-0x03f] Reserved for future use
uint32_t controllerMiscOption; //!< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more
//! details
uint8_t deviceType; //!< [0x044-0x044] Device Type: See Flash Type Definition for more details
uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal
uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequency, device specific definitions, See System Boot
//! Chapter for more details
uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot
//! be done using 1 LUT sequence, currently, only applicable to HyperFLASH
uint32_t reserved3[2]; //!< [0x048-0x04f] Reserved for future use
uint32_t sflashA1Size; //!< [0x050-0x053] Size of Flash connected to A1
uint32_t sflashA2Size; //!< [0x054-0x057] Size of Flash connected to A2
uint32_t sflashB1Size; //!< [0x058-0x05b] Size of Flash connected to B1
uint32_t sflashB2Size; //!< [0x05c-0x05f] Size of Flash connected to B2
uint32_t csPadSettingOverride; //!< [0x060-0x063] CS pad setting override value
uint32_t sclkPadSettingOverride; //!< [0x064-0x067] SCK pad setting override value
uint32_t dataPadSettingOverride; //!< [0x068-0x06b] data pad setting override value
uint32_t dqsPadSettingOverride; //!< [0x06c-0x06f] DQS pad setting override value
uint32_t timeoutInMs; //!< [0x070-0x073] Timeout threshold for read status command
uint32_t commandInterval; //!< [0x074-0x077] CS deselect interval between two commands
uint16_t dataValidTime[2]; //!< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns
uint16_t busyOffset; //!< [0x07c-0x07d] Busy offset, valid value: 0-31
uint16_t busyBitPolarity; //!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 -
//! busy flag is 0 when flash device is busy
uint32_t lookupTable[64]; //!< [0x080-0x17f] Lookup table holds Flash command sequences
flexspi_lut_seq_t lutCustomSeq[12]; //!< [0x180-0x1af] Customizable LUT Sequences
uint32_t reserved4[4]; //!< [0x1b0-0x1bf] Reserved for future use
} flexspi_mem_config_t;
/* */
#define NOR_CMD_INDEX_READ CMD_INDEX_READ //!< 0
#define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS //!< 1
#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE //!< 2
#define NOR_CMD_INDEX_ERASESECTOR 3 //!< 3
#define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE //!< 4
#define NOR_CMD_INDEX_CHIPERASE 5 //!< 5
#define NOR_CMD_INDEX_DUMMY 6 //!< 6
#define NOR_CMD_INDEX_ERASEBLOCK 7 //!< 7
#define NOR_CMD_LUT_SEQ_IDX_READ CMD_LUT_SEQ_IDX_READ //!< 0 READ LUT sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_READSTATUS \
CMD_LUT_SEQ_IDX_READSTATUS //!< 1 Read Status LUT sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \
2 //!< 2 Read status DPI/QPI/OPI sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE \
CMD_LUT_SEQ_IDX_WRITEENABLE //!< 3 Write Enable sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \
4 //!< 4 Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5 //!< 5 Erase Sector sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8 //!< 8 Erase Block sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM \
CMD_LUT_SEQ_IDX_WRITE //!< 9 Program sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11 //!< 11 Chip Erase sequence in lookupTable id stored in config block
#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13 //!< 13 Read SFDP sequence in lookupTable id stored in config block
#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \
14 //!< 14 Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \
15 //!< 15 Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config blobk
/*
* Serial NOR configuration block
*/
typedef struct _flexspi_nor_config
{
flexspi_mem_config_t memConfig; //!< Common memory configuration info via FlexSPI
uint32_t pageSize; //!< Page size of Serial NOR
uint32_t sectorSize; //!< Sector size of Serial NOR
uint8_t ipcmdSerialClkFreq; //!< Clock frequency for IP command
uint8_t isUniformBlockSize; //!< Sector/Block size is the same
uint8_t reserved0[2]; //!< Reserved for future use
uint8_t serialNorType; //!< Serial NOR Flash type: 0/1/2/3
uint8_t needExitNoCmdMode; //!< Need to exit NoCmd mode before other IP command
uint8_t halfClkForNonReadCmd; //!< Half the Serial Clock for non-read command: true/false
uint8_t needRestoreNoCmdMode; //!< Need to Restore NoCmd mode after IP command execution
uint32_t blockSize; //!< Block size
uint32_t reserve2[11]; //!< Reserved for future use
} flexspi_nor_config_t;
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __cplusplus
}
#endif
#endif /* __EVKMIMXRT1011_FLEXSPI_NOR_CONFIG__ */

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managed_components/espressif__tinyusb/hw/bsp/imxrt/boards/metro_m7_1011/metro_m7_1011.ld Normal file
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/*
** ###################################################################
** Processors: MIMXRT1011CAE4A
** MIMXRT1011DAE5A
**
** Compiler: GNU C Compiler
** Reference manual: IMXRT1010RM Rev.0, 09/2019
** Version: rev. 1.0, 2019-08-01
** Build: b210709
**
** Abstract:
** Linker file for the GNU C Compiler
**
** Copyright 2016 Freescale Semiconductor, Inc.
** Copyright 2016-2021 NXP
** All rights reserved.
**
** SPDX-License-Identifier: BSD-3-Clause
**
** http: www.nxp.com
** mail: support@nxp.com
**
** ###################################################################
*/
/* Entry Point */
ENTRY(Reset_Handler)
HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x00000400 : 0;
/* Specify the memory areas */
MEMORY
{
m_flash_config (RX) : ORIGIN = 0x60000400, LENGTH = 0x00000C00
m_ivt (RX) : ORIGIN = 0x60001000, LENGTH = 0x00001000
m_interrupts (RX) : ORIGIN = 0x6000C000, LENGTH = 0x00000400
m_text (RX) : ORIGIN = 0x6000C400, LENGTH = (8*1024*1024 - 0xC400)
m_qacode (RX) : ORIGIN = 0x00000000, LENGTH = 0x00008000
m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00008000
m_data2 (RW) : ORIGIN = 0x20200000, LENGTH = 0x00010000
}
/* Define output sections */
SECTIONS
{
__NCACHE_REGION_START = ORIGIN(m_data2);
__NCACHE_REGION_SIZE = 0;
.flash_config :
{
. = ALIGN(4);
__FLASH_BASE = .;
KEEP(* (.boot_hdr.conf)) /* flash config section */
. = ALIGN(4);
} > m_flash_config
ivt_begin = ORIGIN(m_flash_config) + LENGTH(m_flash_config);
.ivt : AT(ivt_begin)
{
. = ALIGN(4);
KEEP(* (.boot_hdr.ivt)) /* ivt section */
KEEP(* (.boot_hdr.boot_data)) /* boot section */
KEEP(* (.boot_hdr.dcd_data)) /* dcd section */
. = ALIGN(4);
} > m_ivt
/* The startup code goes first into internal RAM */
.interrupts :
{
__VECTOR_TABLE = .;
__Vectors = .;
. = ALIGN(4);
KEEP(*(.isr_vector)) /* Startup code */
. = ALIGN(4);
} > m_interrupts
/* The program code and other data goes into internal RAM */
.text :
{
. = ALIGN(4);
*(.text) /* .text sections (code) */
*(.text*) /* .text* sections (code) */
*(.rodata) /* .rodata sections (constants, strings, etc.) */
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
*(.glue_7) /* glue arm to thumb code */
*(.glue_7t) /* glue thumb to arm code */
*(.eh_frame)
KEEP (*(.init))
KEEP (*(.fini))
. = ALIGN(4);
} > m_text
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > m_text
.ARM :
{
__exidx_start = .;
*(.ARM.exidx*)
__exidx_end = .;
} > m_text
.ctors :
{
__CTOR_LIST__ = .;
/* gcc uses crtbegin.o to find the start of
the constructors, so we make sure it is
first. Because this is a wildcard, it
doesn't matter if the user does not
actually link against crtbegin.o; the
linker won't look for a file to match a
wildcard. The wildcard also means that it
doesn't matter which directory crtbegin.o
is in. */
KEEP (*crtbegin.o(.ctors))
KEEP (*crtbegin?.o(.ctors))
/* We don't want to include the .ctor section from
from the crtend.o file until after the sorted ctors.
The .ctor section from the crtend file contains the
end of ctors marker and it must be last */
KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
__CTOR_END__ = .;
} > m_text
.dtors :
{
__DTOR_LIST__ = .;
KEEP (*crtbegin.o(.dtors))
KEEP (*crtbegin?.o(.dtors))
KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
__DTOR_END__ = .;
} > m_text
.preinit_array :
{
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP (*(.preinit_array*))
PROVIDE_HIDDEN (__preinit_array_end = .);
} > m_text
.init_array :
{
PROVIDE_HIDDEN (__init_array_start = .);
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array*))
PROVIDE_HIDDEN (__init_array_end = .);
} > m_text
.fini_array :
{
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP (*(SORT(.fini_array.*)))
KEEP (*(.fini_array*))
PROVIDE_HIDDEN (__fini_array_end = .);
} > m_text
__etext = .; /* define a global symbol at end of code */
__DATA_ROM = .; /* Symbol is used by startup for data initialization */
.interrupts_ram :
{
. = ALIGN(4);
__VECTOR_RAM__ = .;
__interrupts_ram_start__ = .; /* Create a global symbol at data start */
*(.m_interrupts_ram) /* This is a user defined section */
. += VECTOR_RAM_SIZE;
. = ALIGN(4);
__interrupts_ram_end__ = .; /* Define a global symbol at data end */
} > m_data
__VECTOR_RAM = DEFINED(__ram_vector_table__) ? __VECTOR_RAM__ : ORIGIN(m_interrupts);
__RAM_VECTOR_TABLE_SIZE_BYTES = DEFINED(__ram_vector_table__) ? (__interrupts_ram_end__ - __interrupts_ram_start__) : 0x0;
.data : AT(__DATA_ROM)
{
. = ALIGN(4);
__DATA_RAM = .;
__data_start__ = .; /* create a global symbol at data start */
*(m_usb_dma_init_data)
*(.data) /* .data sections */
*(.data*) /* .data* sections */
*(DataQuickAccess) /* quick access data section */
KEEP(*(.jcr*))
. = ALIGN(4);
__data_end__ = .; /* define a global symbol at data end */
} > m_data
__ram_function_flash_start = __DATA_ROM + (__data_end__ - __data_start__); /* Symbol is used by startup for TCM data initialization */
.ram_function : AT(__ram_function_flash_start)
{
. = ALIGN(32);
__ram_function_start__ = .;
*(CodeQuickAccess)
. = ALIGN(128);
__ram_function_end__ = .;
} > m_qacode
__NDATA_ROM = __ram_function_flash_start + (__ram_function_end__ - __ram_function_start__);
.ncache.init : AT(__NDATA_ROM)
{
__noncachedata_start__ = .; /* create a global symbol at ncache data start */
*(NonCacheable.init)
. = ALIGN(4);
__noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
} > m_data
. = __noncachedata_init_end__;
.ncache :
{
*(NonCacheable)
. = ALIGN(4);
__noncachedata_end__ = .; /* define a global symbol at ncache data end */
} > m_data
__DATA_END = __NDATA_ROM + (__noncachedata_init_end__ - __noncachedata_start__);
text_end = ORIGIN(m_text) + LENGTH(m_text);
ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
/* Uninitialized data section */
.bss :
{
/* This is used by the startup in order to initialize the .bss section */
. = ALIGN(4);
__START_BSS = .;
__bss_start__ = .;
*(m_usb_dma_noninit_data)
*(.bss)
*(.bss*)
*(COMMON)
. = ALIGN(4);
__bss_end__ = .;
__END_BSS = .;
} > m_data
.heap :
{
. = ALIGN(8);
__end__ = .;
PROVIDE(end = .);
__HeapBase = .;
. += HEAP_SIZE;
__HeapLimit = .;
__heap_limit = .; /* Add for _sbrk */
} > m_data
.stack :
{
. = ALIGN(8);
. += STACK_SIZE;
} > m_data
/* Initializes stack on the end of block */
__StackTop = ORIGIN(m_data) + LENGTH(m_data);
__StackLimit = __StackTop - STACK_SIZE;
PROVIDE(__stack = __StackTop);
.ARM.attributes 0 : { *(.ARM.attributes) }
ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
}

400
managed_components/espressif__tinyusb/hw/bsp/imxrt/boards/metro_m7_1011/metro_m7_1011.mex Normal file
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<?xml version="1.0" encoding= "UTF-8" ?>
<configuration name="MIMXRT1010-EVK" xsi:schemaLocation="http://mcuxpresso.nxp.com/XSD/mex_configuration_14 http://mcuxpresso.nxp.com/XSD/mex_configuration_14.xsd" uuid="f341eb24-9521-4127-8932-81692aeb76df" version="14" xmlns="http://mcuxpresso.nxp.com/XSD/mex_configuration_14" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<common>
<processor>MIMXRT1011xxxxx</processor>
<package>MIMXRT1011DAE5A</package>
<board>MIMXRT1010-EVK</board>
<board_revision>A</board_revision>
<mcu_data>ksdk2_0</mcu_data>
<cores selected="core0">
<core name="Cortex-M7F" id="core0" description="M7 core"/>
</cores>
<description></description>
</common>
<preferences>
<validate_boot_init_only>true</validate_boot_init_only>
<generate_extended_information>false</generate_extended_information>
<generate_code_modified_registers_only>false</generate_code_modified_registers_only>
<update_include_paths>true</update_include_paths>
<generate_registers_defines>false</generate_registers_defines>
</preferences>
<tools>
<pins name="Pins" version="14.0" enabled="true" update_project_code="true">
<generated_project_files>
<file path="board/pin_mux.c" update_enabled="true"/>
<file path="board/pin_mux.h" update_enabled="true"/>
</generated_project_files>
<pins_profile>
<processor_version>14.0.0</processor_version>
<pin_labels>
<pin_label pin_num="1" pin_signal="GPIO_11" label="GPIO_11" identifier="GPIO_11"/>
<pin_label pin_num="10" pin_signal="GPIO_03" label="SAI1_RXD0/U10[16]" identifier="LED;USER_LED"/>
<pin_label pin_num="4" pin_signal="GPIO_08" label="SAI1_MCLK/U10[11]" identifier="USER_BUTTON"/>
</pin_labels>
<external_user_signals>
<routingDetailsColumns/>
<properties/>
</external_user_signals>
<power_domains>
<power_domain name="NVCC_GPIO" value="3.3"/>
</power_domains>
</pins_profile>
<functions_list>
<function name="BOARD_InitPins">
<description>Configures pin routing and optionally pin electrical features.</description>
<options>
<callFromInitBoot>true</callFromInitBoot>
<coreID>core0</coreID>
<enableClock>true</enableClock>
</options>
<dependencies>
<dependency resourceType="Peripheral" resourceId="LPUART1" description="Peripheral LPUART1 is not initialized" problem_level="1" source="Pins:BOARD_InitPins">
<feature name="initialized" evaluation="equal">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="Peripheral" resourceId="GPIO1" description="Peripheral GPIO1 is not initialized" problem_level="1" source="Pins:BOARD_InitPins">
<feature name="initialized" evaluation="equal">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitPins">
<feature name="enabled" evaluation="equal" configuration="core0">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitPins">
<feature name="enabled" evaluation="equal" configuration="core0">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.igpio" description="Pins initialization requires the IGPIO Driver in the project." problem_level="2" source="Pins:BOARD_InitPins">
<feature name="enabled" evaluation="equal" configuration="core0">
<data>true</data>
</feature>
</dependency>
</dependencies>
<pins>
<pin peripheral="LPUART1" signal="RXD" pin_num="3" pin_signal="GPIO_09"/>
<pin peripheral="LPUART1" signal="TXD" pin_num="2" pin_signal="GPIO_10"/>
<pin peripheral="GPIO1" signal="gpiomux_io, 03" pin_num="10" pin_signal="GPIO_03">
<pin_features>
<pin_feature name="identifier" value="USER_LED"/>
<pin_feature name="direction" value="OUTPUT"/>
</pin_features>
</pin>
<pin peripheral="GPIO1" signal="gpiomux_io, 08" pin_num="4" pin_signal="GPIO_08">
<pin_features>
<pin_feature name="direction" value="INPUT"/>
<pin_feature name="pull_keeper_select" value="Pull"/>
<pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
</pin_features>
</pin>
</pins>
</function>
</functions_list>
</pins>
<clocks name="Clocks" version="12.0" enabled="true" update_project_code="true">
<generated_project_files>
<file path="board/clock_config.c" update_enabled="true"/>
<file path="board/clock_config.h" update_enabled="true"/>
</generated_project_files>
<clocks_profile>
<processor_version>14.0.0</processor_version>
</clocks_profile>
<clock_configurations>
<clock_configuration name="BOARD_BootClockRUN" id_prefix="" prefix_user_defined="false">
<description></description>
<options/>
<dependencies>
<dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtali" description="&apos;RTC_XTALI&apos; (Pins tool id: XTALOSC24M.rtc_xtali, Clocks tool id: XTALOSC24M.RTC_XTALI) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
<feature name="routed" evaluation="">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtali" description="&apos;RTC_XTALI&apos; (Pins tool id: XTALOSC24M.rtc_xtali, Clocks tool id: XTALOSC24M.RTC_XTALI) needs to have &apos;INPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
<feature name="direction" evaluation="">
<data>INPUT</data>
</feature>
</dependency>
<dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtalo" description="&apos;RTC_XTALO&apos; (Pins tool id: XTALOSC24M.rtc_xtalo, Clocks tool id: XTALOSC24M.RTC_XTALO) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
<feature name="routed" evaluation="">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtalo" description="&apos;RTC_XTALO&apos; (Pins tool id: XTALOSC24M.rtc_xtalo, Clocks tool id: XTALOSC24M.RTC_XTALO) needs to have &apos;OUTPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
<feature name="direction" evaluation="">
<data>OUTPUT</data>
</feature>
</dependency>
<dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtali" description="&apos;XTALI&apos; (Pins tool id: XTALOSC24M.xtali, Clocks tool id: XTALOSC24M.XTALI) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
<feature name="routed" evaluation="">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtali" description="&apos;XTALI&apos; (Pins tool id: XTALOSC24M.xtali, Clocks tool id: XTALOSC24M.XTALI) needs to have &apos;INPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
<feature name="direction" evaluation="">
<data>INPUT</data>
</feature>
</dependency>
<dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtalo" description="&apos;XTALO&apos; (Pins tool id: XTALOSC24M.xtalo, Clocks tool id: XTALOSC24M.XTALO) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
<feature name="routed" evaluation="">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtalo" description="&apos;XTALO&apos; (Pins tool id: XTALOSC24M.xtalo, Clocks tool id: XTALOSC24M.XTALO) needs to have &apos;OUTPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
<feature name="direction" evaluation="">
<data>OUTPUT</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN">
<feature name="enabled" evaluation="equal" configuration="core0">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Clocks initialization requires the IOMUXC Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN">
<feature name="enabled" evaluation="equal" configuration="core0">
<data>true</data>
</feature>
</dependency>
</dependencies>
<clock_sources>
<clock_source id="XTALOSC24M.RTC_OSC.outFreq" value="32.768 kHz" locked="false" enabled="true"/>
</clock_sources>
<clock_outputs>
<clock_output id="ADC_ALT_CLK.outFreq" value="40 MHz" locked="false" accuracy=""/>
<clock_output id="CKIL_SYNC_CLK_ROOT.outFreq" value="32.768 kHz" locked="false" accuracy=""/>
<clock_output id="CLK_1M.outFreq" value="1 MHz" locked="false" accuracy=""/>
<clock_output id="CLK_24M.outFreq" value="24 MHz" locked="false" accuracy=""/>
<clock_output id="CORE_CLK_ROOT.outFreq" value="500 MHz" locked="false" accuracy=""/>
<clock_output id="ENET_500M_REF_CLK.outFreq" value="500 MHz" locked="false" accuracy=""/>
<clock_output id="FLEXIO1_CLK_ROOT.outFreq" value="30 MHz" locked="false" accuracy=""/>
<clock_output id="FLEXSPI_CLK_ROOT.outFreq" value="132 MHz" locked="false" accuracy=""/>
<clock_output id="GPT1_ipg_clk_highfreq.outFreq" value="62.5 MHz" locked="false" accuracy=""/>
<clock_output id="GPT2_ipg_clk_highfreq.outFreq" value="62.5 MHz" locked="false" accuracy=""/>
<clock_output id="IPG_CLK_ROOT.outFreq" value="125 MHz" locked="false" accuracy=""/>
<clock_output id="LPI2C_CLK_ROOT.outFreq" value="60 MHz" locked="false" accuracy=""/>
<clock_output id="LPSPI_CLK_ROOT.outFreq" value="105.6 MHz" locked="false" accuracy=""/>
<clock_output id="MQS_MCLK.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
<clock_output id="PERCLK_CLK_ROOT.outFreq" value="62.5 MHz" locked="false" accuracy=""/>
<clock_output id="SAI1_CLK_ROOT.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
<clock_output id="SAI1_MCLK1.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
<clock_output id="SAI1_MCLK2.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
<clock_output id="SAI1_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/>
<clock_output id="SAI3_CLK_ROOT.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
<clock_output id="SAI3_MCLK1.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
<clock_output id="SAI3_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/>
<clock_output id="SPDIF0_CLK_ROOT.outFreq" value="30 MHz" locked="false" accuracy=""/>
<clock_output id="TRACE_CLK_ROOT.outFreq" value="132 MHz" locked="false" accuracy=""/>
<clock_output id="UART_CLK_ROOT.outFreq" value="80 MHz" locked="false" accuracy=""/>
<clock_output id="USBPHY_CLK.outFreq" value="480 MHz" locked="false" accuracy=""/>
</clock_outputs>
<clock_settings>
<setting id="CCM.ADC_ACLK_PODF.scale" value="12" locked="true"/>
<setting id="CCM.AHB_PODF.scale" value="1" locked="true"/>
<setting id="CCM.FLEXSPI_PODF.scale" value="4" locked="true"/>
<setting id="CCM.IPG_PODF.scale" value="4" locked="false"/>
<setting id="CCM.LPSPI_PODF.scale" value="5" locked="false"/>
<setting id="CCM.PERCLK_PODF.scale" value="2" locked="true"/>
<setting id="CCM.PRE_PERIPH_CLK_SEL.sel" value="CCM_ANALOG.ENET_500M_REF_CLK" locked="false"/>
<setting id="CCM.SAI1_CLK_SEL.sel" value="CCM_ANALOG.PLL3_PFD2_CLK" locked="false"/>
<setting id="CCM.SAI3_CLK_SEL.sel" value="CCM_ANALOG.PLL3_PFD2_CLK" locked="false"/>
<setting id="CCM.TRACE_CLK_SEL.sel" value="CCM_ANALOG.PLL2_MAIN_CLK" locked="false"/>
<setting id="CCM_ANALOG.PLL2.denom" value="1" locked="false"/>
<setting id="CCM_ANALOG.PLL2.num" value="0" locked="false"/>
<setting id="CCM_ANALOG.PLL2_BYPASS.sel" value="CCM_ANALOG.PLL2_OUT_CLK" locked="false"/>
<setting id="CCM_ANALOG.PLL2_PFD0_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD0" locked="false"/>
<setting id="CCM_ANALOG.PLL2_PFD1_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD1" locked="false"/>
<setting id="CCM_ANALOG.PLL2_PFD2_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD2" locked="false"/>
<setting id="CCM_ANALOG.PLL2_PFD2_DIV.scale" value="18" locked="true"/>
<setting id="CCM_ANALOG.PLL2_PFD2_MUL.scale" value="18" locked="true"/>
<setting id="CCM_ANALOG.PLL2_PFD3_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD3" locked="false"/>
<setting id="CCM_ANALOG.PLL2_PFD3_DIV.scale" value="18" locked="true"/>
<setting id="CCM_ANALOG.PLL2_PFD3_MUL.scale" value="18" locked="true"/>
<setting id="CCM_ANALOG.PLL3_BYPASS.sel" value="CCM_ANALOG.PLL3" locked="false"/>
<setting id="CCM_ANALOG.PLL3_PFD0_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD0" locked="false"/>
<setting id="CCM_ANALOG.PLL3_PFD0_DIV.scale" value="22" locked="true"/>
<setting id="CCM_ANALOG.PLL3_PFD0_MUL.scale" value="18" locked="true"/>
<setting id="CCM_ANALOG.PLL3_PFD1_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD1" locked="false"/>
<setting id="CCM_ANALOG.PLL3_PFD2_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD2" locked="false"/>
<setting id="CCM_ANALOG.PLL3_PFD3_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD3" locked="false"/>
<setting id="CCM_ANALOG.PLL3_PFD3_DIV.scale" value="18" locked="true"/>
<setting id="CCM_ANALOG.PLL3_PFD3_MUL.scale" value="18" locked="true"/>
<setting id="CCM_ANALOG.PLL6_BYPASS.sel" value="CCM_ANALOG.PLL6" locked="false"/>
<setting id="CCM_ANALOG_PLL_USB1_EN_USB_CLKS_CFG" value="Enabled" locked="false"/>
<setting id="CCM_ANALOG_PLL_USB1_EN_USB_CLKS_OUT_CFG" value="Enabled" locked="false"/>
<setting id="CCM_ANALOG_PLL_USB1_POWER_CFG" value="Yes" locked="false"/>
</clock_settings>
<called_from_default_init>true</called_from_default_init>
</clock_configuration>
</clock_configurations>
</clocks>
<dcdx name="DCDx" version="2.0" enabled="false" update_project_code="true">
<generated_project_files/>
<dcdx_profile>
<processor_version>0.0.0</processor_version>
</dcdx_profile>
<dcdx_configurations/>
</dcdx>
<periphs name="Peripherals" version="12.0" enabled="false" update_project_code="true">
<generated_project_files/>
<peripherals_profile>
<processor_version>13.0.2</processor_version>
</peripherals_profile>
<functional_groups>
<functional_group name="BOARD_InitPeripherals" uuid="5e519eed-bd94-4950-84de-0f29de85bcea" called_from_default_init="true" id_prefix="" core="core0">
<description></description>
<options/>
<dependencies/>
<instances>
<instance name="COMBO_SENSOR" uuid="2342e373-ea2e-4bed-8aa4-bd33509155f6" type="lpi2c" type_id="lpi2c_6b71962515c3208facfccd030afebc98" mode="master" peripheral="LPI2C1" enabled="false" comment="" custom_name_enabled="true" editing_lock="false">
<config_set name="main" quick_selection="qs_interrupt">
<setting name="clockSource" value="Lpi2cClock"/>
<setting name="clockSourceFreq" value="BOARD_BootClockRUN"/>
</config_set>
<config_set name="interrupt_vector"/>
<config_set name="master" quick_selection="qs_master_transfer">
<setting name="mode" value="transfer"/>
<struct name="config">
<setting name="enableMaster" value="true"/>
<setting name="enableDoze" value="true"/>
<setting name="debugEnable" value="false"/>
<setting name="ignoreAck" value="false"/>
<setting name="pinConfig" value="kLPI2C_2PinOpenDrain"/>
<setting name="baudRate_Hz" value="100000"/>
<setting name="busIdleTimeout_ns" value="0"/>
<setting name="pinLowTimeout_ns" value="0"/>
<setting name="sdaGlitchFilterWidth_ns" value="0"/>
<setting name="sclGlitchFilterWidth_ns" value="0"/>
<struct name="hostRequest">
<setting name="enable" value="false"/>
<setting name="source" value="kLPI2C_HostRequestExternalPin"/>
<setting name="polarity" value="kLPI2C_HostRequestPinActiveHigh"/>
</struct>
<set name="edmaRequestSources">
<selected/>
</set>
</struct>
<struct name="transfer">
<setting name="blocking" value="false"/>
<setting name="enable_custom_handle" value="false"/>
<struct name="callback">
<setting name="name" value=""/>
<setting name="userData" value=""/>
</struct>
<set name="flags">
<selected/>
</set>
<setting name="slaveAddress" value="0"/>
<setting name="direction" value="kLPI2C_Write"/>
<setting name="subaddress" value="0"/>
<setting name="subaddressSize" value="1"/>
<setting name="blocking_buffer" value="false"/>
<setting name="enable_custom_buffer" value="false"/>
<setting name="dataSize" value="1"/>
</struct>
</config_set>
</instance>
<instance name="DEBUG_UART" uuid="0d9274fe-8f49-48a8-8e6a-8c3ac009384d" type="lpuart" type_id="lpuart_bf01db7d964092f3cf860852cba17f7e" mode="polling" peripheral="LPUART1" enabled="false" comment="" custom_name_enabled="true" editing_lock="false">
<config_set name="lpuartConfig_t" quick_selection="QuickSelection1">
<struct name="lpuartConfig">
<setting name="clockSource" value="LpuartClock"/>
<setting name="lpuartSrcClkFreq" value="ClocksTool_DefaultInit"/>
<setting name="baudRate_Bps" value="115200"/>
<setting name="parityMode" value="kLPUART_ParityDisabled"/>
<setting name="dataBitsCount" value="kLPUART_EightDataBits"/>
<setting name="isMsb" value="false"/>
<setting name="stopBitCount" value="kLPUART_OneStopBit"/>
<setting name="enableMatchAddress1" value="false"/>
<setting name="matchAddress1" value="0"/>
<setting name="enableMatchAddress2" value="false"/>
<setting name="matchAddress2" value="0"/>
<setting name="txFifoWatermark" value="0"/>
<setting name="rxFifoWatermark" value="1"/>
<setting name="enableRxRTS" value="false"/>
<setting name="enableTxCTS" value="false"/>
<setting name="txCtsSource" value="kLPUART_CtsSourcePin"/>
<setting name="txCtsConfig" value="kLPUART_CtsSampleAtStart"/>
<setting name="rxIdleType" value="kLPUART_IdleTypeStartBit"/>
<setting name="rxIdleConfig" value="kLPUART_IdleCharacter1"/>
<setting name="enableTx" value="true"/>
<setting name="enableRx" value="true"/>
</struct>
</config_set>
</instance>
<instance name="USER_BUTTON" uuid="6c9e57cc-d98c-4f6d-bf94-3920a8fd474e" type="igpio" type_id="igpio_b1c1fa279aa7069dca167502b8589cb7" mode="GPIO" peripheral="GPIO2" enabled="false" comment="" custom_name_enabled="true" editing_lock="false">
<config_set name="fsl_gpio">
<setting name="enable_irq_comb_0_15" value="false"/>
<struct name="gpio_interrupt_comb_0_15">
<setting name="IRQn" value="GPIO2_Combined_0_15_IRQn"/>
<setting name="enable_interrrupt" value="enabled"/>
<setting name="enable_priority" value="false"/>
<setting name="priority" value="0"/>
<setting name="enable_custom_name" value="false"/>
</struct>
</config_set>
</instance>
<instance name="USER_LED" uuid="0f7a142d-ad6c-4e47-a2a3-015e90afa37b" type="igpio" type_id="igpio_b1c1fa279aa7069dca167502b8589cb7" mode="GPIO" peripheral="GPIO1" enabled="false" comment="" custom_name_enabled="true" editing_lock="false">
<config_set name="fsl_gpio">
<setting name="enable_irq_comb_0_15" value="false"/>
<struct name="gpio_interrupt_comb_0_15">
<setting name="IRQn" value="GPIO1_Combined_0_15_IRQn"/>
<setting name="enable_interrrupt" value="enabled"/>
<setting name="enable_priority" value="false"/>
<setting name="priority" value="0"/>
<setting name="enable_custom_name" value="false"/>
</struct>
<setting name="enable_irq_comb_16_31" value="false"/>
<struct name="gpio_interrupt_comb_16_31">
<setting name="IRQn" value="GPIO1_Combined_16_31_IRQn"/>
<setting name="enable_interrrupt" value="enabled"/>
<setting name="enable_priority" value="false"/>
<setting name="priority" value="0"/>
<setting name="enable_custom_name" value="false"/>
</struct>
</config_set>
</instance>
<instance name="NVIC" uuid="2a54e709-5718-4b89-8b7b-71cefb418658" type="nvic" type_id="nvic_57b5eef3774cc60acaede6f5b8bddc67" mode="general" peripheral="NVIC" enabled="true" comment="" custom_name_enabled="false" editing_lock="false">
<config_set name="nvic">
<array name="interrupt_table"/>
<array name="interrupts"/>
</config_set>
</instance>
</instances>
</functional_group>
</functional_groups>
<components>
<component name="system" uuid="991327ca-3ad0-49d1-aff3-37b7734338db" type_id="system">
<config_set_global name="global_system_definitions">
<setting name="user_definitions" value=""/>
<setting name="user_includes" value=""/>
</config_set_global>
</component>
<component name="msg" uuid="3e46e698-099c-4180-92f5-2af1abbb93a5" type_id="msg">
<config_set_global name="global_messages"/>
</component>
<component name="gpio_adapter_common" uuid="27e43a4b-bddb-4db2-8f6b-3f6a73008a27" type_id="gpio_adapter_common_57579b9ac814fe26bf95df0a384c36b6">
<config_set_global name="global_gpio_adapter_common" quick_selection="default"/>
</component>
<component name="generic_uart" uuid="c946fe99-5d76-4cca-8be0-dea3c7861b68" type_id="generic_uart_8cae00565451cf2346eb1b8c624e73a6">
<config_set_global name="global_uart"/>
</component>
<component name="generic_can" uuid="c18a4299-93be-44e8-b563-3985b3e264c5" type_id="generic_can_1bfdd78b1af214566c1f23cf6a582d80">
<config_set_global name="global_can"/>
</component>
<component name="uart_cmsis_common" uuid="6149366a-a07f-40a7-8909-00ba459085a7" type_id="uart_cmsis_common_9cb8e302497aa696fdbb5a4fd622c2a8">
<config_set_global name="global_USART_CMSIS_common" quick_selection="default"/>
</component>
<component name="generic_enet" uuid="15cc4d18-2002-44a4-b7e7-f681a046f26c" type_id="generic_enet_74db5c914f0ddbe47d86af40cb77a619">
<config_set_global name="global_enet"/>
</component>
</components>
</periphs>
<tee name="TEE" version="4.0" enabled="false" update_project_code="true">
<generated_project_files/>
<tee_profile>
<processor_version>0.0.0</processor_version>
</tee_profile>
</tee>
</tools>
</configuration>

15
managed_components/espressif__tinyusb/hw/bsp/imxrt/boards/metro_m7_1011_sd/board.cmake Normal file
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set(MCU_VARIANT MIMXRT1011)
set(JLINK_DEVICE MIMXRT1011xxx5A)
set(PYOCD_TARGET mimxrt1010)
set(NXPLINK_DEVICE MIMXRT1011xxxxx:EVK-MIMXRT1010)
function(update_board TARGET)
target_sources(${TARGET} PUBLIC
${CMAKE_CURRENT_FUNCTION_LIST_DIR}/evkmimxrt1010_flexspi_nor_config.c
)
target_compile_definitions(${TARGET} PUBLIC
CPU_MIMXRT1011DAE5A
CFG_EXAMPLE_VIDEO_READONLY
)
endfunction()

55
managed_components/espressif__tinyusb/hw/bsp/imxrt/boards/metro_m7_1011_sd/board.h Normal file
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@@ -0,0 +1,55 @@
/*
* The MIT License (MIT)
*
* Copyright (c) 2019, Ha Thach (tinyusb.org)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* This file is part of the TinyUSB stack.
*/
/* metadata:
name: Adafruit Metro M7 1011 SD
url: https://www.adafruit.com/product/5600
*/
#ifndef BOARD_METRO_M7_1011_SD_H_
#define BOARD_METRO_M7_1011_SD_H_
// required since iMXRT MCUX-SDK include this file for board size
#define BOARD_FLASH_SIZE (8*1024*1024)
// LED: IOMUXC_GPIO_03_GPIOMUX_IO03
#define LED_PORT BOARD_INITPINS_USER_LED_PERIPHERAL
#define LED_PIN BOARD_INITPINS_USER_LED_CHANNEL
#define LED_STATE_ON 1
// D8 as button: GPIO8
#define BUTTON_PORT BOARD_INITPINS_USER_BUTTON_PERIPHERAL
#define BUTTON_PIN BOARD_INITPINS_USER_BUTTON_CHANNEL
#define BUTTON_STATE_ACTIVE 0
// UART: IOMUXC_GPIO_09_LPUART1_RXD, IOMUXC_GPIO_10_LPUART1_TXD
#define UART_PORT LPUART1
#define UART_CLK_ROOT BOARD_BOOTCLOCKRUN_UART_CLK_ROOT
static inline void BOARD_ConfigMPU(void) {
}
#endif

17
managed_components/espressif__tinyusb/hw/bsp/imxrt/boards/metro_m7_1011_sd/board.mk Normal file
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CFLAGS += -DCPU_MIMXRT1011DAE5A -DCFG_EXAMPLE_VIDEO_READONLY
MCU_VARIANT = MIMXRT1011
# LD file with uf2
LD_FILE = $(BOARD_PATH)/$(BOARD).ld
# For flash-jlink target
JLINK_DEVICE = MIMXRT1011xxx5A
# For flash-pyocd target
PYOCD_TARGET = mimxrt1010
# flash using pyocd
flash: flash-uf2
flash-uf2: $(BUILD)/$(PROJECT).uf2
@echo copying $<
@$(CP) $< /media/$(USER)/METROM7BOOT

340
managed_components/espressif__tinyusb/hw/bsp/imxrt/boards/metro_m7_1011_sd/board/clock_config.c Normal file
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/*
* How to setup clock using clock driver functions:
*
* 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock.
*
* 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock.
*
* 3. Call CLOCK_SetMux() to configure corresponding clock source for target clock out.
*
* 4. Call CLOCK_SetDiv() to configure corresponding clock divider for target clock out.
*
* 5. Call CLOCK_SetXtalFreq() to set XTAL frequency based on board settings.
*
*/
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!GlobalInfo
product: Clocks v11.0
processor: MIMXRT1011xxxxx
package_id: MIMXRT1011DAE5A
mcu_data: ksdk2_0
processor_version: 13.0.2
board: MIMXRT1010-EVK
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
#include "clock_config.h"
#include "fsl_iomuxc.h"
/*******************************************************************************
* Definitions
******************************************************************************/
/*******************************************************************************
* Variables
******************************************************************************/
/*******************************************************************************
************************ BOARD_InitBootClocks function ************************
******************************************************************************/
void BOARD_InitBootClocks(void)
{
BOARD_BootClockRUN();
}
/*******************************************************************************
********************** Configuration BOARD_BootClockRUN ***********************
******************************************************************************/
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!Configuration
name: BOARD_BootClockRUN
called_from_default_init: true
outputs:
- {id: ADC_ALT_CLK.outFreq, value: 40 MHz}
- {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz}
- {id: CLK_1M.outFreq, value: 1 MHz}
- {id: CLK_24M.outFreq, value: 24 MHz}
- {id: CORE_CLK_ROOT.outFreq, value: 500 MHz}
- {id: ENET_500M_REF_CLK.outFreq, value: 500 MHz}
- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz}
- {id: FLEXSPI_CLK_ROOT.outFreq, value: 132 MHz}
- {id: GPT1_ipg_clk_highfreq.outFreq, value: 62.5 MHz}
- {id: GPT2_ipg_clk_highfreq.outFreq, value: 62.5 MHz}
- {id: IPG_CLK_ROOT.outFreq, value: 125 MHz}
- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz}
- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz}
- {id: MQS_MCLK.outFreq, value: 1080/17 MHz}
- {id: PERCLK_CLK_ROOT.outFreq, value: 62.5 MHz}
- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz}
- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz}
- {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz}
- {id: SAI1_MCLK3.outFreq, value: 30 MHz}
- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz}
- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz}
- {id: SAI3_MCLK3.outFreq, value: 30 MHz}
- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz}
- {id: TRACE_CLK_ROOT.outFreq, value: 132 MHz}
- {id: UART_CLK_ROOT.outFreq, value: 80 MHz}
- {id: USBPHY_CLK.outFreq, value: 480 MHz}
settings:
- {id: CCM.ADC_ACLK_PODF.scale, value: '12', locked: true}
- {id: CCM.AHB_PODF.scale, value: '1', locked: true}
- {id: CCM.FLEXSPI_PODF.scale, value: '4', locked: true}
- {id: CCM.IPG_PODF.scale, value: '4'}
- {id: CCM.LPSPI_PODF.scale, value: '5'}
- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true}
- {id: CCM.PRE_PERIPH_CLK_SEL.sel, value: CCM_ANALOG.ENET_500M_REF_CLK}
- {id: CCM.SAI1_CLK_SEL.sel, value: CCM_ANALOG.PLL3_PFD2_CLK}
- {id: CCM.SAI3_CLK_SEL.sel, value: CCM_ANALOG.PLL3_PFD2_CLK}
- {id: CCM.TRACE_CLK_SEL.sel, value: CCM_ANALOG.PLL2_MAIN_CLK}
- {id: CCM_ANALOG.PLL2.denom, value: '1'}
- {id: CCM_ANALOG.PLL2.num, value: '0'}
- {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK}
- {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0}
- {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1}
- {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2}
- {id: CCM_ANALOG.PLL2_PFD2_DIV.scale, value: '18', locked: true}
- {id: CCM_ANALOG.PLL2_PFD2_MUL.scale, value: '18', locked: true}
- {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3}
- {id: CCM_ANALOG.PLL2_PFD3_DIV.scale, value: '18', locked: true}
- {id: CCM_ANALOG.PLL2_PFD3_MUL.scale, value: '18', locked: true}
- {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3}
- {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0}
- {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '22', locked: true}
- {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true}
- {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1}
- {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2}
- {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3}
- {id: CCM_ANALOG.PLL3_PFD3_DIV.scale, value: '18', locked: true}
- {id: CCM_ANALOG.PLL3_PFD3_MUL.scale, value: '18', locked: true}
- {id: CCM_ANALOG.PLL6_BYPASS.sel, value: CCM_ANALOG.PLL6}
- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_CFG, value: Enabled}
- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_OUT_CFG, value: Enabled}
- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'}
sources:
- {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/*******************************************************************************
* Variables for BOARD_BootClockRUN configuration
******************************************************************************/
const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN =
{
.loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */
.numerator = 0, /* 30 bit numerator of fractional loop divider */
.denominator = 1, /* 30 bit denominator of fractional loop divider */
.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
};
const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN =
{
.loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */
.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
};
const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN =
{
.enableClkOutput500M = true, /* Enable the PLL providing the ENET 500MHz reference clock */
.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
};
/*******************************************************************************
* Code for BOARD_BootClockRUN configuration
******************************************************************************/
void BOARD_BootClockRUN(void)
{
/* Init RTC OSC clock frequency. */
CLOCK_SetRtcXtalFreq(32768U);
/* Enable 1MHz clock output. */
XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK;
/* Use free 1MHz clock output. */
XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK;
/* Set XTAL 24MHz clock frequency. */
CLOCK_SetXtalFreq(24000000U);
/* Enable XTAL 24MHz clock source. */
CLOCK_InitExternalClk(0);
/* Enable internal RC. */
CLOCK_InitRcOsc24M();
/* Switch clock source to external OSC. */
CLOCK_SwitchOsc(kCLOCK_XtalOsc);
/* Set Oscillator ready counter value. */
CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127);
/* Setting the VDD_SOC to 1.25V. It is necessary to config CORE to 500Mhz. */
DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x12);
/* Waiting for DCDC_STS_DC_OK bit is asserted */
while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0))
{
}
/* Disable IPG clock gate. */
CLOCK_DisableClock(kCLOCK_Adc1);
CLOCK_DisableClock(kCLOCK_Xbar1);
/* Set IPG_PODF. */
CLOCK_SetDiv(kCLOCK_IpgDiv, 3);
/* Init Enet PLL. */
CLOCK_InitEnetPll(&enetPllConfig_BOARD_BootClockRUN);
/* Disable PERCLK clock gate. */
CLOCK_DisableClock(kCLOCK_Gpt1);
CLOCK_DisableClock(kCLOCK_Gpt1S);
CLOCK_DisableClock(kCLOCK_Gpt2);
CLOCK_DisableClock(kCLOCK_Gpt2S);
CLOCK_DisableClock(kCLOCK_Pit);
/* Set PERCLK_PODF. */
CLOCK_SetDiv(kCLOCK_PerclkDiv, 1);
/* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
* With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
* Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
/* Disable Flexspi clock gate. */
CLOCK_DisableClock(kCLOCK_FlexSpi);
/* Set FLEXSPI_PODF. */
CLOCK_SetDiv(kCLOCK_FlexspiDiv, 3);
/* Set Flexspi clock source. */
CLOCK_SetMux(kCLOCK_FlexspiMux, 0);
CLOCK_SetMux(kCLOCK_FlexspiSrcMux, 0);
#endif
/* Disable ADC_ACLK_EN clock gate. */
CCM->CSCMR2 &= ~CCM_CSCMR2_ADC_ACLK_EN_MASK;
/* Set ADC_ACLK_PODF. */
CLOCK_SetDiv(kCLOCK_AdcDiv, 11);
/* Disable LPSPI clock gate. */
CLOCK_DisableClock(kCLOCK_Lpspi1);
CLOCK_DisableClock(kCLOCK_Lpspi2);
/* Set LPSPI_PODF. */
CLOCK_SetDiv(kCLOCK_LpspiDiv, 4);
/* Set Lpspi clock source. */
CLOCK_SetMux(kCLOCK_LpspiMux, 2);
/* Disable TRACE clock gate. */
CLOCK_DisableClock(kCLOCK_Trace);
/* Set TRACE_PODF. */
CLOCK_SetDiv(kCLOCK_TraceDiv, 3);
/* Set Trace clock source. */
CLOCK_SetMux(kCLOCK_TraceMux, 0);
/* Disable SAI1 clock gate. */
CLOCK_DisableClock(kCLOCK_Sai1);
/* Set SAI1_CLK_PRED. */
CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3);
/* Set SAI1_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_Sai1Div, 1);
/* Set Sai1 clock source. */
CLOCK_SetMux(kCLOCK_Sai1Mux, 0);
/* Disable SAI3 clock gate. */
CLOCK_DisableClock(kCLOCK_Sai3);
/* Set SAI3_CLK_PRED. */
CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3);
/* Set SAI3_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_Sai3Div, 1);
/* Set Sai3 clock source. */
CLOCK_SetMux(kCLOCK_Sai3Mux, 0);
/* Disable Lpi2c clock gate. */
CLOCK_DisableClock(kCLOCK_Lpi2c1);
CLOCK_DisableClock(kCLOCK_Lpi2c2);
/* Set LPI2C_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0);
/* Set Lpi2c clock source. */
CLOCK_SetMux(kCLOCK_Lpi2cMux, 0);
/* Disable UART clock gate. */
CLOCK_DisableClock(kCLOCK_Lpuart1);
CLOCK_DisableClock(kCLOCK_Lpuart2);
CLOCK_DisableClock(kCLOCK_Lpuart3);
CLOCK_DisableClock(kCLOCK_Lpuart4);
/* Set UART_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_UartDiv, 0);
/* Set Uart clock source. */
CLOCK_SetMux(kCLOCK_UartMux, 0);
/* Disable SPDIF clock gate. */
CLOCK_DisableClock(kCLOCK_Spdif);
/* Set SPDIF0_CLK_PRED. */
CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1);
/* Set SPDIF0_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_Spdif0Div, 7);
/* Set Spdif clock source. */
CLOCK_SetMux(kCLOCK_SpdifMux, 3);
/* Disable Flexio1 clock gate. */
CLOCK_DisableClock(kCLOCK_Flexio1);
/* Set FLEXIO1_CLK_PRED. */
CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1);
/* Set FLEXIO1_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_Flexio1Div, 7);
/* Set Flexio1 clock source. */
CLOCK_SetMux(kCLOCK_Flexio1Mux, 3);
/* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
* With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
* Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
/* Init Usb1 PLL. */
CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN);
/* Init Usb1 pfd0. */
CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 22);
/* Init Usb1 pfd1. */
CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16);
/* Init Usb1 pfd2. */
CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17);
/* Init Usb1 pfd3. */
CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 18);
#endif
/* Set periph clock source to use the USB1 PLL output (PLL3_SW_CLK) temporarily. */
/* Set Pll3 SW clock source to use the USB1 PLL output. */
CLOCK_SetMux(kCLOCK_Pll3SwMux, 0);
/* Set safe value of the AHB_PODF. */
CLOCK_SetDiv(kCLOCK_AhbDiv, 1);
/* Set periph clock2 clock source to use the PLL3_SW_CLK. */
CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
/* Set peripheral clock source (glitchless mux) to select the temporary core clock. */
CLOCK_SetMux(kCLOCK_PeriphMux, 1);
/* Set per clock source. */
CLOCK_SetMux(kCLOCK_PerclkMux, 0);
/* Init System PLL. */
CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN);
/* Init System pfd0. */
CLOCK_InitSysPfd(kCLOCK_Pfd0, 27);
/* Init System pfd1. */
CLOCK_InitSysPfd(kCLOCK_Pfd1, 16);
/* Init System pfd2. */
CLOCK_InitSysPfd(kCLOCK_Pfd2, 18);
/* Init System pfd3. */
CLOCK_InitSysPfd(kCLOCK_Pfd3, 18);
/* DeInit Audio PLL. */
CLOCK_DeinitAudioPll();
/* Bypass Audio PLL. */
CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1);
/* Set divider for Audio PLL. */
CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK;
CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK;
/* Enable Audio PLL output. */
CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK;
/* Set preperiph clock source. */
CLOCK_SetMux(kCLOCK_PrePeriphMux, 3);
/* Set periph clock source. */
CLOCK_SetMux(kCLOCK_PeriphMux, 0);
/* Set periph clock2 clock source. */
CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
/* Set AHB_PODF. */
CLOCK_SetDiv(kCLOCK_AhbDiv, 0);
/* Set clock out1 divider. */
CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0);
/* Set clock out1 source. */
CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1);
/* Set clock out2 divider. */
CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0);
/* Set clock out2 source. */
CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(18);
/* Set clock out1 drives clock out1. */
CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK;
/* Disable clock out1. */
CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK;
/* Disable clock out2. */
CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK;
/* Set SAI1 MCLK1 clock source. */
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0);
/* Set SAI1 MCLK2 clock source. */
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0);
/* Set SAI1 MCLK3 clock source. */
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0);
/* Set SAI3 MCLK3 clock source. */
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
/* Set MQS configuration. */
IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0);
/* Set GPT1 High frequency reference clock source. */
IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK;
/* Set GPT2 High frequency reference clock source. */
IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK;
/* Set SystemCoreClock variable. */
SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
}

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#ifndef _CLOCK_CONFIG_H_
#define _CLOCK_CONFIG_H_
#include "fsl_common.h"
/*******************************************************************************
* Definitions
******************************************************************************/
#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */
#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */
/*******************************************************************************
************************ BOARD_InitBootClocks function ************************
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/
/*!
* @brief This function executes default configuration of clocks.
*
*/
void BOARD_InitBootClocks(void);
#if defined(__cplusplus)
}
#endif /* __cplusplus*/
/*******************************************************************************
********************** Configuration BOARD_BootClockRUN ***********************
******************************************************************************/
/*******************************************************************************
* Definitions for BOARD_BootClockRUN configuration
******************************************************************************/
#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 500000000U /*!< Core clock frequency: 500000000Hz */
/* Clock outputs (values are in Hz): */
#define BOARD_BOOTCLOCKRUN_ADC_ALT_CLK 40000000UL
#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL
#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL
#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL
#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL
#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL
#define BOARD_BOOTCLOCKRUN_CORE_CLK_ROOT 500000000UL
#define BOARD_BOOTCLOCKRUN_ENET_500M_REF_CLK 500000000UL
#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL
#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 132000000UL
#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 62500000UL
#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 62500000UL
#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 125000000UL
#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL
#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL
#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL
#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 62500000UL
#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL
#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL
#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL
#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL
#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 132000000UL
#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL
#define BOARD_BOOTCLOCKRUN_USBPHY_CLK 480000000UL
/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration.
*/
extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN;
/*! @brief Sys PLL for BOARD_BootClockRUN configuration.
*/
extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN;
/*! @brief Enet PLL set for BOARD_BootClockRUN configuration.
*/
extern const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN;
/*******************************************************************************
* API for BOARD_BootClockRUN configuration
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/
/*!
* @brief This function executes configuration of clocks.
*
*/
void BOARD_BootClockRUN(void);
#if defined(__cplusplus)
}
#endif /* __cplusplus*/
#endif /* _CLOCK_CONFIG_H_ */

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/***********************************************************************************************************************
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
**********************************************************************************************************************/
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!GlobalInfo
product: Pins v13.1
processor: MIMXRT1011xxxxx
package_id: MIMXRT1011DAE5A
mcu_data: ksdk2_0
processor_version: 13.0.2
board: MIMXRT1010-EVK
external_user_signals: {}
pin_labels:
- {pin_num: '1', pin_signal: GPIO_11, label: GPIO_11, identifier: GPIO_11}
- {pin_num: '70', pin_signal: GPIO_SD_05}
- {pin_num: '10', pin_signal: GPIO_03, label: 'SAI1_RXD0/U10[16]', identifier: LED;USER_LED}
- {pin_num: '4', pin_signal: GPIO_08, label: 'SAI1_MCLK/U10[11]', identifier: USER_BUTTON}
- {pin_num: '79', pin_signal: GPIO_13, label: 'USB_OTG1_ID/J9[4]/Q9[2]', identifier: TRACE1}
power_domains: {NVCC_GPIO: '3.3'}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
#include "fsl_common.h"
#include "fsl_iomuxc.h"
#include "fsl_gpio.h"
#include "pin_mux.h"
/* FUNCTION ************************************************************************************************************
*
* Function Name : BOARD_InitBootPins
* Description : Calls initialization functions.
*
* END ****************************************************************************************************************/
void BOARD_InitBootPins(void) {
BOARD_InitPins();
}
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
BOARD_InitPins:
- options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'}
- pin_list:
- {pin_num: '3', peripheral: LPUART1, signal: RXD, pin_signal: GPIO_09}
- {pin_num: '2', peripheral: LPUART1, signal: TXD, pin_signal: GPIO_10}
- {pin_num: '10', peripheral: GPIO1, signal: 'gpiomux_io, 03', pin_signal: GPIO_03, identifier: USER_LED, direction: OUTPUT}
- {pin_num: '79', peripheral: ARM, signal: 'TRACE, 1', pin_signal: GPIO_13, speed: MHZ_200}
- {pin_num: '80', peripheral: ARM, signal: 'TRACE, 2', pin_signal: GPIO_12, speed: MHZ_200}
- {pin_num: '58', peripheral: ARM, signal: arm_trace_clk, pin_signal: GPIO_AD_02, speed: MHZ_200}
- {pin_num: '1', peripheral: ARM, signal: 'TRACE, 3', pin_signal: GPIO_11, speed: MHZ_200}
- {pin_num: '60', peripheral: ARM, signal: 'TRACE, 0', pin_signal: GPIO_AD_00, speed: MHZ_200}
- {pin_num: '4', peripheral: GPIO1, signal: 'gpiomux_io, 08', pin_signal: GPIO_08, direction: INPUT, pull_keeper_select: Pull, pull_up_down_config: Pull_Up_100K_Ohm}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
/* FUNCTION ************************************************************************************************************
*
* Function Name : BOARD_InitPins
* Description : Configures pin routing and optionally pin electrical features.
*
* END ****************************************************************************************************************/
void BOARD_InitPins(void) {
CLOCK_EnableClock(kCLOCK_Iomuxc);
/* GPIO configuration of USER_LED on GPIO_03 (pin 10) */
gpio_pin_config_t USER_LED_config = {
.direction = kGPIO_DigitalOutput,
.outputLogic = 0U,
.interruptMode = kGPIO_NoIntmode
};
/* Initialize GPIO functionality on GPIO_03 (pin 10) */
GPIO_PinInit(GPIO1, 3U, &USER_LED_config);
/* GPIO configuration of USER_BUTTON on GPIO_08 (pin 4) */
gpio_pin_config_t USER_BUTTON_config = {
.direction = kGPIO_DigitalInput,
.outputLogic = 0U,
.interruptMode = kGPIO_NoIntmode
};
/* Initialize GPIO functionality on GPIO_08 (pin 4) */
GPIO_PinInit(GPIO1, 8U, &USER_BUTTON_config);
IOMUXC_SetPinMux(IOMUXC_GPIO_03_GPIOMUX_IO03, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_08_GPIOMUX_IO08, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_09_LPUART1_RXD, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_10_LPUART1_TXD, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_11_ARM_TRACE3, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_12_ARM_TRACE2, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_13_ARM_TRACE1, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_00_ARM_TRACE0, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_02_ARM_TRACE_CLK, 0U);
IOMUXC_GPR->GPR26 = ((IOMUXC_GPR->GPR26 &
(~(BOARD_INITPINS_IOMUXC_GPR_GPR26_GPIO_SEL_MASK)))
| IOMUXC_GPR_GPR26_GPIO_SEL(0x00U)
);
IOMUXC_SetPinConfig(IOMUXC_GPIO_08_GPIOMUX_IO08, 0xB0A0U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_11_ARM_TRACE3, 0x10E0U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_12_ARM_TRACE2, 0x10E0U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_13_ARM_TRACE1, 0x10E0U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_00_ARM_TRACE0, 0x10E0U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_02_ARM_TRACE_CLK, 0x10E0U);
}
/***********************************************************************************************************************
* EOF
**********************************************************************************************************************/

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/***********************************************************************************************************************
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
**********************************************************************************************************************/
#ifndef _PIN_MUX_H_
#define _PIN_MUX_H_
/***********************************************************************************************************************
* Definitions
**********************************************************************************************************************/
/*! @brief Direction type */
typedef enum _pin_mux_direction
{
kPIN_MUX_DirectionInput = 0U, /* Input direction */
kPIN_MUX_DirectionOutput = 1U, /* Output direction */
kPIN_MUX_DirectionInputOrOutput = 2U /* Input or output direction */
} pin_mux_direction_t;
/*!
* @addtogroup pin_mux
* @{
*/
/***********************************************************************************************************************
* API
**********************************************************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif
/*!
* @brief Calls initialization functions.
*
*/
void BOARD_InitBootPins(void);
#define BOARD_INITPINS_IOMUXC_GPR_GPR26_GPIO_SEL_MASK 0x08U /*!< Select GPIO1 or GPIO2: affected bits mask */
/* GPIO_09 (number 3), LPUART1_RXD/J56[2] */
/* Routed pin properties */
#define BOARD_INITPINS_UART1_RXD_PERIPHERAL LPUART1 /*!< Peripheral name */
#define BOARD_INITPINS_UART1_RXD_SIGNAL RXD /*!< Signal name */
/* GPIO_10 (number 2), LPUART1_TXD/J56[4] */
/* Routed pin properties */
#define BOARD_INITPINS_UART1_TXD_PERIPHERAL LPUART1 /*!< Peripheral name */
#define BOARD_INITPINS_UART1_TXD_SIGNAL TXD /*!< Signal name */
/* GPIO_03 (number 10), SAI1_RXD0/U10[16] */
/* Routed pin properties */
#define BOARD_INITPINS_USER_LED_PERIPHERAL GPIO1 /*!< Peripheral name */
#define BOARD_INITPINS_USER_LED_SIGNAL gpiomux_io /*!< Signal name */
#define BOARD_INITPINS_USER_LED_CHANNEL 3U /*!< Signal channel */
/* GPIO_13 (number 79), USB_OTG1_ID/J9[4]/Q9[2] */
/* Routed pin properties */
#define BOARD_INITPINS_TRACE1_PERIPHERAL ARM /*!< Peripheral name */
#define BOARD_INITPINS_TRACE1_SIGNAL TRACE /*!< Signal name */
#define BOARD_INITPINS_TRACE1_CHANNEL 1U /*!< Signal channel */
/* GPIO_12 (number 80), USB_OTG1_OC/U7[A2] */
/* Routed pin properties */
#define BOARD_INITPINS_USB_OTG1_OC_PERIPHERAL ARM /*!< Peripheral name */
#define BOARD_INITPINS_USB_OTG1_OC_SIGNAL TRACE /*!< Signal name */
#define BOARD_INITPINS_USB_OTG1_OC_CHANNEL 2U /*!< Signal channel */
/* GPIO_AD_02 (number 58), ADC12_2/J26[12]/J56[16] */
/* Routed pin properties */
#define BOARD_INITPINS_ADC12_2_PERIPHERAL ARM /*!< Peripheral name */
#define BOARD_INITPINS_ADC12_2_SIGNAL arm_trace_clk /*!< Signal name */
/* GPIO_11 (number 1), GPIO_11 */
/* Routed pin properties */
#define BOARD_INITPINS_GPIO_11_PERIPHERAL ARM /*!< Peripheral name */
#define BOARD_INITPINS_GPIO_11_SIGNAL TRACE /*!< Signal name */
#define BOARD_INITPINS_GPIO_11_CHANNEL 3U /*!< Signal channel */
/* GPIO_AD_00 (number 60), USB_OTG1_PWR */
/* Routed pin properties */
#define BOARD_INITPINS_USB_OTG1_PWR_PERIPHERAL ARM /*!< Peripheral name */
#define BOARD_INITPINS_USB_OTG1_PWR_SIGNAL TRACE /*!< Signal name */
#define BOARD_INITPINS_USB_OTG1_PWR_CHANNEL 0U /*!< Signal channel */
/* GPIO_08 (number 4), SAI1_MCLK/U10[11] */
/* Routed pin properties */
#define BOARD_INITPINS_USER_BUTTON_PERIPHERAL GPIO1 /*!< Peripheral name */
#define BOARD_INITPINS_USER_BUTTON_SIGNAL gpiomux_io /*!< Signal name */
#define BOARD_INITPINS_USER_BUTTON_CHANNEL 8U /*!< Signal channel */
/*!
* @brief Configures pin routing and optionally pin electrical features.
*
*/
void BOARD_InitPins(void);
#if defined(__cplusplus)
}
#endif
/*!
* @}
*/
#endif /* _PIN_MUX_H_ */
/***********************************************************************************************************************
* EOF
**********************************************************************************************************************/

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managed_components/espressif__tinyusb/hw/bsp/imxrt/boards/metro_m7_1011_sd/evkmimxrt1010_flexspi_nor_config.c Normal file
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/*
* Copyright 2019 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "evkmimxrt1010_flexspi_nor_config.h"
/* Component ID definition, used by tools. */
#ifndef FSL_COMPONENT_ID
#define FSL_COMPONENT_ID "platform.drivers.xip_board"
#endif
/*******************************************************************************
* Code
******************************************************************************/
#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
__attribute__((section(".boot_hdr.conf")))
#elif defined(__ICCARM__)
#pragma location = ".boot_hdr.conf"
#endif
const flexspi_nor_config_t qspiflash_config = {
.memConfig =
{
.tag = FLEXSPI_CFG_BLK_TAG,
.version = FLEXSPI_CFG_BLK_VERSION,
.readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad,
.csHoldTime = 3u,
.csSetupTime = 3u,
.sflashPadType = kSerialFlash_4Pads,
.serialClkFreq = kFlexSpiSerialClk_100MHz,
.sflashA1Size = 16u * 1024u * 1024u,
.lookupTable =
{
// Read LUTs
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 24),
FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04),
},
},
.pageSize = 256u,
.sectorSize = 4u * 1024u,
.blockSize = 64u * 1024u,
.isUniformBlockSize = false,
};
#endif /* XIP_BOOT_HEADER_ENABLE */

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/*
* Copyright 2019 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __EVKMIMXRT1011_FLEXSPI_NOR_CONFIG__
#define __EVKMIMXRT1011_FLEXSPI_NOR_CONFIG__
#include <stdint.h>
#include <stdbool.h>
#include "fsl_common.h"
/*! @name Driver version */
/*@{*/
/*! @brief XIP_BOARD driver version 2.0.0. */
#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
/*@}*/
/* FLEXSPI memory config block related definitions */
#define FLEXSPI_CFG_BLK_TAG (0x42464346UL) // ascii "FCFB" Big Endian
#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0
#define FLEXSPI_CFG_BLK_SIZE (512)
/* FLEXSPI Feature related definitions */
#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1
/* Lookup table related definitions */
#define CMD_INDEX_READ 0
#define CMD_INDEX_READSTATUS 1
#define CMD_INDEX_WRITEENABLE 2
#define CMD_INDEX_WRITE 4
#define CMD_LUT_SEQ_IDX_READ 0
#define CMD_LUT_SEQ_IDX_READSTATUS 1
#define CMD_LUT_SEQ_IDX_WRITEENABLE 3
#define CMD_LUT_SEQ_IDX_WRITE 9
#define CMD_SDR 0x01
#define CMD_DDR 0x21
#define RADDR_SDR 0x02
#define RADDR_DDR 0x22
#define CADDR_SDR 0x03
#define CADDR_DDR 0x23
#define MODE1_SDR 0x04
#define MODE1_DDR 0x24
#define MODE2_SDR 0x05
#define MODE2_DDR 0x25
#define MODE4_SDR 0x06
#define MODE4_DDR 0x26
#define MODE8_SDR 0x07
#define MODE8_DDR 0x27
#define WRITE_SDR 0x08
#define WRITE_DDR 0x28
#define READ_SDR 0x09
#define READ_DDR 0x29
#define LEARN_SDR 0x0A
#define LEARN_DDR 0x2A
#define DATSZ_SDR 0x0B
#define DATSZ_DDR 0x2B
#define DUMMY_SDR 0x0C
#define DUMMY_DDR 0x2C
#define DUMMY_RWDS_SDR 0x0D
#define DUMMY_RWDS_DDR 0x2D
#define JMP_ON_CS 0x1F
#define STOP 0
#define FLEXSPI_1PAD 0
#define FLEXSPI_2PAD 1
#define FLEXSPI_4PAD 2
#define FLEXSPI_8PAD 3
#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \
(FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \
FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))
//!@brief Definitions for FlexSPI Serial Clock Frequency
typedef enum _FlexSpiSerialClockFreq
{
kFlexSpiSerialClk_30MHz = 1,
kFlexSpiSerialClk_50MHz = 2,
kFlexSpiSerialClk_60MHz = 3,
kFlexSpiSerialClk_75MHz = 4,
kFlexSpiSerialClk_80MHz = 5,
kFlexSpiSerialClk_100MHz = 6,
kFlexSpiSerialClk_120MHz = 7,
kFlexSpiSerialClk_133MHz = 8,
} flexspi_serial_clk_freq_t;
//!@brief FlexSPI clock configuration type
enum
{
kFlexSpiClk_SDR, //!< Clock configure for SDR mode
kFlexSpiClk_DDR, //!< Clock configurat for DDR mode
};
//!@brief FlexSPI Read Sample Clock Source definition
typedef enum _FlashReadSampleClkSource
{
kFlexSPIReadSampleClk_LoopbackInternally = 0,
kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1,
kFlexSPIReadSampleClk_LoopbackFromSckPad = 2,
kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3,
} flexspi_read_sample_clk_t;
//!@brief Misc feature bit definitions
enum
{
kFlexSpiMiscOffset_DiffClkEnable = 0, //!< Bit for Differential clock enable
kFlexSpiMiscOffset_Ck2Enable = 1, //!< Bit for CK2 enable
kFlexSpiMiscOffset_ParallelEnable = 2, //!< Bit for Parallel mode enable
kFlexSpiMiscOffset_WordAddressableEnable = 3, //!< Bit for Word Addressable enable
kFlexSpiMiscOffset_SafeConfigFreqEnable = 4, //!< Bit for Safe Configuration Frequency enable
kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, //!< Bit for Pad setting override enable
kFlexSpiMiscOffset_DdrModeEnable = 6, //!< Bit for DDR clock confiuration indication.
};
//!@brief Flash Type Definition
enum
{
kFlexSpiDeviceType_SerialNOR = 1, //!< Flash devices are Serial NOR
kFlexSpiDeviceType_SerialNAND = 2, //!< Flash devices are Serial NAND
kFlexSpiDeviceType_SerialRAM = 3, //!< Flash devices are Serial RAM/HyperFLASH
kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND
kFlexSpiDeviceType_MCP_NOR_RAM = 0x13, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial RAMs
};
//!@brief Flash Pad Definitions
enum
{
kSerialFlash_1Pad = 1,
kSerialFlash_2Pads = 2,
kSerialFlash_4Pads = 4,
kSerialFlash_8Pads = 8,
};
//!@brief FlexSPI LUT Sequence structure
typedef struct _lut_sequence
{
uint8_t seqNum; //!< Sequence Number, valid number: 1-16
uint8_t seqId; //!< Sequence Index, valid number: 0-15
uint16_t reserved;
} flexspi_lut_seq_t;
//!@brief Flash Configuration Command Type
enum
{
kDeviceConfigCmdType_Generic, //!< Generic command, for example: configure dummy cycles, drive strength, etc
kDeviceConfigCmdType_QuadEnable, //!< Quad Enable command
kDeviceConfigCmdType_Spi2Xpi, //!< Switch from SPI to DPI/QPI/OPI mode
kDeviceConfigCmdType_Xpi2Spi, //!< Switch from DPI/QPI/OPI to SPI mode
kDeviceConfigCmdType_Spi2NoCmd, //!< Switch to 0-4-4/0-8-8 mode
kDeviceConfigCmdType_Reset, //!< Reset device command
};
//!@brief FlexSPI Memory Configuration Block
typedef struct _FlexSPIConfig
{
uint32_t tag; //!< [0x000-0x003] Tag, fixed value 0x42464346UL
uint32_t version; //!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix
uint32_t reserved0; //!< [0x008-0x00b] Reserved for future use
uint8_t readSampleClkSrc; //!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3
uint8_t csHoldTime; //!< [0x00d-0x00d] CS hold time, default value: 3
uint8_t csSetupTime; //!< [0x00e-0x00e] CS setup time, default value: 3
uint8_t columnAddressWidth; //!< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For
//! Serial NAND, need to refer to datasheet
uint8_t deviceModeCfgEnable; //!< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable
uint8_t deviceModeType; //!< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch,
//! Generic configuration, etc.
uint16_t waitTimeCfgCommands; //!< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for
//! DPI/QPI/OPI switch or reset command
flexspi_lut_seq_t deviceModeSeq; //!< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt
//! sequence number, [31:16] Reserved
uint32_t deviceModeArg; //!< [0x018-0x01b] Argument/Parameter for device configuration
uint8_t configCmdEnable; //!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable
uint8_t configModeType[3]; //!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe
flexspi_lut_seq_t
configCmdSeqs[3]; //!< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq
uint32_t reserved1; //!< [0x02c-0x02f] Reserved for future use
uint32_t configCmdArgs[3]; //!< [0x030-0x03b] Arguments/Parameters for device Configuration commands
uint32_t reserved2; //!< [0x03c-0x03f] Reserved for future use
uint32_t controllerMiscOption; //!< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more
//! details
uint8_t deviceType; //!< [0x044-0x044] Device Type: See Flash Type Definition for more details
uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal
uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequency, device specific definitions, See System Boot
//! Chapter for more details
uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot
//! be done using 1 LUT sequence, currently, only applicable to HyperFLASH
uint32_t reserved3[2]; //!< [0x048-0x04f] Reserved for future use
uint32_t sflashA1Size; //!< [0x050-0x053] Size of Flash connected to A1
uint32_t sflashA2Size; //!< [0x054-0x057] Size of Flash connected to A2
uint32_t sflashB1Size; //!< [0x058-0x05b] Size of Flash connected to B1
uint32_t sflashB2Size; //!< [0x05c-0x05f] Size of Flash connected to B2
uint32_t csPadSettingOverride; //!< [0x060-0x063] CS pad setting override value
uint32_t sclkPadSettingOverride; //!< [0x064-0x067] SCK pad setting override value
uint32_t dataPadSettingOverride; //!< [0x068-0x06b] data pad setting override value
uint32_t dqsPadSettingOverride; //!< [0x06c-0x06f] DQS pad setting override value
uint32_t timeoutInMs; //!< [0x070-0x073] Timeout threshold for read status command
uint32_t commandInterval; //!< [0x074-0x077] CS deselect interval between two commands
uint16_t dataValidTime[2]; //!< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns
uint16_t busyOffset; //!< [0x07c-0x07d] Busy offset, valid value: 0-31
uint16_t busyBitPolarity; //!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 -
//! busy flag is 0 when flash device is busy
uint32_t lookupTable[64]; //!< [0x080-0x17f] Lookup table holds Flash command sequences
flexspi_lut_seq_t lutCustomSeq[12]; //!< [0x180-0x1af] Customizable LUT Sequences
uint32_t reserved4[4]; //!< [0x1b0-0x1bf] Reserved for future use
} flexspi_mem_config_t;
/* */
#define NOR_CMD_INDEX_READ CMD_INDEX_READ //!< 0
#define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS //!< 1
#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE //!< 2
#define NOR_CMD_INDEX_ERASESECTOR 3 //!< 3
#define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE //!< 4
#define NOR_CMD_INDEX_CHIPERASE 5 //!< 5
#define NOR_CMD_INDEX_DUMMY 6 //!< 6
#define NOR_CMD_INDEX_ERASEBLOCK 7 //!< 7
#define NOR_CMD_LUT_SEQ_IDX_READ CMD_LUT_SEQ_IDX_READ //!< 0 READ LUT sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_READSTATUS \
CMD_LUT_SEQ_IDX_READSTATUS //!< 1 Read Status LUT sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \
2 //!< 2 Read status DPI/QPI/OPI sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE \
CMD_LUT_SEQ_IDX_WRITEENABLE //!< 3 Write Enable sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \
4 //!< 4 Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5 //!< 5 Erase Sector sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8 //!< 8 Erase Block sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM \
CMD_LUT_SEQ_IDX_WRITE //!< 9 Program sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11 //!< 11 Chip Erase sequence in lookupTable id stored in config block
#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13 //!< 13 Read SFDP sequence in lookupTable id stored in config block
#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \
14 //!< 14 Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \
15 //!< 15 Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config blobk
/*
* Serial NOR configuration block
*/
typedef struct _flexspi_nor_config
{
flexspi_mem_config_t memConfig; //!< Common memory configuration info via FlexSPI
uint32_t pageSize; //!< Page size of Serial NOR
uint32_t sectorSize; //!< Sector size of Serial NOR
uint8_t ipcmdSerialClkFreq; //!< Clock frequency for IP command
uint8_t isUniformBlockSize; //!< Sector/Block size is the same
uint8_t reserved0[2]; //!< Reserved for future use
uint8_t serialNorType; //!< Serial NOR Flash type: 0/1/2/3
uint8_t needExitNoCmdMode; //!< Need to exit NoCmd mode before other IP command
uint8_t halfClkForNonReadCmd; //!< Half the Serial Clock for non-read command: true/false
uint8_t needRestoreNoCmdMode; //!< Need to Restore NoCmd mode after IP command execution
uint32_t blockSize; //!< Block size
uint32_t reserve2[11]; //!< Reserved for future use
} flexspi_nor_config_t;
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __cplusplus
}
#endif
#endif /* __EVKMIMXRT1011_FLEXSPI_NOR_CONFIG__ */

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/*
** ###################################################################
** Processors: MIMXRT1011CAE4A
** MIMXRT1011DAE5A
**
** Compiler: GNU C Compiler
** Reference manual: IMXRT1010RM Rev.0, 09/2019
** Version: rev. 1.0, 2019-08-01
** Build: b210709
**
** Abstract:
** Linker file for the GNU C Compiler
**
** Copyright 2016 Freescale Semiconductor, Inc.
** Copyright 2016-2021 NXP
** All rights reserved.
**
** SPDX-License-Identifier: BSD-3-Clause
**
** http: www.nxp.com
** mail: support@nxp.com
**
** ###################################################################
*/
/* Entry Point */
ENTRY(Reset_Handler)
HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x00000400 : 0;
/* Specify the memory areas */
MEMORY
{
m_flash_config (RX) : ORIGIN = 0x60000400, LENGTH = 0x00000C00
m_ivt (RX) : ORIGIN = 0x60001000, LENGTH = 0x00001000
m_interrupts (RX) : ORIGIN = 0x6000C000, LENGTH = 0x00000400
m_text (RX) : ORIGIN = 0x6000C400, LENGTH = (8*1024*1024 - 0xC400)
m_qacode (RX) : ORIGIN = 0x00000000, LENGTH = 0x00008000
m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00008000
m_data2 (RW) : ORIGIN = 0x20200000, LENGTH = 0x00010000
}
/* Define output sections */
SECTIONS
{
__NCACHE_REGION_START = ORIGIN(m_data2);
__NCACHE_REGION_SIZE = 0;
.flash_config :
{
. = ALIGN(4);
__FLASH_BASE = .;
KEEP(* (.boot_hdr.conf)) /* flash config section */
. = ALIGN(4);
} > m_flash_config
ivt_begin = ORIGIN(m_flash_config) + LENGTH(m_flash_config);
.ivt : AT(ivt_begin)
{
. = ALIGN(4);
KEEP(* (.boot_hdr.ivt)) /* ivt section */
KEEP(* (.boot_hdr.boot_data)) /* boot section */
KEEP(* (.boot_hdr.dcd_data)) /* dcd section */
. = ALIGN(4);
} > m_ivt
/* The startup code goes first into internal RAM */
.interrupts :
{
__VECTOR_TABLE = .;
__Vectors = .;
. = ALIGN(4);
KEEP(*(.isr_vector)) /* Startup code */
. = ALIGN(4);
} > m_interrupts
/* The program code and other data goes into internal RAM */
.text :
{
. = ALIGN(4);
*(.text) /* .text sections (code) */
*(.text*) /* .text* sections (code) */
*(.rodata) /* .rodata sections (constants, strings, etc.) */
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
*(.glue_7) /* glue arm to thumb code */
*(.glue_7t) /* glue thumb to arm code */
*(.eh_frame)
KEEP (*(.init))
KEEP (*(.fini))
. = ALIGN(4);
} > m_text
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > m_text
.ARM :
{
__exidx_start = .;
*(.ARM.exidx*)
__exidx_end = .;
} > m_text
.ctors :
{
__CTOR_LIST__ = .;
/* gcc uses crtbegin.o to find the start of
the constructors, so we make sure it is
first. Because this is a wildcard, it
doesn't matter if the user does not
actually link against crtbegin.o; the
linker won't look for a file to match a
wildcard. The wildcard also means that it
doesn't matter which directory crtbegin.o
is in. */
KEEP (*crtbegin.o(.ctors))
KEEP (*crtbegin?.o(.ctors))
/* We don't want to include the .ctor section from
from the crtend.o file until after the sorted ctors.
The .ctor section from the crtend file contains the
end of ctors marker and it must be last */
KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
__CTOR_END__ = .;
} > m_text
.dtors :
{
__DTOR_LIST__ = .;
KEEP (*crtbegin.o(.dtors))
KEEP (*crtbegin?.o(.dtors))
KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
__DTOR_END__ = .;
} > m_text
.preinit_array :
{
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP (*(.preinit_array*))
PROVIDE_HIDDEN (__preinit_array_end = .);
} > m_text
.init_array :
{
PROVIDE_HIDDEN (__init_array_start = .);
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array*))
PROVIDE_HIDDEN (__init_array_end = .);
} > m_text
.fini_array :
{
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP (*(SORT(.fini_array.*)))
KEEP (*(.fini_array*))
PROVIDE_HIDDEN (__fini_array_end = .);
} > m_text
__etext = .; /* define a global symbol at end of code */
__DATA_ROM = .; /* Symbol is used by startup for data initialization */
.interrupts_ram :
{
. = ALIGN(4);
__VECTOR_RAM__ = .;
__interrupts_ram_start__ = .; /* Create a global symbol at data start */
*(.m_interrupts_ram) /* This is a user defined section */
. += VECTOR_RAM_SIZE;
. = ALIGN(4);
__interrupts_ram_end__ = .; /* Define a global symbol at data end */
} > m_data
__VECTOR_RAM = DEFINED(__ram_vector_table__) ? __VECTOR_RAM__ : ORIGIN(m_interrupts);
__RAM_VECTOR_TABLE_SIZE_BYTES = DEFINED(__ram_vector_table__) ? (__interrupts_ram_end__ - __interrupts_ram_start__) : 0x0;
.data : AT(__DATA_ROM)
{
. = ALIGN(4);
__DATA_RAM = .;
__data_start__ = .; /* create a global symbol at data start */
*(m_usb_dma_init_data)
*(.data) /* .data sections */
*(.data*) /* .data* sections */
*(DataQuickAccess) /* quick access data section */
KEEP(*(.jcr*))
. = ALIGN(4);
__data_end__ = .; /* define a global symbol at data end */
} > m_data
__ram_function_flash_start = __DATA_ROM + (__data_end__ - __data_start__); /* Symbol is used by startup for TCM data initialization */
.ram_function : AT(__ram_function_flash_start)
{
. = ALIGN(32);
__ram_function_start__ = .;
*(CodeQuickAccess)
. = ALIGN(128);
__ram_function_end__ = .;
} > m_qacode
__NDATA_ROM = __ram_function_flash_start + (__ram_function_end__ - __ram_function_start__);
.ncache.init : AT(__NDATA_ROM)
{
__noncachedata_start__ = .; /* create a global symbol at ncache data start */
*(NonCacheable.init)
. = ALIGN(4);
__noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
} > m_data
. = __noncachedata_init_end__;
.ncache :
{
*(NonCacheable)
. = ALIGN(4);
__noncachedata_end__ = .; /* define a global symbol at ncache data end */
} > m_data
__DATA_END = __NDATA_ROM + (__noncachedata_init_end__ - __noncachedata_start__);
text_end = ORIGIN(m_text) + LENGTH(m_text);
ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
/* Uninitialized data section */
.bss :
{
/* This is used by the startup in order to initialize the .bss section */
. = ALIGN(4);
__START_BSS = .;
__bss_start__ = .;
*(m_usb_dma_noninit_data)
*(.bss)
*(.bss*)
*(COMMON)
. = ALIGN(4);
__bss_end__ = .;
__END_BSS = .;
} > m_data
.heap :
{
. = ALIGN(8);
__end__ = .;
PROVIDE(end = .);
__HeapBase = .;
. += HEAP_SIZE;
__HeapLimit = .;
__heap_limit = .; /* Add for _sbrk */
} > m_data
.stack :
{
. = ALIGN(8);
. += STACK_SIZE;
} > m_data
/* Initializes stack on the end of block */
__StackTop = ORIGIN(m_data) + LENGTH(m_data);
__StackLimit = __StackTop - STACK_SIZE;
PROVIDE(__stack = __StackTop);
.ARM.attributes 0 : { *(.ARM.attributes) }
ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
}

431
managed_components/espressif__tinyusb/hw/bsp/imxrt/boards/metro_m7_1011_sd/metro_m7_1011_sd.mex Normal file
View File

@@ -0,0 +1,431 @@
<?xml version="1.0" encoding= "UTF-8" ?>
<configuration name="MIMXRT1010-EVK" xsi:schemaLocation="http://mcuxpresso.nxp.com/XSD/mex_configuration_13 http://mcuxpresso.nxp.com/XSD/mex_configuration_13.xsd" uuid="f341eb24-9521-4127-8932-81692aeb76df" version="13" xmlns="http://mcuxpresso.nxp.com/XSD/mex_configuration_13" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<common>
<processor>MIMXRT1011xxxxx</processor>
<package>MIMXRT1011DAE5A</package>
<board>MIMXRT1010-EVK</board>
<board_revision>A</board_revision>
<mcu_data>ksdk2_0</mcu_data>
<cores selected="core0">
<core name="Cortex-M7F" id="core0" description="M7 core"/>
</cores>
<description></description>
</common>
<preferences>
<validate_boot_init_only>true</validate_boot_init_only>
<generate_extended_information>false</generate_extended_information>
<generate_code_modified_registers_only>false</generate_code_modified_registers_only>
<update_include_paths>true</update_include_paths>
<generate_registers_defines>false</generate_registers_defines>
</preferences>
<tools>
<pins name="Pins" version="13.1" enabled="true" update_project_code="true">
<generated_project_files>
<file path="board/pin_mux.c" update_enabled="true"/>
<file path="board/pin_mux.h" update_enabled="true"/>
</generated_project_files>
<pins_profile>
<processor_version>13.0.2</processor_version>
<pin_labels>
<pin_label pin_num="1" pin_signal="GPIO_11" label="GPIO_11" identifier="GPIO_11"/>
<pin_label pin_num="70" pin_signal="GPIO_SD_05" label=""/>
<pin_label pin_num="10" pin_signal="GPIO_03" label="SAI1_RXD0/U10[16]" identifier="LED;USER_LED"/>
<pin_label pin_num="4" pin_signal="GPIO_08" label="SAI1_MCLK/U10[11]" identifier="USER_BUTTON"/>
<pin_label pin_num="79" pin_signal="GPIO_13" label="USB_OTG1_ID/J9[4]/Q9[2]" identifier="TRACE1"/>
</pin_labels>
<external_user_signals>
<properties/>
</external_user_signals>
<power_domains>
<power_domain name="NVCC_GPIO" value="3.3"/>
</power_domains>
</pins_profile>
<functions_list>
<function name="BOARD_InitPins">
<description>Configures pin routing and optionally pin electrical features.</description>
<options>
<callFromInitBoot>true</callFromInitBoot>
<coreID>core0</coreID>
<enableClock>true</enableClock>
</options>
<dependencies>
<dependency resourceType="Peripheral" resourceId="LPUART1" description="Peripheral LPUART1 is not initialized" problem_level="1" source="Pins:BOARD_InitPins">
<feature name="initialized" evaluation="equal">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="Peripheral" resourceId="ARM" description="Peripheral ARM is not initialized" problem_level="1" source="Pins:BOARD_InitPins">
<feature name="initialized" evaluation="equal">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="Peripheral" resourceId="GPIO1" description="Peripheral GPIO1 is not initialized" problem_level="1" source="Pins:BOARD_InitPins">
<feature name="initialized" evaluation="equal">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitPins">
<feature name="enabled" evaluation="equal" configuration="core0">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitPins">
<feature name="enabled" evaluation="equal" configuration="core0">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.igpio" description="Pins initialization requires the IGPIO Driver in the project." problem_level="2" source="Pins:BOARD_InitPins">
<feature name="enabled" evaluation="equal" configuration="core0">
<data>true</data>
</feature>
</dependency>
</dependencies>
<pins>
<pin peripheral="LPUART1" signal="RXD" pin_num="3" pin_signal="GPIO_09"/>
<pin peripheral="LPUART1" signal="TXD" pin_num="2" pin_signal="GPIO_10"/>
<pin peripheral="GPIO1" signal="gpiomux_io, 03" pin_num="10" pin_signal="GPIO_03">
<pin_features>
<pin_feature name="identifier" value="USER_LED"/>
<pin_feature name="direction" value="OUTPUT"/>
</pin_features>
</pin>
<pin peripheral="ARM" signal="TRACE, 1" pin_num="79" pin_signal="GPIO_13">
<pin_features>
<pin_feature name="speed" value="MHZ_200"/>
</pin_features>
</pin>
<pin peripheral="ARM" signal="TRACE, 2" pin_num="80" pin_signal="GPIO_12">
<pin_features>
<pin_feature name="speed" value="MHZ_200"/>
</pin_features>
</pin>
<pin peripheral="ARM" signal="arm_trace_clk" pin_num="58" pin_signal="GPIO_AD_02">
<pin_features>
<pin_feature name="speed" value="MHZ_200"/>
</pin_features>
</pin>
<pin peripheral="ARM" signal="TRACE, 3" pin_num="1" pin_signal="GPIO_11">
<pin_features>
<pin_feature name="speed" value="MHZ_200"/>
</pin_features>
</pin>
<pin peripheral="ARM" signal="TRACE, 0" pin_num="60" pin_signal="GPIO_AD_00">
<pin_features>
<pin_feature name="speed" value="MHZ_200"/>
</pin_features>
</pin>
<pin peripheral="GPIO1" signal="gpiomux_io, 08" pin_num="4" pin_signal="GPIO_08">
<pin_features>
<pin_feature name="direction" value="INPUT"/>
<pin_feature name="pull_keeper_select" value="Pull"/>
<pin_feature name="pull_up_down_config" value="Pull_Up_100K_Ohm"/>
</pin_features>
</pin>
</pins>
</function>
</functions_list>
</pins>
<clocks name="Clocks" version="11.0" enabled="true" update_project_code="true">
<generated_project_files>
<file path="board/clock_config.c" update_enabled="true"/>
<file path="board/clock_config.h" update_enabled="true"/>
</generated_project_files>
<clocks_profile>
<processor_version>13.0.2</processor_version>
</clocks_profile>
<clock_configurations>
<clock_configuration name="BOARD_BootClockRUN" id_prefix="" prefix_user_defined="false">
<description></description>
<options/>
<dependencies>
<dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtali" description="&apos;RTC_XTALI&apos; (Pins tool id: XTALOSC24M.rtc_xtali, Clocks tool id: XTALOSC24M.RTC_XTALI) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
<feature name="routed" evaluation="">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtali" description="&apos;RTC_XTALI&apos; (Pins tool id: XTALOSC24M.rtc_xtali, Clocks tool id: XTALOSC24M.RTC_XTALI) needs to have &apos;INPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
<feature name="direction" evaluation="">
<data>INPUT</data>
</feature>
</dependency>
<dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtalo" description="&apos;RTC_XTALO&apos; (Pins tool id: XTALOSC24M.rtc_xtalo, Clocks tool id: XTALOSC24M.RTC_XTALO) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
<feature name="routed" evaluation="">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtalo" description="&apos;RTC_XTALO&apos; (Pins tool id: XTALOSC24M.rtc_xtalo, Clocks tool id: XTALOSC24M.RTC_XTALO) needs to have &apos;OUTPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
<feature name="direction" evaluation="">
<data>OUTPUT</data>
</feature>
</dependency>
<dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtali" description="&apos;XTALI&apos; (Pins tool id: XTALOSC24M.xtali, Clocks tool id: XTALOSC24M.XTALI) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
<feature name="routed" evaluation="">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtali" description="&apos;XTALI&apos; (Pins tool id: XTALOSC24M.xtali, Clocks tool id: XTALOSC24M.XTALI) needs to have &apos;INPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
<feature name="direction" evaluation="">
<data>INPUT</data>
</feature>
</dependency>
<dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtalo" description="&apos;XTALO&apos; (Pins tool id: XTALOSC24M.xtalo, Clocks tool id: XTALOSC24M.XTALO) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
<feature name="routed" evaluation="">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtalo" description="&apos;XTALO&apos; (Pins tool id: XTALOSC24M.xtalo, Clocks tool id: XTALOSC24M.XTALO) needs to have &apos;OUTPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
<feature name="direction" evaluation="">
<data>OUTPUT</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN">
<feature name="enabled" evaluation="equal" configuration="core0">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Clocks initialization requires the IOMUXC Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN">
<feature name="enabled" evaluation="equal" configuration="core0">
<data>true</data>
</feature>
</dependency>
</dependencies>
<clock_sources>
<clock_source id="XTALOSC24M.RTC_OSC.outFreq" value="32.768 kHz" locked="false" enabled="true"/>
</clock_sources>
<clock_outputs>
<clock_output id="ADC_ALT_CLK.outFreq" value="40 MHz" locked="false" accuracy=""/>
<clock_output id="CKIL_SYNC_CLK_ROOT.outFreq" value="32.768 kHz" locked="false" accuracy=""/>
<clock_output id="CLK_1M.outFreq" value="1 MHz" locked="false" accuracy=""/>
<clock_output id="CLK_24M.outFreq" value="24 MHz" locked="false" accuracy=""/>
<clock_output id="CORE_CLK_ROOT.outFreq" value="500 MHz" locked="false" accuracy=""/>
<clock_output id="ENET_500M_REF_CLK.outFreq" value="500 MHz" locked="false" accuracy=""/>
<clock_output id="FLEXIO1_CLK_ROOT.outFreq" value="30 MHz" locked="false" accuracy=""/>
<clock_output id="FLEXSPI_CLK_ROOT.outFreq" value="132 MHz" locked="false" accuracy=""/>
<clock_output id="GPT1_ipg_clk_highfreq.outFreq" value="62.5 MHz" locked="false" accuracy=""/>
<clock_output id="GPT2_ipg_clk_highfreq.outFreq" value="62.5 MHz" locked="false" accuracy=""/>
<clock_output id="IPG_CLK_ROOT.outFreq" value="125 MHz" locked="false" accuracy=""/>
<clock_output id="LPI2C_CLK_ROOT.outFreq" value="60 MHz" locked="false" accuracy=""/>
<clock_output id="LPSPI_CLK_ROOT.outFreq" value="105.6 MHz" locked="false" accuracy=""/>
<clock_output id="MQS_MCLK.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
<clock_output id="PERCLK_CLK_ROOT.outFreq" value="62.5 MHz" locked="false" accuracy=""/>
<clock_output id="SAI1_CLK_ROOT.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
<clock_output id="SAI1_MCLK1.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
<clock_output id="SAI1_MCLK2.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
<clock_output id="SAI1_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/>
<clock_output id="SAI3_CLK_ROOT.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
<clock_output id="SAI3_MCLK1.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
<clock_output id="SAI3_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/>
<clock_output id="SPDIF0_CLK_ROOT.outFreq" value="30 MHz" locked="false" accuracy=""/>
<clock_output id="TRACE_CLK_ROOT.outFreq" value="132 MHz" locked="false" accuracy=""/>
<clock_output id="UART_CLK_ROOT.outFreq" value="80 MHz" locked="false" accuracy=""/>
<clock_output id="USBPHY_CLK.outFreq" value="480 MHz" locked="false" accuracy=""/>
</clock_outputs>
<clock_settings>
<setting id="CCM.ADC_ACLK_PODF.scale" value="12" locked="true"/>
<setting id="CCM.AHB_PODF.scale" value="1" locked="true"/>
<setting id="CCM.FLEXSPI_PODF.scale" value="4" locked="true"/>
<setting id="CCM.IPG_PODF.scale" value="4" locked="false"/>
<setting id="CCM.LPSPI_PODF.scale" value="5" locked="false"/>
<setting id="CCM.PERCLK_PODF.scale" value="2" locked="true"/>
<setting id="CCM.PRE_PERIPH_CLK_SEL.sel" value="CCM_ANALOG.ENET_500M_REF_CLK" locked="false"/>
<setting id="CCM.SAI1_CLK_SEL.sel" value="CCM_ANALOG.PLL3_PFD2_CLK" locked="false"/>
<setting id="CCM.SAI3_CLK_SEL.sel" value="CCM_ANALOG.PLL3_PFD2_CLK" locked="false"/>
<setting id="CCM.TRACE_CLK_SEL.sel" value="CCM_ANALOG.PLL2_MAIN_CLK" locked="false"/>
<setting id="CCM_ANALOG.PLL2.denom" value="1" locked="false"/>
<setting id="CCM_ANALOG.PLL2.num" value="0" locked="false"/>
<setting id="CCM_ANALOG.PLL2_BYPASS.sel" value="CCM_ANALOG.PLL2_OUT_CLK" locked="false"/>
<setting id="CCM_ANALOG.PLL2_PFD0_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD0" locked="false"/>
<setting id="CCM_ANALOG.PLL2_PFD1_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD1" locked="false"/>
<setting id="CCM_ANALOG.PLL2_PFD2_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD2" locked="false"/>
<setting id="CCM_ANALOG.PLL2_PFD2_DIV.scale" value="18" locked="true"/>
<setting id="CCM_ANALOG.PLL2_PFD2_MUL.scale" value="18" locked="true"/>
<setting id="CCM_ANALOG.PLL2_PFD3_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD3" locked="false"/>
<setting id="CCM_ANALOG.PLL2_PFD3_DIV.scale" value="18" locked="true"/>
<setting id="CCM_ANALOG.PLL2_PFD3_MUL.scale" value="18" locked="true"/>
<setting id="CCM_ANALOG.PLL3_BYPASS.sel" value="CCM_ANALOG.PLL3" locked="false"/>
<setting id="CCM_ANALOG.PLL3_PFD0_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD0" locked="false"/>
<setting id="CCM_ANALOG.PLL3_PFD0_DIV.scale" value="22" locked="true"/>
<setting id="CCM_ANALOG.PLL3_PFD0_MUL.scale" value="18" locked="true"/>
<setting id="CCM_ANALOG.PLL3_PFD1_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD1" locked="false"/>
<setting id="CCM_ANALOG.PLL3_PFD2_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD2" locked="false"/>
<setting id="CCM_ANALOG.PLL3_PFD3_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD3" locked="false"/>
<setting id="CCM_ANALOG.PLL3_PFD3_DIV.scale" value="18" locked="true"/>
<setting id="CCM_ANALOG.PLL3_PFD3_MUL.scale" value="18" locked="true"/>
<setting id="CCM_ANALOG.PLL6_BYPASS.sel" value="CCM_ANALOG.PLL6" locked="false"/>
<setting id="CCM_ANALOG_PLL_USB1_EN_USB_CLKS_CFG" value="Enabled" locked="false"/>
<setting id="CCM_ANALOG_PLL_USB1_EN_USB_CLKS_OUT_CFG" value="Enabled" locked="false"/>
<setting id="CCM_ANALOG_PLL_USB1_POWER_CFG" value="Yes" locked="false"/>
</clock_settings>
<called_from_default_init>true</called_from_default_init>
</clock_configuration>
</clock_configurations>
</clocks>
<dcdx name="DCDx" version="2.0" enabled="false" update_project_code="true">
<generated_project_files/>
<dcdx_profile>
<processor_version>0.0.0</processor_version>
</dcdx_profile>
<dcdx_configurations/>
</dcdx>
<periphs name="Peripherals" version="12.0" enabled="false" update_project_code="true">
<generated_project_files/>
<peripherals_profile>
<processor_version>13.0.2</processor_version>
</peripherals_profile>
<functional_groups>
<functional_group name="BOARD_InitPeripherals" uuid="5e519eed-bd94-4950-84de-0f29de85bcea" called_from_default_init="true" id_prefix="" core="core0">
<description></description>
<options/>
<dependencies/>
<instances>
<instance name="COMBO_SENSOR" uuid="2342e373-ea2e-4bed-8aa4-bd33509155f6" type="lpi2c" type_id="lpi2c_6b71962515c3208facfccd030afebc98" mode="master" peripheral="LPI2C1" enabled="false" comment="" custom_name_enabled="true" editing_lock="false">
<config_set name="main" quick_selection="qs_interrupt">
<setting name="clockSource" value="Lpi2cClock"/>
<setting name="clockSourceFreq" value="BOARD_BootClockRUN"/>
</config_set>
<config_set name="interrupt_vector"/>
<config_set name="master" quick_selection="qs_master_transfer">
<setting name="mode" value="transfer"/>
<struct name="config">
<setting name="enableMaster" value="true"/>
<setting name="enableDoze" value="true"/>
<setting name="debugEnable" value="false"/>
<setting name="ignoreAck" value="false"/>
<setting name="pinConfig" value="kLPI2C_2PinOpenDrain"/>
<setting name="baudRate_Hz" value="100000"/>
<setting name="busIdleTimeout_ns" value="0"/>
<setting name="pinLowTimeout_ns" value="0"/>
<setting name="sdaGlitchFilterWidth_ns" value="0"/>
<setting name="sclGlitchFilterWidth_ns" value="0"/>
<struct name="hostRequest">
<setting name="enable" value="false"/>
<setting name="source" value="kLPI2C_HostRequestExternalPin"/>
<setting name="polarity" value="kLPI2C_HostRequestPinActiveHigh"/>
</struct>
<set name="edmaRequestSources">
<selected/>
</set>
</struct>
<struct name="transfer">
<setting name="blocking" value="false"/>
<setting name="enable_custom_handle" value="false"/>
<struct name="callback">
<setting name="name" value=""/>
<setting name="userData" value=""/>
</struct>
<set name="flags">
<selected/>
</set>
<setting name="slaveAddress" value="0"/>
<setting name="direction" value="kLPI2C_Write"/>
<setting name="subaddress" value="0"/>
<setting name="subaddressSize" value="1"/>
<setting name="blocking_buffer" value="false"/>
<setting name="enable_custom_buffer" value="false"/>
<setting name="dataSize" value="1"/>
</struct>
</config_set>
</instance>
<instance name="DEBUG_UART" uuid="0d9274fe-8f49-48a8-8e6a-8c3ac009384d" type="lpuart" type_id="lpuart_bf01db7d964092f3cf860852cba17f7e" mode="polling" peripheral="LPUART1" enabled="false" comment="" custom_name_enabled="true" editing_lock="false">
<config_set name="lpuartConfig_t" quick_selection="QuickSelection1">
<struct name="lpuartConfig">
<setting name="clockSource" value="LpuartClock"/>
<setting name="lpuartSrcClkFreq" value="ClocksTool_DefaultInit"/>
<setting name="baudRate_Bps" value="115200"/>
<setting name="parityMode" value="kLPUART_ParityDisabled"/>
<setting name="dataBitsCount" value="kLPUART_EightDataBits"/>
<setting name="isMsb" value="false"/>
<setting name="stopBitCount" value="kLPUART_OneStopBit"/>
<setting name="enableMatchAddress1" value="false"/>
<setting name="matchAddress1" value="0"/>
<setting name="enableMatchAddress2" value="false"/>
<setting name="matchAddress2" value="0"/>
<setting name="txFifoWatermark" value="0"/>
<setting name="rxFifoWatermark" value="1"/>
<setting name="enableRxRTS" value="false"/>
<setting name="enableTxCTS" value="false"/>
<setting name="txCtsSource" value="kLPUART_CtsSourcePin"/>
<setting name="txCtsConfig" value="kLPUART_CtsSampleAtStart"/>
<setting name="rxIdleType" value="kLPUART_IdleTypeStartBit"/>
<setting name="rxIdleConfig" value="kLPUART_IdleCharacter1"/>
<setting name="enableTx" value="true"/>
<setting name="enableRx" value="true"/>
</struct>
</config_set>
</instance>
<instance name="USER_BUTTON" uuid="6c9e57cc-d98c-4f6d-bf94-3920a8fd474e" type="igpio" type_id="igpio_b1c1fa279aa7069dca167502b8589cb7" mode="GPIO" peripheral="GPIO2" enabled="false" comment="" custom_name_enabled="true" editing_lock="false">
<config_set name="fsl_gpio">
<setting name="enable_irq_comb_0_15" value="false"/>
<struct name="gpio_interrupt_comb_0_15">
<setting name="IRQn" value="GPIO2_Combined_0_15_IRQn"/>
<setting name="enable_interrrupt" value="enabled"/>
<setting name="enable_priority" value="false"/>
<setting name="priority" value="0"/>
<setting name="enable_custom_name" value="false"/>
</struct>
</config_set>
</instance>
<instance name="USER_LED" uuid="0f7a142d-ad6c-4e47-a2a3-015e90afa37b" type="igpio" type_id="igpio_b1c1fa279aa7069dca167502b8589cb7" mode="GPIO" peripheral="GPIO1" enabled="false" comment="" custom_name_enabled="true" editing_lock="false">
<config_set name="fsl_gpio">
<setting name="enable_irq_comb_0_15" value="false"/>
<struct name="gpio_interrupt_comb_0_15">
<setting name="IRQn" value="GPIO1_Combined_0_15_IRQn"/>
<setting name="enable_interrrupt" value="enabled"/>
<setting name="enable_priority" value="false"/>
<setting name="priority" value="0"/>
<setting name="enable_custom_name" value="false"/>
</struct>
<setting name="enable_irq_comb_16_31" value="false"/>
<struct name="gpio_interrupt_comb_16_31">
<setting name="IRQn" value="GPIO1_Combined_16_31_IRQn"/>
<setting name="enable_interrrupt" value="enabled"/>
<setting name="enable_priority" value="false"/>
<setting name="priority" value="0"/>
<setting name="enable_custom_name" value="false"/>
</struct>
</config_set>
</instance>
<instance name="NVIC" uuid="2a54e709-5718-4b89-8b7b-71cefb418658" type="nvic" type_id="nvic_57b5eef3774cc60acaede6f5b8bddc67" mode="general" peripheral="NVIC" enabled="true" comment="" custom_name_enabled="false" editing_lock="false">
<config_set name="nvic">
<array name="interrupt_table"/>
<array name="interrupts"/>
</config_set>
</instance>
</instances>
</functional_group>
</functional_groups>
<components>
<component name="system" uuid="991327ca-3ad0-49d1-aff3-37b7734338db" type_id="system">
<config_set_global name="global_system_definitions">
<setting name="user_definitions" value=""/>
<setting name="user_includes" value=""/>
</config_set_global>
</component>
<component name="msg" uuid="3e46e698-099c-4180-92f5-2af1abbb93a5" type_id="msg">
<config_set_global name="global_messages"/>
</component>
<component name="gpio_adapter_common" uuid="27e43a4b-bddb-4db2-8f6b-3f6a73008a27" type_id="gpio_adapter_common_57579b9ac814fe26bf95df0a384c36b6">
<config_set_global name="global_gpio_adapter_common" quick_selection="default"/>
</component>
<component name="generic_uart" uuid="c946fe99-5d76-4cca-8be0-dea3c7861b68" type_id="generic_uart_8cae00565451cf2346eb1b8c624e73a6">
<config_set_global name="global_uart"/>
</component>
<component name="generic_can" uuid="c18a4299-93be-44e8-b563-3985b3e264c5" type_id="generic_can_1bfdd78b1af214566c1f23cf6a582d80">
<config_set_global name="global_can"/>
</component>
<component name="uart_cmsis_common" uuid="6149366a-a07f-40a7-8909-00ba459085a7" type_id="uart_cmsis_common_9cb8e302497aa696fdbb5a4fd622c2a8">
<config_set_global name="global_USART_CMSIS_common" quick_selection="default"/>
</component>
<component name="generic_enet" uuid="15cc4d18-2002-44a4-b7e7-f681a046f26c" type_id="generic_enet_74db5c914f0ddbe47d86af40cb77a619">
<config_set_global name="global_enet"/>
</component>
</components>
</periphs>
<tee name="TEE" version="4.0" enabled="false" update_project_code="true">
<generated_project_files/>
<tee_profile>
<processor_version>0.0.0</processor_version>
</tee_profile>
</tee>
</tools>
</configuration>

215
managed_components/espressif__tinyusb/hw/bsp/imxrt/boards/metro_m7_1011_sd/ozone/metro_m7_1011_sd.jdebug Normal file
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/*********************************************************************
*
* OnProjectLoad
*
* Function description
* Project load routine. Required.
*
**********************************************************************
*/
void OnProjectLoad (void) {
Project.SetTraceSource ("Trace Pins");
Project.SetTraceTiming (50, 50, 50, 50);
Project.SetDevice ("MIMXRT1011xxx4A");
Project.SetHostIF ("USB", "");
Project.SetTargetIF ("SWD");
Project.SetTIFSpeed ("20 MHz");
Project.AddSvdFile ("$(InstallDir)/Config/CPU/Cortex-M7F.svd");
Project.AddSvdFile ("$(InstallDir)/Config/Peripherals/ARMv7M.svd");
Project.AddSvdFile ("./MIMXRT1011.svd");
// timing delay for trace pins in pico seconds, default is 2 nano seconds
File.Open ("../../../../../../examples/cmake-build-metro-m7-1011-sd/device/cdc_msc/cdc_msc.elf");
}
/*********************************************************************
*
* TargetReset
*
* Function description
* Replaces the default target device reset routine. Optional.
*
* Notes
* This example demonstrates the usage when
* debugging a RAM program on a Cortex-M target device
*
**********************************************************************
*/
//void TargetReset (void) {
//
// unsigned int SP;
// unsigned int PC;
// unsigned int VectorTableAddr;
//
// Exec.Reset();
//
// VectorTableAddr = Elf.GetBaseAddr();
//
// if (VectorTableAddr != 0xFFFFFFFF) {
//
// Util.Log("Resetting Program.");
//
// SP = Target.ReadU32(VectorTableAddr);
// Target.SetReg("SP", SP);
//
// PC = Target.ReadU32(VectorTableAddr + 4);
// Target.SetReg("PC", PC);
// }
//}
/*********************************************************************
*
* BeforeTargetReset
*
* Function description
* Event handler routine. Optional.
*
**********************************************************************
*/
//void BeforeTargetReset (void) {
//}
/*********************************************************************
*
* AfterTargetReset
*
* Function description
* Event handler routine.
* - Sets the PC register to program reset value.
* - Sets the SP register to program reset value on Cortex-M.
*
**********************************************************************
*/
void AfterTargetReset (void) {
}
/*********************************************************************
*
* DebugStart
*
* Function description
* Replaces the default debug session startup routine. Optional.
*
**********************************************************************
*/
//void DebugStart (void) {
//}
/*********************************************************************
*
* TargetConnect
*
* Function description
* Replaces the default target IF connection routine. Optional.
*
**********************************************************************
*/
//void TargetConnect (void) {
//}
/*********************************************************************
*
* BeforeTargetConnect
*
* Function description
* Event handler routine. Optional.
*
**********************************************************************
*/
void BeforeTargetConnect (void) {
//
// Trace pin init is done by J-Link script file as J-Link script files are IDE independent
//
//Project.SetJLinkScript("./ST_STM32H743_Traceconfig.pex");
}
/*********************************************************************
*
* AfterTargetConnect
*
* Function description
* Event handler routine. Optional.
*
**********************************************************************
*/
//void AfterTargetConnect (void) {
//}
/*********************************************************************
*
* TargetDownload
*
* Function description
* Replaces the default program download routine. Optional.
*
**********************************************************************
*/
//void TargetDownload (void) {
//}
/*********************************************************************
*
* BeforeTargetDownload
*
* Function description
* Event handler routine. Optional.
*
**********************************************************************
*/
//void BeforeTargetDownload (void) {
//}
/*********************************************************************
*
* AfterTargetDownload
*
* Function description
* Event handler routine.
* - Sets the PC register to program reset value.
* - Sets the SP register to program reset value on Cortex-M.
*
**********************************************************************
*/
void AfterTargetDownload (void) {
}
/*********************************************************************
*
* BeforeTargetDisconnect
*
* Function description
* Event handler routine. Optional.
*
**********************************************************************
*/
//void BeforeTargetDisconnect (void) {
//}
/*********************************************************************
*
* AfterTargetDisconnect
*
* Function description
* Event handler routine. Optional.
*
**********************************************************************
*/
//void AfterTargetDisconnect (void) {
//}
/*********************************************************************
*
* AfterTargetHalt
*
* Function description
* Event handler routine. Optional.
*
**********************************************************************
*/
//void AfterTargetHalt (void) {
//}

15
managed_components/espressif__tinyusb/hw/bsp/imxrt/boards/mimxrt1010_evk/board.cmake Normal file
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set(MCU_VARIANT MIMXRT1011)
set(JLINK_DEVICE MIMXRT1011xxx5A)
set(PYOCD_TARGET mimxrt1010)
set(NXPLINK_DEVICE MIMXRT1011xxxxx:EVK-MIMXRT1010)
function(update_board TARGET)
target_sources(${TARGET} PUBLIC
${CMAKE_CURRENT_FUNCTION_LIST_DIR}/evkmimxrt1010_flexspi_nor_config.c
)
target_compile_definitions(${TARGET} PUBLIC
CPU_MIMXRT1011DAE5A
CFG_EXAMPLE_VIDEO_READONLY
)
endfunction()

55
managed_components/espressif__tinyusb/hw/bsp/imxrt/boards/mimxrt1010_evk/board.h Normal file
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/*
* The MIT License (MIT)
*
* Copyright (c) 2019, Ha Thach (tinyusb.org)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* This file is part of the TinyUSB stack.
*/
/* metadata:
name: i.MX RT1010 Evaluation Kit
url: https://www.nxp.com/design/design-center/development-boards-and-designs/i-mx-evaluation-and-development-boards/i-mx-rt1010-evaluation-kit:MIMXRT1010-EVK
*/
#ifndef BOARD_MIMXRT1010_EVK_H_
#define BOARD_MIMXRT1010_EVK_H_
// required since iMXRT MCUX-SDK include this file for board size
#define BOARD_FLASH_SIZE (0x1000000U)
// LED: IOMUXC_GPIO_11_GPIOMUX_IO11
#define LED_PORT BOARD_INITPINS_USER_LED_PERIPHERAL
#define LED_PIN BOARD_INITPINS_USER_LED_CHANNEL
#define LED_STATE_ON 0
// SW8 button: IOMUXC_GPIO_SD_05_GPIO2_IO05
#define BUTTON_PORT BOARD_INITPINS_USER_BUTTON_GPIO
#define BUTTON_PIN BOARD_INITPINS_USER_BUTTON_GPIO_PIN
#define BUTTON_STATE_ACTIVE 0
// UART: IOMUXC_GPIO_09_LPUART1_RXD, IOMUXC_GPIO_10_LPUART1_TXD
#define UART_PORT LPUART1
#define UART_CLK_ROOT BOARD_BOOTCLOCKRUN_UART_CLK_ROOT
static inline void BOARD_ConfigMPU(void) {
}
#endif

11
managed_components/espressif__tinyusb/hw/bsp/imxrt/boards/mimxrt1010_evk/board.mk Normal file
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CFLAGS += -DCPU_MIMXRT1011DAE5A -DCFG_EXAMPLE_VIDEO_READONLY
MCU_VARIANT = MIMXRT1011
# For flash-jlink target
JLINK_DEVICE = MIMXRT1011xxx5A
# For flash-pyocd target
PYOCD_TARGET = mimxrt1010
# flash using pyocd
flash: flash-pyocd

340
managed_components/espressif__tinyusb/hw/bsp/imxrt/boards/mimxrt1010_evk/board/clock_config.c Normal file
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/*
* How to setup clock using clock driver functions:
*
* 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock.
*
* 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock.
*
* 3. Call CLOCK_SetMux() to configure corresponding clock source for target clock out.
*
* 4. Call CLOCK_SetDiv() to configure corresponding clock divider for target clock out.
*
* 5. Call CLOCK_SetXtalFreq() to set XTAL frequency based on board settings.
*
*/
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!GlobalInfo
product: Clocks v11.0
processor: MIMXRT1011xxxxx
package_id: MIMXRT1011DAE5A
mcu_data: ksdk2_0
processor_version: 13.0.2
board: MIMXRT1010-EVK
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
#include "clock_config.h"
#include "fsl_iomuxc.h"
/*******************************************************************************
* Definitions
******************************************************************************/
/*******************************************************************************
* Variables
******************************************************************************/
/*******************************************************************************
************************ BOARD_InitBootClocks function ************************
******************************************************************************/
void BOARD_InitBootClocks(void)
{
BOARD_BootClockRUN();
}
/*******************************************************************************
********************** Configuration BOARD_BootClockRUN ***********************
******************************************************************************/
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!Configuration
name: BOARD_BootClockRUN
called_from_default_init: true
outputs:
- {id: ADC_ALT_CLK.outFreq, value: 40 MHz}
- {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz}
- {id: CLK_1M.outFreq, value: 1 MHz}
- {id: CLK_24M.outFreq, value: 24 MHz}
- {id: CORE_CLK_ROOT.outFreq, value: 500 MHz}
- {id: ENET_500M_REF_CLK.outFreq, value: 500 MHz}
- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz}
- {id: FLEXSPI_CLK_ROOT.outFreq, value: 132 MHz}
- {id: GPT1_ipg_clk_highfreq.outFreq, value: 62.5 MHz}
- {id: GPT2_ipg_clk_highfreq.outFreq, value: 62.5 MHz}
- {id: IPG_CLK_ROOT.outFreq, value: 125 MHz}
- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz}
- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz}
- {id: MQS_MCLK.outFreq, value: 1080/17 MHz}
- {id: PERCLK_CLK_ROOT.outFreq, value: 62.5 MHz}
- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz}
- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz}
- {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz}
- {id: SAI1_MCLK3.outFreq, value: 30 MHz}
- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz}
- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz}
- {id: SAI3_MCLK3.outFreq, value: 30 MHz}
- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz}
- {id: TRACE_CLK_ROOT.outFreq, value: 132 MHz}
- {id: UART_CLK_ROOT.outFreq, value: 80 MHz}
- {id: USBPHY_CLK.outFreq, value: 480 MHz}
settings:
- {id: CCM.ADC_ACLK_PODF.scale, value: '12', locked: true}
- {id: CCM.AHB_PODF.scale, value: '1', locked: true}
- {id: CCM.FLEXSPI_PODF.scale, value: '4', locked: true}
- {id: CCM.IPG_PODF.scale, value: '4'}
- {id: CCM.LPSPI_PODF.scale, value: '5'}
- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true}
- {id: CCM.PRE_PERIPH_CLK_SEL.sel, value: CCM_ANALOG.ENET_500M_REF_CLK}
- {id: CCM.SAI1_CLK_SEL.sel, value: CCM_ANALOG.PLL3_PFD2_CLK}
- {id: CCM.SAI3_CLK_SEL.sel, value: CCM_ANALOG.PLL3_PFD2_CLK}
- {id: CCM.TRACE_CLK_SEL.sel, value: CCM_ANALOG.PLL2_MAIN_CLK}
- {id: CCM_ANALOG.PLL2.denom, value: '1'}
- {id: CCM_ANALOG.PLL2.num, value: '0'}
- {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK}
- {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0}
- {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1}
- {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2}
- {id: CCM_ANALOG.PLL2_PFD2_DIV.scale, value: '18', locked: true}
- {id: CCM_ANALOG.PLL2_PFD2_MUL.scale, value: '18', locked: true}
- {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3}
- {id: CCM_ANALOG.PLL2_PFD3_DIV.scale, value: '18', locked: true}
- {id: CCM_ANALOG.PLL2_PFD3_MUL.scale, value: '18', locked: true}
- {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3}
- {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0}
- {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '22', locked: true}
- {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true}
- {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1}
- {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2}
- {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3}
- {id: CCM_ANALOG.PLL3_PFD3_DIV.scale, value: '18', locked: true}
- {id: CCM_ANALOG.PLL3_PFD3_MUL.scale, value: '18', locked: true}
- {id: CCM_ANALOG.PLL6_BYPASS.sel, value: CCM_ANALOG.PLL6}
- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_CFG, value: Enabled}
- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_OUT_CFG, value: Enabled}
- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'}
sources:
- {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/*******************************************************************************
* Variables for BOARD_BootClockRUN configuration
******************************************************************************/
const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN =
{
.loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */
.numerator = 0, /* 30 bit numerator of fractional loop divider */
.denominator = 1, /* 30 bit denominator of fractional loop divider */
.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
};
const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN =
{
.loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */
.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
};
const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN =
{
.enableClkOutput500M = true, /* Enable the PLL providing the ENET 500MHz reference clock */
.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
};
/*******************************************************************************
* Code for BOARD_BootClockRUN configuration
******************************************************************************/
void BOARD_BootClockRUN(void)
{
/* Init RTC OSC clock frequency. */
CLOCK_SetRtcXtalFreq(32768U);
/* Enable 1MHz clock output. */
XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK;
/* Use free 1MHz clock output. */
XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK;
/* Set XTAL 24MHz clock frequency. */
CLOCK_SetXtalFreq(24000000U);
/* Enable XTAL 24MHz clock source. */
CLOCK_InitExternalClk(0);
/* Enable internal RC. */
CLOCK_InitRcOsc24M();
/* Switch clock source to external OSC. */
CLOCK_SwitchOsc(kCLOCK_XtalOsc);
/* Set Oscillator ready counter value. */
CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127);
/* Setting the VDD_SOC to 1.25V. It is necessary to config CORE to 500Mhz. */
DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x12);
/* Waiting for DCDC_STS_DC_OK bit is asserted */
while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0))
{
}
/* Disable IPG clock gate. */
CLOCK_DisableClock(kCLOCK_Adc1);
CLOCK_DisableClock(kCLOCK_Xbar1);
/* Set IPG_PODF. */
CLOCK_SetDiv(kCLOCK_IpgDiv, 3);
/* Init Enet PLL. */
CLOCK_InitEnetPll(&enetPllConfig_BOARD_BootClockRUN);
/* Disable PERCLK clock gate. */
CLOCK_DisableClock(kCLOCK_Gpt1);
CLOCK_DisableClock(kCLOCK_Gpt1S);
CLOCK_DisableClock(kCLOCK_Gpt2);
CLOCK_DisableClock(kCLOCK_Gpt2S);
CLOCK_DisableClock(kCLOCK_Pit);
/* Set PERCLK_PODF. */
CLOCK_SetDiv(kCLOCK_PerclkDiv, 1);
/* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
* With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
* Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
/* Disable Flexspi clock gate. */
CLOCK_DisableClock(kCLOCK_FlexSpi);
/* Set FLEXSPI_PODF. */
CLOCK_SetDiv(kCLOCK_FlexspiDiv, 3);
/* Set Flexspi clock source. */
CLOCK_SetMux(kCLOCK_FlexspiMux, 0);
CLOCK_SetMux(kCLOCK_FlexspiSrcMux, 0);
#endif
/* Disable ADC_ACLK_EN clock gate. */
CCM->CSCMR2 &= ~CCM_CSCMR2_ADC_ACLK_EN_MASK;
/* Set ADC_ACLK_PODF. */
CLOCK_SetDiv(kCLOCK_AdcDiv, 11);
/* Disable LPSPI clock gate. */
CLOCK_DisableClock(kCLOCK_Lpspi1);
CLOCK_DisableClock(kCLOCK_Lpspi2);
/* Set LPSPI_PODF. */
CLOCK_SetDiv(kCLOCK_LpspiDiv, 4);
/* Set Lpspi clock source. */
CLOCK_SetMux(kCLOCK_LpspiMux, 2);
/* Disable TRACE clock gate. */
CLOCK_DisableClock(kCLOCK_Trace);
/* Set TRACE_PODF. */
CLOCK_SetDiv(kCLOCK_TraceDiv, 3);
/* Set Trace clock source. */
CLOCK_SetMux(kCLOCK_TraceMux, 0);
/* Disable SAI1 clock gate. */
CLOCK_DisableClock(kCLOCK_Sai1);
/* Set SAI1_CLK_PRED. */
CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3);
/* Set SAI1_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_Sai1Div, 1);
/* Set Sai1 clock source. */
CLOCK_SetMux(kCLOCK_Sai1Mux, 0);
/* Disable SAI3 clock gate. */
CLOCK_DisableClock(kCLOCK_Sai3);
/* Set SAI3_CLK_PRED. */
CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3);
/* Set SAI3_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_Sai3Div, 1);
/* Set Sai3 clock source. */
CLOCK_SetMux(kCLOCK_Sai3Mux, 0);
/* Disable Lpi2c clock gate. */
CLOCK_DisableClock(kCLOCK_Lpi2c1);
CLOCK_DisableClock(kCLOCK_Lpi2c2);
/* Set LPI2C_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0);
/* Set Lpi2c clock source. */
CLOCK_SetMux(kCLOCK_Lpi2cMux, 0);
/* Disable UART clock gate. */
CLOCK_DisableClock(kCLOCK_Lpuart1);
CLOCK_DisableClock(kCLOCK_Lpuart2);
CLOCK_DisableClock(kCLOCK_Lpuart3);
CLOCK_DisableClock(kCLOCK_Lpuart4);
/* Set UART_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_UartDiv, 0);
/* Set Uart clock source. */
CLOCK_SetMux(kCLOCK_UartMux, 0);
/* Disable SPDIF clock gate. */
CLOCK_DisableClock(kCLOCK_Spdif);
/* Set SPDIF0_CLK_PRED. */
CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1);
/* Set SPDIF0_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_Spdif0Div, 7);
/* Set Spdif clock source. */
CLOCK_SetMux(kCLOCK_SpdifMux, 3);
/* Disable Flexio1 clock gate. */
CLOCK_DisableClock(kCLOCK_Flexio1);
/* Set FLEXIO1_CLK_PRED. */
CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1);
/* Set FLEXIO1_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_Flexio1Div, 7);
/* Set Flexio1 clock source. */
CLOCK_SetMux(kCLOCK_Flexio1Mux, 3);
/* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
* With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
* Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
/* Init Usb1 PLL. */
CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN);
/* Init Usb1 pfd0. */
CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 22);
/* Init Usb1 pfd1. */
CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16);
/* Init Usb1 pfd2. */
CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17);
/* Init Usb1 pfd3. */
CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 18);
#endif
/* Set periph clock source to use the USB1 PLL output (PLL3_SW_CLK) temporarily. */
/* Set Pll3 SW clock source to use the USB1 PLL output. */
CLOCK_SetMux(kCLOCK_Pll3SwMux, 0);
/* Set safe value of the AHB_PODF. */
CLOCK_SetDiv(kCLOCK_AhbDiv, 1);
/* Set periph clock2 clock source to use the PLL3_SW_CLK. */
CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
/* Set peripheral clock source (glitchless mux) to select the temporary core clock. */
CLOCK_SetMux(kCLOCK_PeriphMux, 1);
/* Set per clock source. */
CLOCK_SetMux(kCLOCK_PerclkMux, 0);
/* Init System PLL. */
CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN);
/* Init System pfd0. */
CLOCK_InitSysPfd(kCLOCK_Pfd0, 27);
/* Init System pfd1. */
CLOCK_InitSysPfd(kCLOCK_Pfd1, 16);
/* Init System pfd2. */
CLOCK_InitSysPfd(kCLOCK_Pfd2, 18);
/* Init System pfd3. */
CLOCK_InitSysPfd(kCLOCK_Pfd3, 18);
/* DeInit Audio PLL. */
CLOCK_DeinitAudioPll();
/* Bypass Audio PLL. */
CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1);
/* Set divider for Audio PLL. */
CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK;
CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK;
/* Enable Audio PLL output. */
CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK;
/* Set preperiph clock source. */
CLOCK_SetMux(kCLOCK_PrePeriphMux, 3);
/* Set periph clock source. */
CLOCK_SetMux(kCLOCK_PeriphMux, 0);
/* Set periph clock2 clock source. */
CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
/* Set AHB_PODF. */
CLOCK_SetDiv(kCLOCK_AhbDiv, 0);
/* Set clock out1 divider. */
CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0);
/* Set clock out1 source. */
CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1);
/* Set clock out2 divider. */
CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0);
/* Set clock out2 source. */
CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(18);
/* Set clock out1 drives clock out1. */
CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK;
/* Disable clock out1. */
CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK;
/* Disable clock out2. */
CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK;
/* Set SAI1 MCLK1 clock source. */
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0);
/* Set SAI1 MCLK2 clock source. */
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0);
/* Set SAI1 MCLK3 clock source. */
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0);
/* Set SAI3 MCLK3 clock source. */
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
/* Set MQS configuration. */
IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0);
/* Set GPT1 High frequency reference clock source. */
IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK;
/* Set GPT2 High frequency reference clock source. */
IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK;
/* Set SystemCoreClock variable. */
SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
}

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#ifndef _CLOCK_CONFIG_H_
#define _CLOCK_CONFIG_H_
#include "fsl_common.h"
/*******************************************************************************
* Definitions
******************************************************************************/
#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */
#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */
/*******************************************************************************
************************ BOARD_InitBootClocks function ************************
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/
/*!
* @brief This function executes default configuration of clocks.
*
*/
void BOARD_InitBootClocks(void);
#if defined(__cplusplus)
}
#endif /* __cplusplus*/
/*******************************************************************************
********************** Configuration BOARD_BootClockRUN ***********************
******************************************************************************/
/*******************************************************************************
* Definitions for BOARD_BootClockRUN configuration
******************************************************************************/
#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 500000000U /*!< Core clock frequency: 500000000Hz */
/* Clock outputs (values are in Hz): */
#define BOARD_BOOTCLOCKRUN_ADC_ALT_CLK 40000000UL
#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL
#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL
#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL
#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL
#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL
#define BOARD_BOOTCLOCKRUN_CORE_CLK_ROOT 500000000UL
#define BOARD_BOOTCLOCKRUN_ENET_500M_REF_CLK 500000000UL
#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL
#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 132000000UL
#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 62500000UL
#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 62500000UL
#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 125000000UL
#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL
#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL
#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL
#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 62500000UL
#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL
#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL
#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL
#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL
#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 132000000UL
#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL
#define BOARD_BOOTCLOCKRUN_USBPHY_CLK 480000000UL
/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration.
*/
extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN;
/*! @brief Sys PLL for BOARD_BootClockRUN configuration.
*/
extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN;
/*! @brief Enet PLL set for BOARD_BootClockRUN configuration.
*/
extern const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN;
/*******************************************************************************
* API for BOARD_BootClockRUN configuration
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/
/*!
* @brief This function executes configuration of clocks.
*
*/
void BOARD_BootClockRUN(void);
#if defined(__cplusplus)
}
#endif /* __cplusplus*/
#endif /* _CLOCK_CONFIG_H_ */

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/***********************************************************************************************************************
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
**********************************************************************************************************************/
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!GlobalInfo
product: Pins v13.1
processor: MIMXRT1011xxxxx
package_id: MIMXRT1011DAE5A
mcu_data: ksdk2_0
processor_version: 13.0.2
board: MIMXRT1010-EVK
external_user_signals: {}
pin_labels:
- {pin_num: '1', pin_signal: GPIO_11, label: GPIO_11, identifier: LED;USERLED;USER_LED}
power_domains: {NVCC_GPIO: '3.3'}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
#include "fsl_common.h"
#include "fsl_iomuxc.h"
#include "fsl_gpio.h"
#include "pin_mux.h"
/* FUNCTION ************************************************************************************************************
*
* Function Name : BOARD_InitBootPins
* Description : Calls initialization functions.
*
* END ****************************************************************************************************************/
void BOARD_InitBootPins(void) {
BOARD_InitPins();
}
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
BOARD_InitPins:
- options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'}
- pin_list:
- {pin_num: '70', peripheral: GPIO2, signal: 'gpio_io, 05', pin_signal: GPIO_SD_05, direction: INPUT, pull_keeper_select: Pull, pull_up_down_config: Pull_Up_47K_Ohm}
- {pin_num: '1', peripheral: GPIO1, signal: 'gpiomux_io, 11', pin_signal: GPIO_11, identifier: USER_LED, direction: OUTPUT}
- {pin_num: '3', peripheral: LPUART1, signal: RXD, pin_signal: GPIO_09}
- {pin_num: '2', peripheral: LPUART1, signal: TXD, pin_signal: GPIO_10}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
/* FUNCTION ************************************************************************************************************
*
* Function Name : BOARD_InitPins
* Description : Configures pin routing and optionally pin electrical features.
*
* END ****************************************************************************************************************/
void BOARD_InitPins(void) {
CLOCK_EnableClock(kCLOCK_Iomuxc);
/* GPIO configuration of USER_LED on GPIO_11 (pin 1) */
gpio_pin_config_t USER_LED_config = {
.direction = kGPIO_DigitalOutput,
.outputLogic = 0U,
.interruptMode = kGPIO_NoIntmode
};
/* Initialize GPIO functionality on GPIO_11 (pin 1) */
GPIO_PinInit(GPIO1, 11U, &USER_LED_config);
/* GPIO configuration of USER_BUTTON on GPIO_SD_05 (pin 70) */
gpio_pin_config_t USER_BUTTON_config = {
.direction = kGPIO_DigitalInput,
.outputLogic = 0U,
.interruptMode = kGPIO_NoIntmode
};
/* Initialize GPIO functionality on GPIO_SD_05 (pin 70) */
GPIO_PinInit(GPIO2, 5U, &USER_BUTTON_config);
IOMUXC_SetPinMux(IOMUXC_GPIO_09_LPUART1_RXD, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_10_LPUART1_TXD, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_11_GPIOMUX_IO11, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_05_GPIO2_IO05, 0U);
IOMUXC_GPR->GPR26 = ((IOMUXC_GPR->GPR26 &
(~(BOARD_INITPINS_IOMUXC_GPR_GPR26_GPIO_SEL_MASK)))
| IOMUXC_GPR_GPR26_GPIO_SEL(0x00U)
);
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_05_GPIO2_IO05, 0x70A0U);
}
/***********************************************************************************************************************
* EOF
**********************************************************************************************************************/

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/***********************************************************************************************************************
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
**********************************************************************************************************************/
#ifndef _PIN_MUX_H_
#define _PIN_MUX_H_
/***********************************************************************************************************************
* Definitions
**********************************************************************************************************************/
/*! @brief Direction type */
typedef enum _pin_mux_direction
{
kPIN_MUX_DirectionInput = 0U, /* Input direction */
kPIN_MUX_DirectionOutput = 1U, /* Output direction */
kPIN_MUX_DirectionInputOrOutput = 2U /* Input or output direction */
} pin_mux_direction_t;
/*!
* @addtogroup pin_mux
* @{
*/
/***********************************************************************************************************************
* API
**********************************************************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif
/*!
* @brief Calls initialization functions.
*
*/
void BOARD_InitBootPins(void);
#define BOARD_INITPINS_IOMUXC_GPR_GPR26_GPIO_SEL_MASK 0x0820U /*!< Select GPIO1 or GPIO2: affected bits mask */
/* GPIO_SD_05 (number 70), USER_BUTTON */
/* Routed pin properties */
#define BOARD_INITPINS_USER_BUTTON_PERIPHERAL GPIO2 /*!< Peripheral name */
#define BOARD_INITPINS_USER_BUTTON_SIGNAL gpio_io /*!< Signal name */
#define BOARD_INITPINS_USER_BUTTON_CHANNEL 5U /*!< Signal channel */
/* Symbols to be used with GPIO driver */
#define BOARD_INITPINS_USER_BUTTON_GPIO GPIO2 /*!< GPIO peripheral base pointer */
#define BOARD_INITPINS_USER_BUTTON_GPIO_PIN 5U /*!< GPIO pin number */
#define BOARD_INITPINS_USER_BUTTON_GPIO_PIN_MASK (1U << 5U) /*!< GPIO pin mask */
#define BOARD_INITPINS_USER_BUTTON_PORT GPIO2 /*!< PORT peripheral base pointer */
#define BOARD_INITPINS_USER_BUTTON_PIN 5U /*!< PORT pin number */
#define BOARD_INITPINS_USER_BUTTON_PIN_MASK (1U << 5U) /*!< PORT pin mask */
/* GPIO_11 (number 1), GPIO_11 */
/* Routed pin properties */
#define BOARD_INITPINS_USER_LED_PERIPHERAL GPIO1 /*!< Peripheral name */
#define BOARD_INITPINS_USER_LED_SIGNAL gpiomux_io /*!< Signal name */
#define BOARD_INITPINS_USER_LED_CHANNEL 11U /*!< Signal channel */
/* GPIO_09 (number 3), LPUART1_RXD/J56[2] */
/* Routed pin properties */
#define BOARD_INITPINS_UART1_RXD_PERIPHERAL LPUART1 /*!< Peripheral name */
#define BOARD_INITPINS_UART1_RXD_SIGNAL RXD /*!< Signal name */
/* GPIO_10 (number 2), LPUART1_TXD/J56[4] */
/* Routed pin properties */
#define BOARD_INITPINS_UART1_TXD_PERIPHERAL LPUART1 /*!< Peripheral name */
#define BOARD_INITPINS_UART1_TXD_SIGNAL TXD /*!< Signal name */
/*!
* @brief Configures pin routing and optionally pin electrical features.
*
*/
void BOARD_InitPins(void);
#if defined(__cplusplus)
}
#endif
/*!
* @}
*/
#endif /* _PIN_MUX_H_ */
/***********************************************************************************************************************
* EOF
**********************************************************************************************************************/

48
managed_components/espressif__tinyusb/hw/bsp/imxrt/boards/mimxrt1010_evk/evkmimxrt1010_flexspi_nor_config.c Normal file
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/*
* Copyright 2019 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "evkmimxrt1010_flexspi_nor_config.h"
/* Component ID definition, used by tools. */
#ifndef FSL_COMPONENT_ID
#define FSL_COMPONENT_ID "platform.drivers.xip_board"
#endif
/*******************************************************************************
* Code
******************************************************************************/
#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
__attribute__((section(".boot_hdr.conf")))
#elif defined(__ICCARM__)
#pragma location = ".boot_hdr.conf"
#endif
const flexspi_nor_config_t qspiflash_config = {
.memConfig =
{
.tag = FLEXSPI_CFG_BLK_TAG,
.version = FLEXSPI_CFG_BLK_VERSION,
.readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad,
.csHoldTime = 3u,
.csSetupTime = 3u,
.sflashPadType = kSerialFlash_4Pads,
.serialClkFreq = kFlexSpiSerialClk_100MHz,
.sflashA1Size = 16u * 1024u * 1024u,
.lookupTable =
{
// Read LUTs
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18),
FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04),
},
},
.pageSize = 256u,
.sectorSize = 4u * 1024u,
.blockSize = 256u * 1024u,
.isUniformBlockSize = false,
};
#endif /* XIP_BOOT_HEADER_ENABLE */

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/*
* Copyright 2019 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __EVKMIMXRT1011_FLEXSPI_NOR_CONFIG__
#define __EVKMIMXRT1011_FLEXSPI_NOR_CONFIG__
#include <stdint.h>
#include <stdbool.h>
#include "fsl_common.h"
/*! @name Driver version */
/*@{*/
/*! @brief XIP_BOARD driver version 2.0.0. */
#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
/*@}*/
/* FLEXSPI memory config block related definitions */
#define FLEXSPI_CFG_BLK_TAG (0x42464346UL) // ascii "FCFB" Big Endian
#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0
#define FLEXSPI_CFG_BLK_SIZE (512)
/* FLEXSPI Feature related definitions */
#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1
/* Lookup table related definitions */
#define CMD_INDEX_READ 0
#define CMD_INDEX_READSTATUS 1
#define CMD_INDEX_WRITEENABLE 2
#define CMD_INDEX_WRITE 4
#define CMD_LUT_SEQ_IDX_READ 0
#define CMD_LUT_SEQ_IDX_READSTATUS 1
#define CMD_LUT_SEQ_IDX_WRITEENABLE 3
#define CMD_LUT_SEQ_IDX_WRITE 9
#define CMD_SDR 0x01
#define CMD_DDR 0x21
#define RADDR_SDR 0x02
#define RADDR_DDR 0x22
#define CADDR_SDR 0x03
#define CADDR_DDR 0x23
#define MODE1_SDR 0x04
#define MODE1_DDR 0x24
#define MODE2_SDR 0x05
#define MODE2_DDR 0x25
#define MODE4_SDR 0x06
#define MODE4_DDR 0x26
#define MODE8_SDR 0x07
#define MODE8_DDR 0x27
#define WRITE_SDR 0x08
#define WRITE_DDR 0x28
#define READ_SDR 0x09
#define READ_DDR 0x29
#define LEARN_SDR 0x0A
#define LEARN_DDR 0x2A
#define DATSZ_SDR 0x0B
#define DATSZ_DDR 0x2B
#define DUMMY_SDR 0x0C
#define DUMMY_DDR 0x2C
#define DUMMY_RWDS_SDR 0x0D
#define DUMMY_RWDS_DDR 0x2D
#define JMP_ON_CS 0x1F
#define STOP 0
#define FLEXSPI_1PAD 0
#define FLEXSPI_2PAD 1
#define FLEXSPI_4PAD 2
#define FLEXSPI_8PAD 3
#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \
(FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \
FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))
//!@brief Definitions for FlexSPI Serial Clock Frequency
typedef enum _FlexSpiSerialClockFreq
{
kFlexSpiSerialClk_30MHz = 1,
kFlexSpiSerialClk_50MHz = 2,
kFlexSpiSerialClk_60MHz = 3,
kFlexSpiSerialClk_75MHz = 4,
kFlexSpiSerialClk_80MHz = 5,
kFlexSpiSerialClk_100MHz = 6,
kFlexSpiSerialClk_120MHz = 7,
kFlexSpiSerialClk_133MHz = 8,
} flexspi_serial_clk_freq_t;
//!@brief FlexSPI clock configuration type
enum
{
kFlexSpiClk_SDR, //!< Clock configure for SDR mode
kFlexSpiClk_DDR, //!< Clock configurat for DDR mode
};
//!@brief FlexSPI Read Sample Clock Source definition
typedef enum _FlashReadSampleClkSource
{
kFlexSPIReadSampleClk_LoopbackInternally = 0,
kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1,
kFlexSPIReadSampleClk_LoopbackFromSckPad = 2,
kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3,
} flexspi_read_sample_clk_t;
//!@brief Misc feature bit definitions
enum
{
kFlexSpiMiscOffset_DiffClkEnable = 0, //!< Bit for Differential clock enable
kFlexSpiMiscOffset_Ck2Enable = 1, //!< Bit for CK2 enable
kFlexSpiMiscOffset_ParallelEnable = 2, //!< Bit for Parallel mode enable
kFlexSpiMiscOffset_WordAddressableEnable = 3, //!< Bit for Word Addressable enable
kFlexSpiMiscOffset_SafeConfigFreqEnable = 4, //!< Bit for Safe Configuration Frequency enable
kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, //!< Bit for Pad setting override enable
kFlexSpiMiscOffset_DdrModeEnable = 6, //!< Bit for DDR clock confiuration indication.
};
//!@brief Flash Type Definition
enum
{
kFlexSpiDeviceType_SerialNOR = 1, //!< Flash devices are Serial NOR
kFlexSpiDeviceType_SerialNAND = 2, //!< Flash devices are Serial NAND
kFlexSpiDeviceType_SerialRAM = 3, //!< Flash devices are Serial RAM/HyperFLASH
kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND
kFlexSpiDeviceType_MCP_NOR_RAM = 0x13, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial RAMs
};
//!@brief Flash Pad Definitions
enum
{
kSerialFlash_1Pad = 1,
kSerialFlash_2Pads = 2,
kSerialFlash_4Pads = 4,
kSerialFlash_8Pads = 8,
};
//!@brief FlexSPI LUT Sequence structure
typedef struct _lut_sequence
{
uint8_t seqNum; //!< Sequence Number, valid number: 1-16
uint8_t seqId; //!< Sequence Index, valid number: 0-15
uint16_t reserved;
} flexspi_lut_seq_t;
//!@brief Flash Configuration Command Type
enum
{
kDeviceConfigCmdType_Generic, //!< Generic command, for example: configure dummy cycles, drive strength, etc
kDeviceConfigCmdType_QuadEnable, //!< Quad Enable command
kDeviceConfigCmdType_Spi2Xpi, //!< Switch from SPI to DPI/QPI/OPI mode
kDeviceConfigCmdType_Xpi2Spi, //!< Switch from DPI/QPI/OPI to SPI mode
kDeviceConfigCmdType_Spi2NoCmd, //!< Switch to 0-4-4/0-8-8 mode
kDeviceConfigCmdType_Reset, //!< Reset device command
};
//!@brief FlexSPI Memory Configuration Block
typedef struct _FlexSPIConfig
{
uint32_t tag; //!< [0x000-0x003] Tag, fixed value 0x42464346UL
uint32_t version; //!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix
uint32_t reserved0; //!< [0x008-0x00b] Reserved for future use
uint8_t readSampleClkSrc; //!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3
uint8_t csHoldTime; //!< [0x00d-0x00d] CS hold time, default value: 3
uint8_t csSetupTime; //!< [0x00e-0x00e] CS setup time, default value: 3
uint8_t columnAddressWidth; //!< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For
//! Serial NAND, need to refer to datasheet
uint8_t deviceModeCfgEnable; //!< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable
uint8_t deviceModeType; //!< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch,
//! Generic configuration, etc.
uint16_t waitTimeCfgCommands; //!< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for
//! DPI/QPI/OPI switch or reset command
flexspi_lut_seq_t deviceModeSeq; //!< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt
//! sequence number, [31:16] Reserved
uint32_t deviceModeArg; //!< [0x018-0x01b] Argument/Parameter for device configuration
uint8_t configCmdEnable; //!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable
uint8_t configModeType[3]; //!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe
flexspi_lut_seq_t
configCmdSeqs[3]; //!< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq
uint32_t reserved1; //!< [0x02c-0x02f] Reserved for future use
uint32_t configCmdArgs[3]; //!< [0x030-0x03b] Arguments/Parameters for device Configuration commands
uint32_t reserved2; //!< [0x03c-0x03f] Reserved for future use
uint32_t controllerMiscOption; //!< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more
//! details
uint8_t deviceType; //!< [0x044-0x044] Device Type: See Flash Type Definition for more details
uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal
uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequency, device specific definitions, See System Boot
//! Chapter for more details
uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot
//! be done using 1 LUT sequence, currently, only applicable to HyperFLASH
uint32_t reserved3[2]; //!< [0x048-0x04f] Reserved for future use
uint32_t sflashA1Size; //!< [0x050-0x053] Size of Flash connected to A1
uint32_t sflashA2Size; //!< [0x054-0x057] Size of Flash connected to A2
uint32_t sflashB1Size; //!< [0x058-0x05b] Size of Flash connected to B1
uint32_t sflashB2Size; //!< [0x05c-0x05f] Size of Flash connected to B2
uint32_t csPadSettingOverride; //!< [0x060-0x063] CS pad setting override value
uint32_t sclkPadSettingOverride; //!< [0x064-0x067] SCK pad setting override value
uint32_t dataPadSettingOverride; //!< [0x068-0x06b] data pad setting override value
uint32_t dqsPadSettingOverride; //!< [0x06c-0x06f] DQS pad setting override value
uint32_t timeoutInMs; //!< [0x070-0x073] Timeout threshold for read status command
uint32_t commandInterval; //!< [0x074-0x077] CS deselect interval between two commands
uint16_t dataValidTime[2]; //!< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns
uint16_t busyOffset; //!< [0x07c-0x07d] Busy offset, valid value: 0-31
uint16_t busyBitPolarity; //!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 -
//! busy flag is 0 when flash device is busy
uint32_t lookupTable[64]; //!< [0x080-0x17f] Lookup table holds Flash command sequences
flexspi_lut_seq_t lutCustomSeq[12]; //!< [0x180-0x1af] Customizable LUT Sequences
uint32_t reserved4[4]; //!< [0x1b0-0x1bf] Reserved for future use
} flexspi_mem_config_t;
/* */
#define NOR_CMD_INDEX_READ CMD_INDEX_READ //!< 0
#define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS //!< 1
#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE //!< 2
#define NOR_CMD_INDEX_ERASESECTOR 3 //!< 3
#define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE //!< 4
#define NOR_CMD_INDEX_CHIPERASE 5 //!< 5
#define NOR_CMD_INDEX_DUMMY 6 //!< 6
#define NOR_CMD_INDEX_ERASEBLOCK 7 //!< 7
#define NOR_CMD_LUT_SEQ_IDX_READ CMD_LUT_SEQ_IDX_READ //!< 0 READ LUT sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_READSTATUS \
CMD_LUT_SEQ_IDX_READSTATUS //!< 1 Read Status LUT sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \
2 //!< 2 Read status DPI/QPI/OPI sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE \
CMD_LUT_SEQ_IDX_WRITEENABLE //!< 3 Write Enable sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \
4 //!< 4 Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5 //!< 5 Erase Sector sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8 //!< 8 Erase Block sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM \
CMD_LUT_SEQ_IDX_WRITE //!< 9 Program sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11 //!< 11 Chip Erase sequence in lookupTable id stored in config block
#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13 //!< 13 Read SFDP sequence in lookupTable id stored in config block
#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \
14 //!< 14 Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \
15 //!< 15 Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config blobk
/*
* Serial NOR configuration block
*/
typedef struct _flexspi_nor_config
{
flexspi_mem_config_t memConfig; //!< Common memory configuration info via FlexSPI
uint32_t pageSize; //!< Page size of Serial NOR
uint32_t sectorSize; //!< Sector size of Serial NOR
uint8_t ipcmdSerialClkFreq; //!< Clock frequency for IP command
uint8_t isUniformBlockSize; //!< Sector/Block size is the same
uint8_t reserved0[2]; //!< Reserved for future use
uint8_t serialNorType; //!< Serial NOR Flash type: 0/1/2/3
uint8_t needExitNoCmdMode; //!< Need to exit NoCmd mode before other IP command
uint8_t halfClkForNonReadCmd; //!< Half the Serial Clock for non-read command: true/false
uint8_t needRestoreNoCmdMode; //!< Need to Restore NoCmd mode after IP command execution
uint32_t blockSize; //!< Block size
uint32_t reserve2[11]; //!< Reserved for future use
} flexspi_nor_config_t;
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __cplusplus
}
#endif
#endif /* __EVKMIMXRT1011_FLEXSPI_NOR_CONFIG__ */

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managed_components/espressif__tinyusb/hw/bsp/imxrt/boards/mimxrt1010_evk/mimxrt1010_evk.mex Normal file
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<?xml version="1.0" encoding= "UTF-8" ?>
<configuration name="MIMXRT1010-EVK" xsi:schemaLocation="http://mcuxpresso.nxp.com/XSD/mex_configuration_13 http://mcuxpresso.nxp.com/XSD/mex_configuration_13.xsd" uuid="f341eb24-9521-4127-8932-81692aeb76df" version="13" xmlns="http://mcuxpresso.nxp.com/XSD/mex_configuration_13" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<common>
<processor>MIMXRT1011xxxxx</processor>
<package>MIMXRT1011DAE5A</package>
<board>MIMXRT1010-EVK</board>
<board_revision>A</board_revision>
<mcu_data>ksdk2_0</mcu_data>
<cores selected="core0">
<core name="Cortex-M7F" id="core0" description="M7 core"/>
</cores>
<description></description>
</common>
<preferences>
<validate_boot_init_only>true</validate_boot_init_only>
<generate_extended_information>false</generate_extended_information>
<generate_code_modified_registers_only>false</generate_code_modified_registers_only>
<update_include_paths>true</update_include_paths>
<generate_registers_defines>false</generate_registers_defines>
</preferences>
<tools>
<pins name="Pins" version="13.1" enabled="true" update_project_code="true">
<generated_project_files>
<file path="board/pin_mux.c" update_enabled="true"/>
<file path="board/pin_mux.h" update_enabled="true"/>
</generated_project_files>
<pins_profile>
<processor_version>13.0.2</processor_version>
<pin_labels>
<pin_label pin_num="1" pin_signal="GPIO_11" label="GPIO_11" identifier="LED;USERLED;USER_LED"/>
</pin_labels>
<external_user_signals>
<properties/>
</external_user_signals>
<power_domains>
<power_domain name="NVCC_GPIO" value="3.3"/>
</power_domains>
</pins_profile>
<functions_list>
<function name="BOARD_InitPins">
<description>Configures pin routing and optionally pin electrical features.</description>
<options>
<callFromInitBoot>true</callFromInitBoot>
<coreID>core0</coreID>
<enableClock>true</enableClock>
</options>
<dependencies>
<dependency resourceType="Peripheral" resourceId="GPIO2" description="Peripheral GPIO2 is not initialized" problem_level="1" source="Pins:BOARD_InitPins">
<feature name="initialized" evaluation="equal">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="Peripheral" resourceId="LPUART1" description="Peripheral LPUART1 is not initialized" problem_level="1" source="Pins:BOARD_InitPins">
<feature name="initialized" evaluation="equal">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitPins">
<feature name="enabled" evaluation="equal" configuration="core0">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitPins">
<feature name="enabled" evaluation="equal" configuration="core0">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.igpio" description="Pins initialization requires the IGPIO Driver in the project." problem_level="2" source="Pins:BOARD_InitPins">
<feature name="enabled" evaluation="equal" configuration="core0">
<data>true</data>
</feature>
</dependency>
</dependencies>
<pins>
<pin peripheral="GPIO2" signal="gpio_io, 05" pin_num="70" pin_signal="GPIO_SD_05">
<pin_features>
<pin_feature name="direction" value="INPUT"/>
<pin_feature name="pull_keeper_select" value="Pull"/>
<pin_feature name="pull_up_down_config" value="Pull_Up_47K_Ohm"/>
</pin_features>
</pin>
<pin peripheral="GPIO1" signal="gpiomux_io, 11" pin_num="1" pin_signal="GPIO_11">
<pin_features>
<pin_feature name="identifier" value="USER_LED"/>
<pin_feature name="direction" value="OUTPUT"/>
</pin_features>
</pin>
<pin peripheral="LPUART1" signal="RXD" pin_num="3" pin_signal="GPIO_09"/>
<pin peripheral="LPUART1" signal="TXD" pin_num="2" pin_signal="GPIO_10"/>
</pins>
</function>
</functions_list>
</pins>
<clocks name="Clocks" version="11.0" enabled="true" update_project_code="true">
<generated_project_files>
<file path="board/clock_config.c" update_enabled="true"/>
<file path="board/clock_config.h" update_enabled="true"/>
</generated_project_files>
<clocks_profile>
<processor_version>13.0.2</processor_version>
</clocks_profile>
<clock_configurations>
<clock_configuration name="BOARD_BootClockRUN" id_prefix="" prefix_user_defined="false">
<description></description>
<options/>
<dependencies>
<dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtali" description="&apos;RTC_XTALI&apos; (Pins tool id: XTALOSC24M.rtc_xtali, Clocks tool id: XTALOSC24M.RTC_XTALI) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
<feature name="routed" evaluation="">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtali" description="&apos;RTC_XTALI&apos; (Pins tool id: XTALOSC24M.rtc_xtali, Clocks tool id: XTALOSC24M.RTC_XTALI) needs to have &apos;INPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
<feature name="direction" evaluation="">
<data>INPUT</data>
</feature>
</dependency>
<dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtalo" description="&apos;RTC_XTALO&apos; (Pins tool id: XTALOSC24M.rtc_xtalo, Clocks tool id: XTALOSC24M.RTC_XTALO) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
<feature name="routed" evaluation="">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtalo" description="&apos;RTC_XTALO&apos; (Pins tool id: XTALOSC24M.rtc_xtalo, Clocks tool id: XTALOSC24M.RTC_XTALO) needs to have &apos;OUTPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
<feature name="direction" evaluation="">
<data>OUTPUT</data>
</feature>
</dependency>
<dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtali" description="&apos;XTALI&apos; (Pins tool id: XTALOSC24M.xtali, Clocks tool id: XTALOSC24M.XTALI) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
<feature name="routed" evaluation="">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtali" description="&apos;XTALI&apos; (Pins tool id: XTALOSC24M.xtali, Clocks tool id: XTALOSC24M.XTALI) needs to have &apos;INPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
<feature name="direction" evaluation="">
<data>INPUT</data>
</feature>
</dependency>
<dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtalo" description="&apos;XTALO&apos; (Pins tool id: XTALOSC24M.xtalo, Clocks tool id: XTALOSC24M.XTALO) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
<feature name="routed" evaluation="">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtalo" description="&apos;XTALO&apos; (Pins tool id: XTALOSC24M.xtalo, Clocks tool id: XTALOSC24M.XTALO) needs to have &apos;OUTPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
<feature name="direction" evaluation="">
<data>OUTPUT</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN">
<feature name="enabled" evaluation="equal" configuration="core0">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Clocks initialization requires the IOMUXC Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN">
<feature name="enabled" evaluation="equal" configuration="core0">
<data>true</data>
</feature>
</dependency>
</dependencies>
<clock_sources>
<clock_source id="XTALOSC24M.RTC_OSC.outFreq" value="32.768 kHz" locked="false" enabled="true"/>
</clock_sources>
<clock_outputs>
<clock_output id="ADC_ALT_CLK.outFreq" value="40 MHz" locked="false" accuracy=""/>
<clock_output id="CKIL_SYNC_CLK_ROOT.outFreq" value="32.768 kHz" locked="false" accuracy=""/>
<clock_output id="CLK_1M.outFreq" value="1 MHz" locked="false" accuracy=""/>
<clock_output id="CLK_24M.outFreq" value="24 MHz" locked="false" accuracy=""/>
<clock_output id="CORE_CLK_ROOT.outFreq" value="500 MHz" locked="false" accuracy=""/>
<clock_output id="ENET_500M_REF_CLK.outFreq" value="500 MHz" locked="false" accuracy=""/>
<clock_output id="FLEXIO1_CLK_ROOT.outFreq" value="30 MHz" locked="false" accuracy=""/>
<clock_output id="FLEXSPI_CLK_ROOT.outFreq" value="132 MHz" locked="false" accuracy=""/>
<clock_output id="GPT1_ipg_clk_highfreq.outFreq" value="62.5 MHz" locked="false" accuracy=""/>
<clock_output id="GPT2_ipg_clk_highfreq.outFreq" value="62.5 MHz" locked="false" accuracy=""/>
<clock_output id="IPG_CLK_ROOT.outFreq" value="125 MHz" locked="false" accuracy=""/>
<clock_output id="LPI2C_CLK_ROOT.outFreq" value="60 MHz" locked="false" accuracy=""/>
<clock_output id="LPSPI_CLK_ROOT.outFreq" value="105.6 MHz" locked="false" accuracy=""/>
<clock_output id="MQS_MCLK.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
<clock_output id="PERCLK_CLK_ROOT.outFreq" value="62.5 MHz" locked="false" accuracy=""/>
<clock_output id="SAI1_CLK_ROOT.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
<clock_output id="SAI1_MCLK1.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
<clock_output id="SAI1_MCLK2.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
<clock_output id="SAI1_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/>
<clock_output id="SAI3_CLK_ROOT.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
<clock_output id="SAI3_MCLK1.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
<clock_output id="SAI3_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/>
<clock_output id="SPDIF0_CLK_ROOT.outFreq" value="30 MHz" locked="false" accuracy=""/>
<clock_output id="TRACE_CLK_ROOT.outFreq" value="132 MHz" locked="false" accuracy=""/>
<clock_output id="UART_CLK_ROOT.outFreq" value="80 MHz" locked="false" accuracy=""/>
<clock_output id="USBPHY_CLK.outFreq" value="480 MHz" locked="false" accuracy=""/>
</clock_outputs>
<clock_settings>
<setting id="CCM.ADC_ACLK_PODF.scale" value="12" locked="true"/>
<setting id="CCM.AHB_PODF.scale" value="1" locked="true"/>
<setting id="CCM.FLEXSPI_PODF.scale" value="4" locked="true"/>
<setting id="CCM.IPG_PODF.scale" value="4" locked="false"/>
<setting id="CCM.LPSPI_PODF.scale" value="5" locked="false"/>
<setting id="CCM.PERCLK_PODF.scale" value="2" locked="true"/>
<setting id="CCM.PRE_PERIPH_CLK_SEL.sel" value="CCM_ANALOG.ENET_500M_REF_CLK" locked="false"/>
<setting id="CCM.SAI1_CLK_SEL.sel" value="CCM_ANALOG.PLL3_PFD2_CLK" locked="false"/>
<setting id="CCM.SAI3_CLK_SEL.sel" value="CCM_ANALOG.PLL3_PFD2_CLK" locked="false"/>
<setting id="CCM.TRACE_CLK_SEL.sel" value="CCM_ANALOG.PLL2_MAIN_CLK" locked="false"/>
<setting id="CCM_ANALOG.PLL2.denom" value="1" locked="false"/>
<setting id="CCM_ANALOG.PLL2.num" value="0" locked="false"/>
<setting id="CCM_ANALOG.PLL2_BYPASS.sel" value="CCM_ANALOG.PLL2_OUT_CLK" locked="false"/>
<setting id="CCM_ANALOG.PLL2_PFD0_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD0" locked="false"/>
<setting id="CCM_ANALOG.PLL2_PFD1_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD1" locked="false"/>
<setting id="CCM_ANALOG.PLL2_PFD2_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD2" locked="false"/>
<setting id="CCM_ANALOG.PLL2_PFD2_DIV.scale" value="18" locked="true"/>
<setting id="CCM_ANALOG.PLL2_PFD2_MUL.scale" value="18" locked="true"/>
<setting id="CCM_ANALOG.PLL2_PFD3_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD3" locked="false"/>
<setting id="CCM_ANALOG.PLL2_PFD3_DIV.scale" value="18" locked="true"/>
<setting id="CCM_ANALOG.PLL2_PFD3_MUL.scale" value="18" locked="true"/>
<setting id="CCM_ANALOG.PLL3_BYPASS.sel" value="CCM_ANALOG.PLL3" locked="false"/>
<setting id="CCM_ANALOG.PLL3_PFD0_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD0" locked="false"/>
<setting id="CCM_ANALOG.PLL3_PFD0_DIV.scale" value="22" locked="true"/>
<setting id="CCM_ANALOG.PLL3_PFD0_MUL.scale" value="18" locked="true"/>
<setting id="CCM_ANALOG.PLL3_PFD1_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD1" locked="false"/>
<setting id="CCM_ANALOG.PLL3_PFD2_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD2" locked="false"/>
<setting id="CCM_ANALOG.PLL3_PFD3_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD3" locked="false"/>
<setting id="CCM_ANALOG.PLL3_PFD3_DIV.scale" value="18" locked="true"/>
<setting id="CCM_ANALOG.PLL3_PFD3_MUL.scale" value="18" locked="true"/>
<setting id="CCM_ANALOG.PLL6_BYPASS.sel" value="CCM_ANALOG.PLL6" locked="false"/>
<setting id="CCM_ANALOG_PLL_USB1_EN_USB_CLKS_CFG" value="Enabled" locked="false"/>
<setting id="CCM_ANALOG_PLL_USB1_EN_USB_CLKS_OUT_CFG" value="Enabled" locked="false"/>
<setting id="CCM_ANALOG_PLL_USB1_POWER_CFG" value="Yes" locked="false"/>
</clock_settings>
<called_from_default_init>true</called_from_default_init>
</clock_configuration>
</clock_configurations>
</clocks>
<dcdx name="DCDx" version="2.0" enabled="false" update_project_code="true">
<generated_project_files/>
<dcdx_profile>
<processor_version>0.0.0</processor_version>
</dcdx_profile>
<dcdx_configurations/>
</dcdx>
<periphs name="Peripherals" version="12.0" enabled="false" update_project_code="true">
<generated_project_files/>
<peripherals_profile>
<processor_version>13.0.2</processor_version>
</peripherals_profile>
<functional_groups>
<functional_group name="BOARD_InitPeripherals" uuid="5e519eed-bd94-4950-84de-0f29de85bcea" called_from_default_init="true" id_prefix="" core="core0">
<description></description>
<options/>
<dependencies/>
<instances>
<instance name="COMBO_SENSOR" uuid="2342e373-ea2e-4bed-8aa4-bd33509155f6" type="lpi2c" type_id="lpi2c_6b71962515c3208facfccd030afebc98" mode="master" peripheral="LPI2C1" enabled="false" comment="" custom_name_enabled="true" editing_lock="false">
<config_set name="main" quick_selection="qs_interrupt">
<setting name="clockSource" value="Lpi2cClock"/>
<setting name="clockSourceFreq" value="BOARD_BootClockRUN"/>
</config_set>
<config_set name="interrupt_vector"/>
<config_set name="master" quick_selection="qs_master_transfer">
<setting name="mode" value="transfer"/>
<struct name="config">
<setting name="enableMaster" value="true"/>
<setting name="enableDoze" value="true"/>
<setting name="debugEnable" value="false"/>
<setting name="ignoreAck" value="false"/>
<setting name="pinConfig" value="kLPI2C_2PinOpenDrain"/>
<setting name="baudRate_Hz" value="100000"/>
<setting name="busIdleTimeout_ns" value="0"/>
<setting name="pinLowTimeout_ns" value="0"/>
<setting name="sdaGlitchFilterWidth_ns" value="0"/>
<setting name="sclGlitchFilterWidth_ns" value="0"/>
<struct name="hostRequest">
<setting name="enable" value="false"/>
<setting name="source" value="kLPI2C_HostRequestExternalPin"/>
<setting name="polarity" value="kLPI2C_HostRequestPinActiveHigh"/>
</struct>
<set name="edmaRequestSources">
<selected/>
</set>
</struct>
<struct name="transfer">
<setting name="blocking" value="false"/>
<setting name="enable_custom_handle" value="false"/>
<struct name="callback">
<setting name="name" value=""/>
<setting name="userData" value=""/>
</struct>
<set name="flags">
<selected/>
</set>
<setting name="slaveAddress" value="0"/>
<setting name="direction" value="kLPI2C_Write"/>
<setting name="subaddress" value="0"/>
<setting name="subaddressSize" value="1"/>
<setting name="blocking_buffer" value="false"/>
<setting name="enable_custom_buffer" value="false"/>
<setting name="dataSize" value="1"/>
</struct>
</config_set>
</instance>
<instance name="DEBUG_UART" uuid="0d9274fe-8f49-48a8-8e6a-8c3ac009384d" type="lpuart" type_id="lpuart_bf01db7d964092f3cf860852cba17f7e" mode="polling" peripheral="LPUART1" enabled="false" comment="" custom_name_enabled="true" editing_lock="false">
<config_set name="lpuartConfig_t" quick_selection="QuickSelection1">
<struct name="lpuartConfig">
<setting name="clockSource" value="LpuartClock"/>
<setting name="lpuartSrcClkFreq" value="ClocksTool_DefaultInit"/>
<setting name="baudRate_Bps" value="115200"/>
<setting name="parityMode" value="kLPUART_ParityDisabled"/>
<setting name="dataBitsCount" value="kLPUART_EightDataBits"/>
<setting name="isMsb" value="false"/>
<setting name="stopBitCount" value="kLPUART_OneStopBit"/>
<setting name="enableMatchAddress1" value="false"/>
<setting name="matchAddress1" value="0"/>
<setting name="enableMatchAddress2" value="false"/>
<setting name="matchAddress2" value="0"/>
<setting name="txFifoWatermark" value="0"/>
<setting name="rxFifoWatermark" value="1"/>
<setting name="enableRxRTS" value="false"/>
<setting name="enableTxCTS" value="false"/>
<setting name="txCtsSource" value="kLPUART_CtsSourcePin"/>
<setting name="txCtsConfig" value="kLPUART_CtsSampleAtStart"/>
<setting name="rxIdleType" value="kLPUART_IdleTypeStartBit"/>
<setting name="rxIdleConfig" value="kLPUART_IdleCharacter1"/>
<setting name="enableTx" value="true"/>
<setting name="enableRx" value="true"/>
</struct>
</config_set>
</instance>
<instance name="USER_BUTTON" uuid="6c9e57cc-d98c-4f6d-bf94-3920a8fd474e" type="igpio" type_id="igpio_b1c1fa279aa7069dca167502b8589cb7" mode="GPIO" peripheral="GPIO2" enabled="false" comment="" custom_name_enabled="true" editing_lock="false">
<config_set name="fsl_gpio">
<setting name="enable_irq_comb_0_15" value="false"/>
<struct name="gpio_interrupt_comb_0_15">
<setting name="IRQn" value="GPIO2_Combined_0_15_IRQn"/>
<setting name="enable_interrrupt" value="enabled"/>
<setting name="enable_priority" value="false"/>
<setting name="priority" value="0"/>
<setting name="enable_custom_name" value="false"/>
</struct>
</config_set>
</instance>
<instance name="USER_LED" uuid="0f7a142d-ad6c-4e47-a2a3-015e90afa37b" type="igpio" type_id="igpio_b1c1fa279aa7069dca167502b8589cb7" mode="GPIO" peripheral="GPIO1" enabled="false" comment="" custom_name_enabled="true" editing_lock="false">
<config_set name="fsl_gpio">
<setting name="enable_irq_comb_0_15" value="false"/>
<struct name="gpio_interrupt_comb_0_15">
<setting name="IRQn" value="GPIO1_Combined_0_15_IRQn"/>
<setting name="enable_interrrupt" value="enabled"/>
<setting name="enable_priority" value="false"/>
<setting name="priority" value="0"/>
<setting name="enable_custom_name" value="false"/>
</struct>
<setting name="enable_irq_comb_16_31" value="false"/>
<struct name="gpio_interrupt_comb_16_31">
<setting name="IRQn" value="GPIO1_Combined_16_31_IRQn"/>
<setting name="enable_interrrupt" value="enabled"/>
<setting name="enable_priority" value="false"/>
<setting name="priority" value="0"/>
<setting name="enable_custom_name" value="false"/>
</struct>
</config_set>
</instance>
<instance name="NVIC" uuid="2a54e709-5718-4b89-8b7b-71cefb418658" type="nvic" type_id="nvic_57b5eef3774cc60acaede6f5b8bddc67" mode="general" peripheral="NVIC" enabled="true" comment="" custom_name_enabled="false" editing_lock="false">
<config_set name="nvic">
<array name="interrupt_table"/>
<array name="interrupts"/>
</config_set>
</instance>
</instances>
</functional_group>
</functional_groups>
<components>
<component name="system" uuid="991327ca-3ad0-49d1-aff3-37b7734338db" type_id="system">
<config_set_global name="global_system_definitions">
<setting name="user_definitions" value=""/>
<setting name="user_includes" value=""/>
</config_set_global>
</component>
<component name="msg" uuid="3e46e698-099c-4180-92f5-2af1abbb93a5" type_id="msg">
<config_set_global name="global_messages"/>
</component>
<component name="gpio_adapter_common" uuid="27e43a4b-bddb-4db2-8f6b-3f6a73008a27" type_id="gpio_adapter_common_57579b9ac814fe26bf95df0a384c36b6">
<config_set_global name="global_gpio_adapter_common" quick_selection="default"/>
</component>
<component name="generic_uart" uuid="c946fe99-5d76-4cca-8be0-dea3c7861b68" type_id="generic_uart_8cae00565451cf2346eb1b8c624e73a6">
<config_set_global name="global_uart"/>
</component>
<component name="generic_can" uuid="c18a4299-93be-44e8-b563-3985b3e264c5" type_id="generic_can_1bfdd78b1af214566c1f23cf6a582d80">
<config_set_global name="global_can"/>
</component>
<component name="uart_cmsis_common" uuid="6149366a-a07f-40a7-8909-00ba459085a7" type_id="uart_cmsis_common_9cb8e302497aa696fdbb5a4fd622c2a8">
<config_set_global name="global_USART_CMSIS_common" quick_selection="default"/>
</component>
<component name="generic_enet" uuid="15cc4d18-2002-44a4-b7e7-f681a046f26c" type_id="generic_enet_74db5c914f0ddbe47d86af40cb77a619">
<config_set_global name="global_enet"/>
</component>
</components>
</periphs>
<tee name="TEE" version="4.0" enabled="false" update_project_code="true">
<generated_project_files/>
<tee_profile>
<processor_version>0.0.0</processor_version>
</tee_profile>
</tee>
</tools>
</configuration>

15
managed_components/espressif__tinyusb/hw/bsp/imxrt/boards/mimxrt1015_evk/board.cmake Normal file
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set(MCU_VARIANT MIMXRT1015)
set(JLINK_DEVICE MIMXRT1015DAF5A)
set(PYOCD_TARGET mimxrt1015)
set(NXPLINK_DEVICE MIMXRT1015xxxxx:EVK-MIMXRT1015)
function(update_board TARGET)
target_sources(${TARGET} PUBLIC
${CMAKE_CURRENT_FUNCTION_LIST_DIR}/evkmimxrt1015_flexspi_nor_config.c
)
target_compile_definitions(${TARGET} PUBLIC
CPU_MIMXRT1015DAF5A
CFG_EXAMPLE_VIDEO_READONLY
)
endfunction()

59
managed_components/espressif__tinyusb/hw/bsp/imxrt/boards/mimxrt1015_evk/board.h Normal file
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/*
* The MIT License (MIT)
*
* Copyright (c) 2019, Ha Thach (tinyusb.org)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* This file is part of the TinyUSB stack.
*/
/* metadata:
name: i.MX RT1015 Evaluation Kit
url: https://www.nxp.com/design/design-center/development-boards-and-designs/MIMXRT1015-EVK
*/
#ifndef BOARD_MIMXRT1015_EVK_H_
#define BOARD_MIMXRT1015_EVK_H_
// required since iMXRT MCUX-SDK include this file for board size
#define BOARD_FLASH_SIZE (0x1000000U)
// LED
#define LED_PINMUX IOMUXC_GPIO_SD_B1_01_GPIO3_IO21
#define LED_PORT BOARD_INITPINS_USER_LED_PERIPHERAL
#define LED_PIN BOARD_INITPINS_USER_LED_CHANNEL
#define LED_STATE_ON 0
// SW8 button
#define BUTTON_PINMUX IOMUXC_GPIO_EMC_09_GPIO2_IO09
#define BUTTON_PORT BOARD_INITPINS_USER_BUTTON_GPIO
#define BUTTON_PIN BOARD_INITPINS_USER_BUTTON_GPIO_PIN
#define BUTTON_STATE_ACTIVE 0
// UART
#define UART_PORT LPUART1
#define UART_CLK_ROOT BOARD_BOOTCLOCKRUN_UART_CLK_ROOT
#define UART_RX_PINMUX IOMUXC_GPIO_AD_B0_07_LPUART1_RX
#define UART_TX_PINMUX IOMUXC_GPIO_AD_B0_06_LPUART1_TX
static inline void BOARD_ConfigMPU(void) {
}
#endif

11
managed_components/espressif__tinyusb/hw/bsp/imxrt/boards/mimxrt1015_evk/board.mk Normal file
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@@ -0,0 +1,11 @@
CFLAGS += -DCPU_MIMXRT1015DAF5A -DCFG_EXAMPLE_VIDEO_READONLY
MCU_VARIANT = MIMXRT1015
# For flash-jlink target
JLINK_DEVICE = MIMXRT1015DAF5A
# For flash-pyocd target
PYOCD_TARGET = mimxrt1015
# flash using pyocd
flash: flash-pyocd

357
managed_components/espressif__tinyusb/hw/bsp/imxrt/boards/mimxrt1015_evk/board/clock_config.c Normal file
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/*
* How to setup clock using clock driver functions:
*
* 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock.
*
* 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock.
*
* 3. Call CLOCK_SetMux() to configure corresponding clock source for target clock out.
*
* 4. Call CLOCK_SetDiv() to configure corresponding clock divider for target clock out.
*
* 5. Call CLOCK_SetXtalFreq() to set XTAL frequency based on board settings.
*
*/
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!GlobalInfo
product: Clocks v15.0
processor: MIMXRT1015xxxxx
package_id: MIMXRT1015DAF5A
mcu_data: ksdk2_0
processor_version: 24.12.10
board: MIMXRT1015-EVK
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
#include "clock_config.h"
#include "fsl_iomuxc.h"
/*******************************************************************************
* Definitions
******************************************************************************/
/*******************************************************************************
* Variables
******************************************************************************/
/*******************************************************************************
************************ BOARD_InitBootClocks function ************************
******************************************************************************/
void BOARD_InitBootClocks(void)
{
BOARD_BootClockRUN();
}
/*******************************************************************************
********************** Configuration BOARD_BootClockRUN ***********************
******************************************************************************/
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!Configuration
name: BOARD_BootClockRUN
called_from_default_init: true
outputs:
- {id: AHB_CLK_ROOT.outFreq, value: 500 MHz}
- {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz}
- {id: CLK_1M.outFreq, value: 1 MHz}
- {id: CLK_24M.outFreq, value: 24 MHz}
- {id: ENET_500M_REF_CLK.outFreq, value: 500 MHz}
- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz}
- {id: FLEXSPI_CLK_ROOT.outFreq, value: 2160/11 MHz}
- {id: GPT1_ipg_clk_highfreq.outFreq, value: 62.5 MHz}
- {id: GPT2_ipg_clk_highfreq.outFreq, value: 62.5 MHz}
- {id: IPG_CLK_ROOT.outFreq, value: 125 MHz}
- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz}
- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz}
- {id: MQS_MCLK.outFreq, value: 1080/17 MHz}
- {id: PERCLK_CLK_ROOT.outFreq, value: 62.5 MHz}
- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz}
- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz}
- {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz}
- {id: SAI1_MCLK3.outFreq, value: 30 MHz}
- {id: SAI2_CLK_ROOT.outFreq, value: 1080/17 MHz}
- {id: SAI2_MCLK1.outFreq, value: 1080/17 MHz}
- {id: SAI2_MCLK3.outFreq, value: 30 MHz}
- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz}
- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz}
- {id: SAI3_MCLK3.outFreq, value: 30 MHz}
- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz}
- {id: TRACE_CLK_ROOT.outFreq, value: 352/3 MHz}
- {id: UART_CLK_ROOT.outFreq, value: 80 MHz}
- {id: USBPHY1_CLK.outFreq, value: 480 MHz}
settings:
- {id: CCM.AHB_PODF.scale, value: '1', locked: true}
- {id: CCM.ARM_PODF.scale, value: '1', locked: true}
- {id: CCM.CLKO2_SEL.sel, value: CCM.LPI2C_CLK_ROOT}
- {id: CCM.FLEXSPI_PODF.scale, value: '2', locked: true}
- {id: CCM.FLEXSPI_SEL.sel, value: CCM_ANALOG.PLL3_PFD0_CLK}
- {id: CCM.IPG_PODF.scale, value: '4'}
- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true}
- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true}
- {id: CCM.PRE_PERIPH_CLK_SEL.sel, value: CCM.ARM_PODF}
- {id: CCM.SEMC_PODF.scale, value: '2'}
- {id: CCM.TRACE_PODF.scale, value: '3', locked: true}
- {id: CCM_ANALOG.PLL2.denom, value: '1', locked: true}
- {id: CCM_ANALOG.PLL2.num, value: '0', locked: true}
- {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK}
- {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0}
- {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1}
- {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2}
- {id: CCM_ANALOG.PLL2_PFD2_DIV.scale, value: '18', locked: true}
- {id: CCM_ANALOG.PLL2_PFD2_MUL.scale, value: '18', locked: true}
- {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3}
- {id: CCM_ANALOG.PLL2_PFD3_DIV.scale, value: '18', locked: true}
- {id: CCM_ANALOG.PLL2_PFD3_MUL.scale, value: '18', locked: true}
- {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3}
- {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0}
- {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '22', locked: true}
- {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true}
- {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1}
- {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2}
- {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3}
- {id: CCM_ANALOG.PLL3_PFD3_DIV.scale, value: '18', locked: true}
- {id: CCM_ANALOG.PLL3_PFD3_MUL.scale, value: '18', locked: true}
- {id: CCM_ANALOG.PLL4.denom, value: '50'}
- {id: CCM_ANALOG.PLL4.div, value: '47'}
- {id: CCM_ANALOG.PLL6_BYPASS.sel, value: CCM_ANALOG.PLL6}
- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_CFG, value: Enabled}
- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_OUT_CFG, value: Enabled}
- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'}
sources:
- {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/*******************************************************************************
* Variables for BOARD_BootClockRUN configuration
******************************************************************************/
const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN =
{
.loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */
.numerator = 0, /* 30 bit numerator of fractional loop divider */
.denominator = 1, /* 30 bit denominator of fractional loop divider */
.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
};
const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN =
{
.loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */
.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
};
const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN =
{
.enableClkOutput500M = true, /* Enable the PLL providing the ENET 500MHz reference clock */
.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
};
/*******************************************************************************
* Code for BOARD_BootClockRUN configuration
******************************************************************************/
void BOARD_BootClockRUN(void)
{
/* Init RTC OSC clock frequency. */
CLOCK_SetRtcXtalFreq(32768U);
/* Enable 1MHz clock output. */
XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK;
/* Use free 1MHz clock output. */
XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK;
/* Set XTAL 24MHz clock frequency. */
CLOCK_SetXtalFreq(24000000U);
/* Enable XTAL 24MHz clock source. */
CLOCK_InitExternalClk(0);
/* Enable internal RC. */
CLOCK_InitRcOsc24M();
/* Switch clock source to external OSC. */
CLOCK_SwitchOsc(kCLOCK_XtalOsc);
/* Set Oscillator ready counter value. */
CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127);
/* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */
CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */
CLOCK_SetMux(kCLOCK_PeriphMux, 1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */
/* Setting the VDD_SOC to 1.25V. It is necessary to config AHB to 500Mhz. */
DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x12);
/* Waiting for DCDC_STS_DC_OK bit is asserted */
while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0))
{
}
/* Set AHB_PODF. */
CLOCK_SetDiv(kCLOCK_AhbDiv, 0);
/* Disable IPG clock gate. */
CLOCK_DisableClock(kCLOCK_Adc1);
CLOCK_DisableClock(kCLOCK_Xbar1);
CLOCK_DisableClock(kCLOCK_Xbar2);
/* Set IPG_PODF. */
CLOCK_SetDiv(kCLOCK_IpgDiv, 3);
/* Set ARM_PODF. */
CLOCK_SetDiv(kCLOCK_ArmDiv, 0);
/* Set PERIPH_CLK2_PODF. */
CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0);
/* Disable PERCLK clock gate. */
CLOCK_DisableClock(kCLOCK_Gpt1);
CLOCK_DisableClock(kCLOCK_Gpt1S);
CLOCK_DisableClock(kCLOCK_Gpt2);
CLOCK_DisableClock(kCLOCK_Gpt2S);
CLOCK_DisableClock(kCLOCK_Pit);
/* Set PERCLK_PODF. */
CLOCK_SetDiv(kCLOCK_PerclkDiv, 1);
/* Set SEMC_PODF. */
CLOCK_SetDiv(kCLOCK_SemcDiv, 1);
/* Set Semc alt clock source. */
CLOCK_SetMux(kCLOCK_SemcAltMux, 0);
/* Set Semc clock source. */
CLOCK_SetMux(kCLOCK_SemcMux, 0);
/* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
* With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
* Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
/* Disable Flexspi clock gate. */
CLOCK_DisableClock(kCLOCK_FlexSpi);
/* Set FLEXSPI_PODF. */
CLOCK_SetDiv(kCLOCK_FlexspiDiv, 1);
/* Set Flexspi clock source. */
CLOCK_SetMux(kCLOCK_FlexspiMux, 3);
#endif
/* Disable LPSPI clock gate. */
CLOCK_DisableClock(kCLOCK_Lpspi1);
CLOCK_DisableClock(kCLOCK_Lpspi2);
/* Set LPSPI_PODF. */
CLOCK_SetDiv(kCLOCK_LpspiDiv, 4);
/* Set Lpspi clock source. */
CLOCK_SetMux(kCLOCK_LpspiMux, 2);
/* Disable TRACE clock gate. */
CLOCK_DisableClock(kCLOCK_Trace);
/* Set TRACE_PODF. */
CLOCK_SetDiv(kCLOCK_TraceDiv, 2);
/* Set Trace clock source. */
CLOCK_SetMux(kCLOCK_TraceMux, 2);
/* Disable SAI1 clock gate. */
CLOCK_DisableClock(kCLOCK_Sai1);
/* Set SAI1_CLK_PRED. */
CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3);
/* Set SAI1_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_Sai1Div, 1);
/* Set Sai1 clock source. */
CLOCK_SetMux(kCLOCK_Sai1Mux, 0);
/* Disable SAI2 clock gate. */
CLOCK_DisableClock(kCLOCK_Sai2);
/* Set SAI2_CLK_PRED. */
CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3);
/* Set SAI2_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_Sai2Div, 1);
/* Set Sai2 clock source. */
CLOCK_SetMux(kCLOCK_Sai2Mux, 0);
/* Disable SAI3 clock gate. */
CLOCK_DisableClock(kCLOCK_Sai3);
/* Set SAI3_CLK_PRED. */
CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3);
/* Set SAI3_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_Sai3Div, 1);
/* Set Sai3 clock source. */
CLOCK_SetMux(kCLOCK_Sai3Mux, 0);
/* Disable Lpi2c clock gate. */
CLOCK_DisableClock(kCLOCK_Lpi2c1);
CLOCK_DisableClock(kCLOCK_Lpi2c2);
/* Set LPI2C_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0);
/* Set Lpi2c clock source. */
CLOCK_SetMux(kCLOCK_Lpi2cMux, 0);
/* Disable UART clock gate. */
CLOCK_DisableClock(kCLOCK_Lpuart1);
CLOCK_DisableClock(kCLOCK_Lpuart2);
CLOCK_DisableClock(kCLOCK_Lpuart3);
CLOCK_DisableClock(kCLOCK_Lpuart4);
/* Set UART_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_UartDiv, 0);
/* Set Uart clock source. */
CLOCK_SetMux(kCLOCK_UartMux, 0);
/* Disable SPDIF clock gate. */
CLOCK_DisableClock(kCLOCK_Spdif);
/* Set SPDIF0_CLK_PRED. */
CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1);
/* Set SPDIF0_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_Spdif0Div, 7);
/* Set Spdif clock source. */
CLOCK_SetMux(kCLOCK_SpdifMux, 3);
/* Disable Flexio1 clock gate. */
CLOCK_DisableClock(kCLOCK_Flexio1);
/* Set FLEXIO1_CLK_PRED. */
CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1);
/* Set FLEXIO1_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_Flexio1Div, 7);
/* Set Flexio1 clock source. */
CLOCK_SetMux(kCLOCK_Flexio1Mux, 3);
/* Set Pll3 sw clock source. */
CLOCK_SetMux(kCLOCK_Pll3SwMux, 0);
/* Init System PLL. */
CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN);
/* Init System pfd0. */
CLOCK_InitSysPfd(kCLOCK_Pfd0, 27);
/* Init System pfd1. */
CLOCK_InitSysPfd(kCLOCK_Pfd1, 16);
/* Init System pfd2. */
CLOCK_InitSysPfd(kCLOCK_Pfd2, 18);
/* Init System pfd3. */
CLOCK_InitSysPfd(kCLOCK_Pfd3, 18);
/* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
* With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
* Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
/* Init Usb1 PLL. */
CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN);
/* Init Usb1 pfd0. */
CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 22);
/* Init Usb1 pfd1. */
CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16);
/* Init Usb1 pfd2. */
CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17);
/* Init Usb1 pfd3. */
CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 18);
#endif
/* DeInit Audio PLL. */
CLOCK_DeinitAudioPll();
/* Bypass Audio PLL. */
CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1);
/* Set divider for Audio PLL. */
CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK;
CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK;
/* Enable Audio PLL output. */
CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK;
/* Init Enet PLL. */
CLOCK_InitEnetPll(&enetPllConfig_BOARD_BootClockRUN);
/* Set preperiph clock source. */
CLOCK_SetMux(kCLOCK_PrePeriphMux, 3);
/* Set periph clock source. */
CLOCK_SetMux(kCLOCK_PeriphMux, 0);
/* Set periph clock2 clock source. */
CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
/* Set per clock source. */
CLOCK_SetMux(kCLOCK_PerclkMux, 0);
/* Set clock out1 divider. */
CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0);
/* Set clock out1 source. */
CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1);
/* Set clock out2 divider. */
CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0);
/* Set clock out2 source. */
CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(6);
/* Set clock out1 drives clock out1. */
CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK;
/* Disable clock out1. */
CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK;
/* Disable clock out2. */
CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK;
/* Set SAI1 MCLK1 clock source. */
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0);
/* Set SAI1 MCLK2 clock source. */
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0);
/* Set SAI1 MCLK3 clock source. */
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0);
/* Set SAI2 MCLK3 clock source. */
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0);
/* Set SAI3 MCLK3 clock source. */
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
/* Set MQS configuration. */
IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0);
/* Set GPT1 High frequency reference clock source. */
IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK;
/* Set GPT2 High frequency reference clock source. */
IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK;
/* Set SystemCoreClock variable. */
SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
}

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#ifndef _CLOCK_CONFIG_H_
#define _CLOCK_CONFIG_H_
#include "fsl_common.h"
/*******************************************************************************
* Definitions
******************************************************************************/
#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */
#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */
/*******************************************************************************
************************ BOARD_InitBootClocks function ************************
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/
/*!
* @brief This function executes default configuration of clocks.
*
*/
void BOARD_InitBootClocks(void);
#if defined(__cplusplus)
}
#endif /* __cplusplus*/
/*******************************************************************************
********************** Configuration BOARD_BootClockRUN ***********************
******************************************************************************/
/*******************************************************************************
* Definitions for BOARD_BootClockRUN configuration
******************************************************************************/
#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 500000000U /*!< Core clock frequency: 500000000Hz */
/* Clock outputs (values are in Hz): */
#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT 500000000UL /* Clock consumers of AHB_CLK_ROOT output : AIPSTZ1, AIPSTZ2, AIPSTZ3, AIPSTZ4, ARM, FLEXSPI */
#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL /* Clock consumers of CKIL_SYNC_CLK_ROOT output : CSU, EWM, GPT1, GPT2, KPP, PIT, RTWDOG, SNVS, SPDIF, TEMPMON, USB, WDOG1, WDOG2 */
#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL /* Clock consumers of CLKO1_CLK output : N/A */
#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL /* Clock consumers of CLKO2_CLK output : N/A */
#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL /* Clock consumers of CLK_1M output : EWM, RTWDOG */
#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL /* Clock consumers of CLK_24M output : GPT1, GPT2 */
#define BOARD_BOOTCLOCKRUN_ENET_500M_REF_CLK 500000000UL /* Clock consumers of ENET_500M_REF_CLK output : N/A */
#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL /* Clock consumers of FLEXIO1_CLK_ROOT output : FLEXIO1 */
#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 196363636UL /* Clock consumers of FLEXSPI_CLK_ROOT output : FLEXSPI */
#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 62500000UL /* Clock consumers of GPT1_ipg_clk_highfreq output : GPT1 */
#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 62500000UL /* Clock consumers of GPT2_ipg_clk_highfreq output : GPT2 */
#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 125000000UL /* Clock consumers of IPG_CLK_ROOT output : ADC1, ADC_ETC, AOI, ARM, BEE, CCM, CSU, DCDC, DCP, DMA0, DMAMUX, ENC1, EWM, FLEXIO1, FLEXRAM, FLEXSPI, GPC, GPIO1, GPIO2, GPIO3, GPIO5, IOMUXC, KPP, LPI2C1, LPI2C2, LPSPI1, LPSPI2, LPUART1, LPUART2, LPUART3, LPUART4, NVIC, OCOTP, PWM1, RTWDOG, SAI1, SAI2, SAI3, SNVS, SPDIF, SRC, TEMPMON, TMR1, TRNG, USB, WDOG1, WDOG2, XBARA, XBARB */
#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL /* Clock consumers of LPI2C_CLK_ROOT output : LPI2C1, LPI2C2 */
#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL /* Clock consumers of LPSPI_CLK_ROOT output : LPSPI1, LPSPI2 */
#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL /* Clock consumers of MQS_MCLK output : N/A */
#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 62500000UL /* Clock consumers of PERCLK_CLK_ROOT output : GPT1, GPT2, PIT */
#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL /* Clock consumers of SAI1_CLK_ROOT output : N/A */
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL /* Clock consumers of SAI1_MCLK1 output : SAI1 */
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL /* Clock consumers of SAI1_MCLK2 output : SAI1 */
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL /* Clock consumers of SAI1_MCLK3 output : SAI1 */
#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 63529411UL /* Clock consumers of SAI2_CLK_ROOT output : N/A */
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 63529411UL /* Clock consumers of SAI2_MCLK1 output : SAI2 */
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL /* Clock consumers of SAI2_MCLK2 output : SAI2 */
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 30000000UL /* Clock consumers of SAI2_MCLK3 output : SAI2 */
#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL /* Clock consumers of SAI3_CLK_ROOT output : N/A */
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL /* Clock consumers of SAI3_MCLK1 output : SAI3 */
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL /* Clock consumers of SAI3_MCLK2 output : SAI3 */
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL /* Clock consumers of SAI3_MCLK3 output : SAI3 */
#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL /* Clock consumers of SPDIF0_CLK_ROOT output : SPDIF */
#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL /* Clock consumers of SPDIF0_EXTCLK_OUT output : SPDIF */
#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 117333333UL /* Clock consumers of TRACE_CLK_ROOT output : ARM */
#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL /* Clock consumers of UART_CLK_ROOT output : LPUART1, LPUART2, LPUART3, LPUART4 */
#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK 480000000UL /* Clock consumers of USBPHY1_CLK output : TEMPMON, USB */
/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration.
*/
extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN;
/*! @brief Sys PLL for BOARD_BootClockRUN configuration.
*/
extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN;
/*! @brief Enet PLL set for BOARD_BootClockRUN configuration.
*/
extern const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN;
/*******************************************************************************
* API for BOARD_BootClockRUN configuration
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/
/*!
* @brief This function executes configuration of clocks.
*
*/
void BOARD_BootClockRUN(void);
#if defined(__cplusplus)
}
#endif /* __cplusplus*/
#endif /* _CLOCK_CONFIG_H_ */

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/***********************************************************************************************************************
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
**********************************************************************************************************************/
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!GlobalInfo
product: Pins v17.0
processor: MIMXRT1015xxxxx
package_id: MIMXRT1015DAF5A
mcu_data: ksdk2_0
processor_version: 24.12.10
board: MIMXRT1015-EVK
external_user_signals: {}
pin_labels:
- {pin_num: '21', pin_signal: GPIO_SD_B1_01, label: GPIO SD_B1_01, identifier: USER_LED}
power_domains: {NVCC_GPIO: '3.3'}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
#include "fsl_common.h"
#include "fsl_iomuxc.h"
#include "fsl_gpio.h"
#include "pin_mux.h"
/* FUNCTION ************************************************************************************************************
*
* Function Name : BOARD_InitBootPins
* Description : Calls initialization functions.
*
* END ****************************************************************************************************************/
void BOARD_InitBootPins(void) {
BOARD_InitPins();
BOARD_InitDEBUG_UARTPins();
}
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
BOARD_InitPins:
- options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'}
- pin_list:
- {pin_num: '1', peripheral: GPIO2, signal: 'gpio_io, 09', pin_signal: GPIO_EMC_09, direction: INPUT, pull_keeper_select: Pull, pull_up_down_config: Pull_Up_47K_Ohm}
- {pin_num: '21', peripheral: GPIO3, signal: 'gpio_io, 21', pin_signal: GPIO_SD_B1_01, direction: OUTPUT}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
/* FUNCTION ************************************************************************************************************
*
* Function Name : BOARD_InitPins
* Description : Configures pin routing and optionally pin electrical features.
*
* END ****************************************************************************************************************/
void BOARD_InitPins(void) {
CLOCK_EnableClock(kCLOCK_Iomuxc);
/* GPIO configuration of USER_BUTTON on GPIO_EMC_09 (pin 1) */
gpio_pin_config_t USER_BUTTON_config = {
.direction = kGPIO_DigitalInput,
.outputLogic = 0U,
.interruptMode = kGPIO_NoIntmode
};
/* Initialize GPIO functionality on GPIO_EMC_09 (pin 1) */
GPIO_PinInit(GPIO2, 9U, &USER_BUTTON_config);
/* GPIO configuration of USER_LED on GPIO_SD_B1_01 (pin 21) */
gpio_pin_config_t USER_LED_config = {
.direction = kGPIO_DigitalOutput,
.outputLogic = 0U,
.interruptMode = kGPIO_NoIntmode
};
/* Initialize GPIO functionality on GPIO_SD_B1_01 (pin 21) */
GPIO_PinInit(GPIO3, 21U, &USER_LED_config);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_09_GPIO2_IO09, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_01_GPIO3_IO21, 0U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_09_GPIO2_IO09, 0x70B0U);
}
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
BOARD_InitQSPIPins:
- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'}
- pin_list:
- {pin_num: '12', peripheral: FLEXSPI, signal: FLEXSPI_A_SCLK, pin_signal: GPIO_SD_B1_07}
- {pin_num: '11', peripheral: FLEXSPI, signal: FLEXSPI_A_DATA0, pin_signal: GPIO_SD_B1_08}
- {pin_num: '9', peripheral: FLEXSPI, signal: FLEXSPI_A_DATA1, pin_signal: GPIO_SD_B1_10}
- {pin_num: '10', peripheral: FLEXSPI, signal: FLEXSPI_A_DATA2, pin_signal: GPIO_SD_B1_09}
- {pin_num: '13', peripheral: FLEXSPI, signal: FLEXSPI_A_DATA3, pin_signal: GPIO_SD_B1_06}
- {pin_num: '8', peripheral: FLEXSPI, signal: FLEXSPI_A_SS0_B, pin_signal: GPIO_SD_B1_11}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
/* FUNCTION ************************************************************************************************************
*
* Function Name : BOARD_InitQSPIPins
* Description : Configures pin routing and optionally pin electrical features.
*
* END ****************************************************************************************************************/
void BOARD_InitQSPIPins(void) {
CLOCK_EnableClock(kCLOCK_Iomuxc);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_06_FLEXSPI_A_DATA03, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_07_FLEXSPI_A_SCLK, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_08_FLEXSPI_A_DATA00, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_09_FLEXSPI_A_DATA02, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_10_FLEXSPI_A_DATA01, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_11_FLEXSPI_A_SS0_B, 0U);
}
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
BOARD_InitDEBUG_UARTPins:
- options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'}
- pin_list:
- {pin_num: '68', peripheral: LPUART1, signal: RX, pin_signal: GPIO_AD_B0_07, slew_rate: Slow}
- {pin_num: '72', peripheral: LPUART1, signal: TX, pin_signal: GPIO_AD_B0_06, slew_rate: Slow}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
/* FUNCTION ************************************************************************************************************
*
* Function Name : BOARD_InitDEBUG_UARTPins
* Description : Configures pin routing and optionally pin electrical features.
*
* END ****************************************************************************************************************/
void BOARD_InitDEBUG_UARTPins(void) {
CLOCK_EnableClock(kCLOCK_Iomuxc);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_06_LPUART1_TX, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_07_LPUART1_RX, 0U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_06_LPUART1_TX, 0x10B0U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_07_LPUART1_RX, 0x10B0U);
}
/***********************************************************************************************************************
* EOF
**********************************************************************************************************************/

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/***********************************************************************************************************************
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
**********************************************************************************************************************/
#ifndef _PIN_MUX_H_
#define _PIN_MUX_H_
/***********************************************************************************************************************
* Definitions
**********************************************************************************************************************/
/*! @brief Direction type */
typedef enum _pin_mux_direction
{
kPIN_MUX_DirectionInput = 0U, /* Input direction */
kPIN_MUX_DirectionOutput = 1U, /* Output direction */
kPIN_MUX_DirectionInputOrOutput = 2U /* Input or output direction */
} pin_mux_direction_t;
/*!
* @addtogroup pin_mux
* @{
*/
/***********************************************************************************************************************
* API
**********************************************************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif
/*!
* @brief Calls initialization functions.
*
*/
void BOARD_InitBootPins(void);
/* GPIO_EMC_09 (number 1), USER_BUTTON/SW4 */
/* Routed pin properties */
#define BOARD_INITPINS_USER_BUTTON_PERIPHERAL GPIO2 /*!< Peripheral name */
#define BOARD_INITPINS_USER_BUTTON_SIGNAL gpio_io /*!< Signal name */
#define BOARD_INITPINS_USER_BUTTON_CHANNEL 9U /*!< Signal channel */
/* Symbols to be used with GPIO driver */
#define BOARD_INITPINS_USER_BUTTON_GPIO GPIO2 /*!< GPIO peripheral base pointer */
#define BOARD_INITPINS_USER_BUTTON_GPIO_PIN 9U /*!< GPIO pin number */
#define BOARD_INITPINS_USER_BUTTON_GPIO_PIN_MASK (1U << 9U) /*!< GPIO pin mask */
#define BOARD_INITPINS_USER_BUTTON_PORT GPIO2 /*!< PORT peripheral base pointer */
#define BOARD_INITPINS_USER_BUTTON_PIN 9U /*!< PORT pin number */
#define BOARD_INITPINS_USER_BUTTON_PIN_MASK (1U << 9U) /*!< PORT pin mask */
/* GPIO_SD_B1_01 (number 21), GPIO SD_B1_01 */
/* Routed pin properties */
#define BOARD_INITPINS_USER_LED_PERIPHERAL GPIO3 /*!< Peripheral name */
#define BOARD_INITPINS_USER_LED_SIGNAL gpio_io /*!< Signal name */
#define BOARD_INITPINS_USER_LED_CHANNEL 21U /*!< Signal channel */
/* Symbols to be used with GPIO driver */
#define BOARD_INITPINS_USER_LED_GPIO GPIO3 /*!< GPIO peripheral base pointer */
#define BOARD_INITPINS_USER_LED_INIT_GPIO_VALUE 0U /*!< GPIO output initial state */
#define BOARD_INITPINS_USER_LED_GPIO_PIN 21U /*!< GPIO pin number */
#define BOARD_INITPINS_USER_LED_GPIO_PIN_MASK (1U << 21U) /*!< GPIO pin mask */
#define BOARD_INITPINS_USER_LED_PORT GPIO3 /*!< PORT peripheral base pointer */
#define BOARD_INITPINS_USER_LED_PIN 21U /*!< PORT pin number */
#define BOARD_INITPINS_USER_LED_PIN_MASK (1U << 21U) /*!< PORT pin mask */
/*!
* @brief Configures pin routing and optionally pin electrical features.
*
*/
void BOARD_InitPins(void);
/* GPIO_SD_B1_07 (number 12), FlexSPI_CLK_A/U13[6] */
/* Routed pin properties */
#define BOARD_INITQSPIPINS_FlexSPI_CLK_PERIPHERAL FLEXSPI /*!< Peripheral name */
#define BOARD_INITQSPIPINS_FlexSPI_CLK_SIGNAL FLEXSPI_A_SCLK /*!< Signal name */
/* GPIO_SD_B1_08 (number 11), FlexSPI_D0_A/U13[5] */
/* Routed pin properties */
#define BOARD_INITQSPIPINS_FlexSPI_D0_A_PERIPHERAL FLEXSPI /*!< Peripheral name */
#define BOARD_INITQSPIPINS_FlexSPI_D0_A_SIGNAL FLEXSPI_A_DATA0 /*!< Signal name */
/* GPIO_SD_B1_10 (number 9), FlexSPI_D1_A/U13[2] */
/* Routed pin properties */
#define BOARD_INITQSPIPINS_FlexSPI_D1_A_PERIPHERAL FLEXSPI /*!< Peripheral name */
#define BOARD_INITQSPIPINS_FlexSPI_D1_A_SIGNAL FLEXSPI_A_DATA1 /*!< Signal name */
/* GPIO_SD_B1_09 (number 10), FlexSPI_D2_A/U13[3] */
/* Routed pin properties */
#define BOARD_INITQSPIPINS_FlexSPI_D2_A_PERIPHERAL FLEXSPI /*!< Peripheral name */
#define BOARD_INITQSPIPINS_FlexSPI_D2_A_SIGNAL FLEXSPI_A_DATA2 /*!< Signal name */
/* GPIO_SD_B1_06 (number 13), FlexSPI_D3_A/U13[7] */
/* Routed pin properties */
#define BOARD_INITQSPIPINS_FlexSPI_D3_A_PERIPHERAL FLEXSPI /*!< Peripheral name */
#define BOARD_INITQSPIPINS_FlexSPI_D3_A_SIGNAL FLEXSPI_A_DATA3 /*!< Signal name */
/* GPIO_SD_B1_11 (number 8), FlexSPI_SS0/U13[1] */
/* Routed pin properties */
#define BOARD_INITQSPIPINS_FlexSPI_SS0_PERIPHERAL FLEXSPI /*!< Peripheral name */
#define BOARD_INITQSPIPINS_FlexSPI_SS0_SIGNAL FLEXSPI_A_SS0_B /*!< Signal name */
/*!
* @brief Configures pin routing and optionally pin electrical features.
*
*/
void BOARD_InitQSPIPins(void);
/* GPIO_AD_B0_07 (number 68), LPUART1_RXD */
/* Routed pin properties */
#define BOARD_INITDEBUG_UARTPINS_UART1_RXD_PERIPHERAL LPUART1 /*!< Peripheral name */
#define BOARD_INITDEBUG_UARTPINS_UART1_RXD_SIGNAL RX /*!< Signal name */
/* GPIO_AD_B0_06 (number 72), LPUART1_TXD */
/* Routed pin properties */
#define BOARD_INITDEBUG_UARTPINS_UART1_TXD_PERIPHERAL LPUART1 /*!< Peripheral name */
#define BOARD_INITDEBUG_UARTPINS_UART1_TXD_SIGNAL TX /*!< Signal name */
/*!
* @brief Configures pin routing and optionally pin electrical features.
*
*/
void BOARD_InitDEBUG_UARTPins(void);
#if defined(__cplusplus)
}
#endif
/*!
* @}
*/
#endif /* _PIN_MUX_H_ */
/***********************************************************************************************************************
* EOF
**********************************************************************************************************************/

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managed_components/espressif__tinyusb/hw/bsp/imxrt/boards/mimxrt1015_evk/evkmimxrt1015_flexspi_nor_config.c Normal file
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/*
* Copyright 2018-2019 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "evkmimxrt1015_flexspi_nor_config.h"
/* Component ID definition, used by tools. */
#ifndef FSL_COMPONENT_ID
#define FSL_COMPONENT_ID "platform.drivers.xip_board"
#endif
/*******************************************************************************
* Code
******************************************************************************/
#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
__attribute__((section(".boot_hdr.conf")))
#elif defined(__ICCARM__)
#pragma location = ".boot_hdr.conf"
#endif
const flexspi_nor_config_t qspiflash_config = {
.memConfig =
{
.tag = FLEXSPI_CFG_BLK_TAG,
.version = FLEXSPI_CFG_BLK_VERSION,
.readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad,
.csHoldTime = 3u,
.csSetupTime = 3u,
.sflashPadType = kSerialFlash_4Pads,
.serialClkFreq = kFlexSpiSerialClk_100MHz,
.sflashA1Size = 16u * 1024u * 1024u,
.lookupTable =
{
// Read LUTs
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18),
FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04),
},
},
.pageSize = 256u,
.sectorSize = 4u * 1024u,
.blockSize = 256u * 1024u,
.isUniformBlockSize = false,
};
#endif /* XIP_BOOT_HEADER_ENABLE */

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/*
* Copyright 2018-2019 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __EVKMIMXRT1015_FLEXSPI_NOR_CONFIG__
#define __EVKMIMXRT1015_FLEXSPI_NOR_CONFIG__
#include <stdint.h>
#include <stdbool.h>
#include "fsl_common.h"
/*! @name Driver version */
/*@{*/
/*! @brief XIP_BOARD driver version 2.0.0. */
#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
/*@}*/
/* FLEXSPI memory config block related definitions */
#define FLEXSPI_CFG_BLK_TAG (0x42464346UL) // ascii "FCFB" Big Endian
#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0
#define FLEXSPI_CFG_BLK_SIZE (512)
/* FLEXSPI Feature related definitions */
#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1
/* Lookup table related definitions */
#define CMD_INDEX_READ 0
#define CMD_INDEX_READSTATUS 1
#define CMD_INDEX_WRITEENABLE 2
#define CMD_INDEX_WRITE 4
#define CMD_LUT_SEQ_IDX_READ 0
#define CMD_LUT_SEQ_IDX_READSTATUS 1
#define CMD_LUT_SEQ_IDX_WRITEENABLE 3
#define CMD_LUT_SEQ_IDX_WRITE 9
#define CMD_SDR 0x01
#define CMD_DDR 0x21
#define RADDR_SDR 0x02
#define RADDR_DDR 0x22
#define CADDR_SDR 0x03
#define CADDR_DDR 0x23
#define MODE1_SDR 0x04
#define MODE1_DDR 0x24
#define MODE2_SDR 0x05
#define MODE2_DDR 0x25
#define MODE4_SDR 0x06
#define MODE4_DDR 0x26
#define MODE8_SDR 0x07
#define MODE8_DDR 0x27
#define WRITE_SDR 0x08
#define WRITE_DDR 0x28
#define READ_SDR 0x09
#define READ_DDR 0x29
#define LEARN_SDR 0x0A
#define LEARN_DDR 0x2A
#define DATSZ_SDR 0x0B
#define DATSZ_DDR 0x2B
#define DUMMY_SDR 0x0C
#define DUMMY_DDR 0x2C
#define DUMMY_RWDS_SDR 0x0D
#define DUMMY_RWDS_DDR 0x2D
#define JMP_ON_CS 0x1F
#define STOP 0
#define FLEXSPI_1PAD 0
#define FLEXSPI_2PAD 1
#define FLEXSPI_4PAD 2
#define FLEXSPI_8PAD 3
#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \
(FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \
FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))
//!@brief Definitions for FlexSPI Serial Clock Frequency
typedef enum _FlexSpiSerialClockFreq
{
kFlexSpiSerialClk_30MHz = 1,
kFlexSpiSerialClk_50MHz = 2,
kFlexSpiSerialClk_60MHz = 3,
kFlexSpiSerialClk_75MHz = 4,
kFlexSpiSerialClk_80MHz = 5,
kFlexSpiSerialClk_100MHz = 6,
kFlexSpiSerialClk_133MHz = 7,
kFlexSpiSerialClk_166MHz = 8,
kFlexSpiSerialClk_200MHz = 9,
} flexspi_serial_clk_freq_t;
//!@brief FlexSPI clock configuration type
enum
{
kFlexSpiClk_SDR, //!< Clock configure for SDR mode
kFlexSpiClk_DDR, //!< Clock configurat for DDR mode
};
//!@brief FlexSPI Read Sample Clock Source definition
typedef enum _FlashReadSampleClkSource
{
kFlexSPIReadSampleClk_LoopbackInternally = 0,
kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1,
kFlexSPIReadSampleClk_LoopbackFromSckPad = 2,
kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3,
} flexspi_read_sample_clk_t;
//!@brief Misc feature bit definitions
enum
{
kFlexSpiMiscOffset_DiffClkEnable = 0, //!< Bit for Differential clock enable
kFlexSpiMiscOffset_Ck2Enable = 1, //!< Bit for CK2 enable
kFlexSpiMiscOffset_ParallelEnable = 2, //!< Bit for Parallel mode enable
kFlexSpiMiscOffset_WordAddressableEnable = 3, //!< Bit for Word Addressable enable
kFlexSpiMiscOffset_SafeConfigFreqEnable = 4, //!< Bit for Safe Configuration Frequency enable
kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, //!< Bit for Pad setting override enable
kFlexSpiMiscOffset_DdrModeEnable = 6, //!< Bit for DDR clock confiuration indication.
};
//!@brief Flash Type Definition
enum
{
kFlexSpiDeviceType_SerialNOR = 1, //!< Flash devices are Serial NOR
kFlexSpiDeviceType_SerialNAND = 2, //!< Flash devices are Serial NAND
kFlexSpiDeviceType_SerialRAM = 3, //!< Flash devices are Serial RAM/HyperFLASH
kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND
kFlexSpiDeviceType_MCP_NOR_RAM = 0x13, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial RAMs
};
//!@brief Flash Pad Definitions
enum
{
kSerialFlash_1Pad = 1,
kSerialFlash_2Pads = 2,
kSerialFlash_4Pads = 4,
kSerialFlash_8Pads = 8,
};
//!@brief FlexSPI LUT Sequence structure
typedef struct _lut_sequence
{
uint8_t seqNum; //!< Sequence Number, valid number: 1-16
uint8_t seqId; //!< Sequence Index, valid number: 0-15
uint16_t reserved;
} flexspi_lut_seq_t;
//!@brief Flash Configuration Command Type
enum
{
kDeviceConfigCmdType_Generic, //!< Generic command, for example: configure dummy cycles, drive strength, etc
kDeviceConfigCmdType_QuadEnable, //!< Quad Enable command
kDeviceConfigCmdType_Spi2Xpi, //!< Switch from SPI to DPI/QPI/OPI mode
kDeviceConfigCmdType_Xpi2Spi, //!< Switch from DPI/QPI/OPI to SPI mode
kDeviceConfigCmdType_Spi2NoCmd, //!< Switch to 0-4-4/0-8-8 mode
kDeviceConfigCmdType_Reset, //!< Reset device command
};
//!@brief FlexSPI Memory Configuration Block
typedef struct _FlexSPIConfig
{
uint32_t tag; //!< [0x000-0x003] Tag, fixed value 0x42464346UL
uint32_t version; //!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix
uint32_t reserved0; //!< [0x008-0x00b] Reserved for future use
uint8_t readSampleClkSrc; //!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3
uint8_t csHoldTime; //!< [0x00d-0x00d] CS hold time, default value: 3
uint8_t csSetupTime; //!< [0x00e-0x00e] CS setup time, default value: 3
uint8_t columnAddressWidth; //!< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For
//! Serial NAND, need to refer to datasheet
uint8_t deviceModeCfgEnable; //!< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable
uint8_t deviceModeType; //!< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch,
//! Generic configuration, etc.
uint16_t waitTimeCfgCommands; //!< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for
//! DPI/QPI/OPI switch or reset command
flexspi_lut_seq_t deviceModeSeq; //!< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt
//! sequence number, [31:16] Reserved
uint32_t deviceModeArg; //!< [0x018-0x01b] Argument/Parameter for device configuration
uint8_t configCmdEnable; //!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable
uint8_t configModeType[3]; //!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe
flexspi_lut_seq_t
configCmdSeqs[3]; //!< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq
uint32_t reserved1; //!< [0x02c-0x02f] Reserved for future use
uint32_t configCmdArgs[3]; //!< [0x030-0x03b] Arguments/Parameters for device Configuration commands
uint32_t reserved2; //!< [0x03c-0x03f] Reserved for future use
uint32_t controllerMiscOption; //!< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more
//! details
uint8_t deviceType; //!< [0x044-0x044] Device Type: See Flash Type Definition for more details
uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal
uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequency, device specific definitions, See System Boot
//! Chapter for more details
uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot
//! be done using 1 LUT sequence, currently, only applicable to HyperFLASH
uint32_t reserved3[2]; //!< [0x048-0x04f] Reserved for future use
uint32_t sflashA1Size; //!< [0x050-0x053] Size of Flash connected to A1
uint32_t sflashA2Size; //!< [0x054-0x057] Size of Flash connected to A2
uint32_t sflashB1Size; //!< [0x058-0x05b] Size of Flash connected to B1
uint32_t sflashB2Size; //!< [0x05c-0x05f] Size of Flash connected to B2
uint32_t csPadSettingOverride; //!< [0x060-0x063] CS pad setting override value
uint32_t sclkPadSettingOverride; //!< [0x064-0x067] SCK pad setting override value
uint32_t dataPadSettingOverride; //!< [0x068-0x06b] data pad setting override value
uint32_t dqsPadSettingOverride; //!< [0x06c-0x06f] DQS pad setting override value
uint32_t timeoutInMs; //!< [0x070-0x073] Timeout threshold for read status command
uint32_t commandInterval; //!< [0x074-0x077] CS deselect interval between two commands
uint16_t dataValidTime[2]; //!< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns
uint16_t busyOffset; //!< [0x07c-0x07d] Busy offset, valid value: 0-31
uint16_t busyBitPolarity; //!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 -
//! busy flag is 0 when flash device is busy
uint32_t lookupTable[64]; //!< [0x080-0x17f] Lookup table holds Flash command sequences
flexspi_lut_seq_t lutCustomSeq[12]; //!< [0x180-0x1af] Customizable LUT Sequences
uint32_t reserved4[4]; //!< [0x1b0-0x1bf] Reserved for future use
} flexspi_mem_config_t;
/* */
#define NOR_CMD_INDEX_READ CMD_INDEX_READ //!< 0
#define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS //!< 1
#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE //!< 2
#define NOR_CMD_INDEX_ERASESECTOR 3 //!< 3
#define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE //!< 4
#define NOR_CMD_INDEX_CHIPERASE 5 //!< 5
#define NOR_CMD_INDEX_DUMMY 6 //!< 6
#define NOR_CMD_INDEX_ERASEBLOCK 7 //!< 7
#define NOR_CMD_LUT_SEQ_IDX_READ CMD_LUT_SEQ_IDX_READ //!< 0 READ LUT sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_READSTATUS \
CMD_LUT_SEQ_IDX_READSTATUS //!< 1 Read Status LUT sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \
2 //!< 2 Read status DPI/QPI/OPI sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE \
CMD_LUT_SEQ_IDX_WRITEENABLE //!< 3 Write Enable sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \
4 //!< 4 Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5 //!< 5 Erase Sector sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8 //!< 8 Erase Block sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM \
CMD_LUT_SEQ_IDX_WRITE //!< 9 Program sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11 //!< 11 Chip Erase sequence in lookupTable id stored in config block
#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13 //!< 13 Read SFDP sequence in lookupTable id stored in config block
#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \
14 //!< 14 Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \
15 //!< 15 Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config blobk
/*
* Serial NOR configuration block
*/
typedef struct _flexspi_nor_config
{
flexspi_mem_config_t memConfig; //!< Common memory configuration info via FlexSPI
uint32_t pageSize; //!< Page size of Serial NOR
uint32_t sectorSize; //!< Sector size of Serial NOR
uint8_t ipcmdSerialClkFreq; //!< Clock frequency for IP command
uint8_t isUniformBlockSize; //!< Sector/Block size is the same
uint8_t reserved0[2]; //!< Reserved for future use
uint8_t serialNorType; //!< Serial NOR Flash type: 0/1/2/3
uint8_t needExitNoCmdMode; //!< Need to exit NoCmd mode before other IP command
uint8_t halfClkForNonReadCmd; //!< Half the Serial Clock for non-read command: true/false
uint8_t needRestoreNoCmdMode; //!< Need to Restore NoCmd mode after IP command execution
uint32_t blockSize; //!< Block size
uint32_t reserve2[11]; //!< Reserved for future use
} flexspi_nor_config_t;
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __cplusplus
}
#endif
#endif /* __EVKMIMXRT1015_FLEXSPI_NOR_CONFIG__ */

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<?xml version="1.0" encoding= "UTF-8" ?>
<configuration name="MIMXRT1015-EVK" xsi:schemaLocation="http://mcuxpresso.nxp.com/XSD/mex_configuration_17 http://mcuxpresso.nxp.com/XSD/mex_configuration_17.xsd" uuid="4be4468a-3124-4ac9-9d4f-05d5f8ad6399" version="17" xmlns="http://mcuxpresso.nxp.com/XSD/mex_configuration_17" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<common>
<processor>MIMXRT1015xxxxx</processor>
<package>MIMXRT1015DAF5A</package>
<board>MIMXRT1015-EVK</board>
<board_revision>B</board_revision>
<mcu_data>ksdk2_0</mcu_data>
<cores selected="core0">
<core name="Cortex-M7F" id="core0" description="M7 core"/>
</cores>
<description></description>
</common>
<preferences>
<validate_boot_init_only>true</validate_boot_init_only>
<generate_code_modified_registers_only>false</generate_code_modified_registers_only>
<update_include_paths>true</update_include_paths>
<generate_registers_defines>false</generate_registers_defines>
</preferences>
<tools>
<pins name="Pins" version="17.0" enabled="true" update_project_code="true">
<generated_project_files>
<file path="board/pin_mux.c" update_enabled="true"/>
<file path="board/pin_mux.h" update_enabled="true"/>
</generated_project_files>
<pins_profile>
<processor_version>24.12.10</processor_version>
<pin_labels>
<pin_label pin_num="21" pin_signal="GPIO_SD_B1_01" label="GPIO SD_B1_01" identifier="USER_LED"/>
</pin_labels>
<external_user_signals>
<properties/>
</external_user_signals>
<power_domains>
<power_domain name="NVCC_GPIO" value="3.3"/>
</power_domains>
</pins_profile>
<functions_list>
<function name="BOARD_InitPins">
<description>Configures pin routing and optionally pin electrical features.</description>
<options>
<callFromInitBoot>true</callFromInitBoot>
<coreID>core0</coreID>
<enableClock>true</enableClock>
</options>
<dependencies>
<dependency resourceType="Peripheral" resourceId="GPIO2" description="Peripheral GPIO2 signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitPins">
<feature name="initialized" evaluation="equal">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitPins">
<feature name="enabled" evaluation="equal" configuration="core0">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitPins">
<feature name="enabled" evaluation="equal" configuration="core0">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.igpio" description="Pins initialization requires the IGPIO Driver in the project." problem_level="2" source="Pins:BOARD_InitPins">
<feature name="enabled" evaluation="equal" configuration="core0">
<data>true</data>
</feature>
</dependency>
</dependencies>
<pins>
<pin peripheral="GPIO2" signal="gpio_io, 09" pin_num="1" pin_signal="GPIO_EMC_09">
<pin_features>
<pin_feature name="direction" value="INPUT"/>
<pin_feature name="pull_keeper_select" value="Pull"/>
<pin_feature name="pull_up_down_config" value="Pull_Up_47K_Ohm"/>
</pin_features>
</pin>
<pin peripheral="GPIO3" signal="gpio_io, 21" pin_num="21" pin_signal="GPIO_SD_B1_01">
<pin_features>
<pin_feature name="direction" value="OUTPUT"/>
</pin_features>
</pin>
</pins>
</function>
<function name="BOARD_InitQSPIPins">
<description>Configures pin routing and optionally pin electrical features.</description>
<options>
<callFromInitBoot>false</callFromInitBoot>
<coreID>core0</coreID>
<enableClock>true</enableClock>
</options>
<dependencies>
<dependency resourceType="Peripheral" resourceId="FLEXSPI" description="Peripheral FLEXSPI signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitQSPIPins">
<feature name="initialized" evaluation="equal">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitQSPIPins">
<feature name="enabled" evaluation="equal" configuration="core0">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitQSPIPins">
<feature name="enabled" evaluation="equal" configuration="core0">
<data>true</data>
</feature>
</dependency>
</dependencies>
<pins>
<pin peripheral="FLEXSPI" signal="FLEXSPI_A_SCLK" pin_num="12" pin_signal="GPIO_SD_B1_07"/>
<pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA0" pin_num="11" pin_signal="GPIO_SD_B1_08"/>
<pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA1" pin_num="9" pin_signal="GPIO_SD_B1_10"/>
<pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA2" pin_num="10" pin_signal="GPIO_SD_B1_09"/>
<pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA3" pin_num="13" pin_signal="GPIO_SD_B1_06"/>
<pin peripheral="FLEXSPI" signal="FLEXSPI_A_SS0_B" pin_num="8" pin_signal="GPIO_SD_B1_11"/>
</pins>
</function>
<function name="BOARD_InitDEBUG_UARTPins">
<description>Configures pin routing and optionally pin electrical features.</description>
<options>
<callFromInitBoot>true</callFromInitBoot>
<coreID>core0</coreID>
<enableClock>true</enableClock>
</options>
<dependencies>
<dependency resourceType="Peripheral" resourceId="LPUART1" description="Peripheral LPUART1 signals are routed in the Pins Tool, but the peripheral is not initialized in the Peripherals Tool." problem_level="1" source="Pins:BOARD_InitDEBUG_UARTPins">
<feature name="initialized" evaluation="equal">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitDEBUG_UARTPins">
<feature name="enabled" evaluation="equal" configuration="core0">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitDEBUG_UARTPins">
<feature name="enabled" evaluation="equal" configuration="core0">
<data>true</data>
</feature>
</dependency>
</dependencies>
<pins>
<pin peripheral="LPUART1" signal="RX" pin_num="68" pin_signal="GPIO_AD_B0_07">
<pin_features>
<pin_feature name="slew_rate" value="Slow"/>
</pin_features>
</pin>
<pin peripheral="LPUART1" signal="TX" pin_num="72" pin_signal="GPIO_AD_B0_06">
<pin_features>
<pin_feature name="slew_rate" value="Slow"/>
</pin_features>
</pin>
</pins>
</function>
</functions_list>
</pins>
<clocks name="Clocks" version="15.0" enabled="true" update_project_code="true">
<generated_project_files>
<file path="board/clock_config.c" update_enabled="true"/>
<file path="board/clock_config.h" update_enabled="true"/>
</generated_project_files>
<clocks_profile>
<processor_version>24.12.10</processor_version>
</clocks_profile>
<clock_configurations>
<clock_configuration name="BOARD_BootClockRUN" id_prefix="" prefix_user_defined="false">
<description></description>
<options/>
<dependencies>
<dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtali" description="&apos;RTC_XTALI&apos; (Pins tool id: XTALOSC24M.rtc_xtali, Clocks tool id: XTALOSC24M.RTC_XTALI) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
<feature name="routed" evaluation="">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtali" description="&apos;RTC_XTALI&apos; (Pins tool id: XTALOSC24M.rtc_xtali, Clocks tool id: XTALOSC24M.RTC_XTALI) needs to have &apos;INPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
<feature name="direction" evaluation="">
<data>INPUT</data>
</feature>
</dependency>
<dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtalo" description="&apos;RTC_XTALO&apos; (Pins tool id: XTALOSC24M.rtc_xtalo, Clocks tool id: XTALOSC24M.RTC_XTALO) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
<feature name="routed" evaluation="">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtalo" description="&apos;RTC_XTALO&apos; (Pins tool id: XTALOSC24M.rtc_xtalo, Clocks tool id: XTALOSC24M.RTC_XTALO) needs to have &apos;OUTPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
<feature name="direction" evaluation="">
<data>OUTPUT</data>
</feature>
</dependency>
<dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtali" description="&apos;XTALI&apos; (Pins tool id: XTALOSC24M.xtali, Clocks tool id: XTALOSC24M.XTALI) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
<feature name="routed" evaluation="">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtali" description="&apos;XTALI&apos; (Pins tool id: XTALOSC24M.xtali, Clocks tool id: XTALOSC24M.XTALI) needs to have &apos;INPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
<feature name="direction" evaluation="">
<data>INPUT</data>
</feature>
</dependency>
<dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtalo" description="&apos;XTALO&apos; (Pins tool id: XTALOSC24M.xtalo, Clocks tool id: XTALOSC24M.XTALO) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
<feature name="routed" evaluation="">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtalo" description="&apos;XTALO&apos; (Pins tool id: XTALOSC24M.xtalo, Clocks tool id: XTALOSC24M.XTALO) needs to have &apos;OUTPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
<feature name="direction" evaluation="">
<data>OUTPUT</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN">
<feature name="enabled" evaluation="equal" configuration="core0">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Clocks initialization requires the IOMUXC Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN">
<feature name="enabled" evaluation="equal" configuration="core0">
<data>true</data>
</feature>
</dependency>
</dependencies>
<clock_sources>
<clock_source id="XTALOSC24M.RTC_OSC.outFreq" value="32.768 kHz" locked="false" enabled="true"/>
</clock_sources>
<clock_outputs>
<clock_output id="AHB_CLK_ROOT.outFreq" value="500 MHz" locked="false" accuracy=""/>
<clock_output id="CKIL_SYNC_CLK_ROOT.outFreq" value="32.768 kHz" locked="false" accuracy=""/>
<clock_output id="CLK_1M.outFreq" value="1 MHz" locked="false" accuracy=""/>
<clock_output id="CLK_24M.outFreq" value="24 MHz" locked="false" accuracy=""/>
<clock_output id="ENET_500M_REF_CLK.outFreq" value="500 MHz" locked="false" accuracy=""/>
<clock_output id="FLEXIO1_CLK_ROOT.outFreq" value="30 MHz" locked="false" accuracy=""/>
<clock_output id="FLEXSPI_CLK_ROOT.outFreq" value="2160/11 MHz" locked="false" accuracy=""/>
<clock_output id="GPT1_ipg_clk_highfreq.outFreq" value="62.5 MHz" locked="false" accuracy=""/>
<clock_output id="GPT2_ipg_clk_highfreq.outFreq" value="62.5 MHz" locked="false" accuracy=""/>
<clock_output id="IPG_CLK_ROOT.outFreq" value="125 MHz" locked="false" accuracy=""/>
<clock_output id="LPI2C_CLK_ROOT.outFreq" value="60 MHz" locked="false" accuracy=""/>
<clock_output id="LPSPI_CLK_ROOT.outFreq" value="105.6 MHz" locked="false" accuracy=""/>
<clock_output id="MQS_MCLK.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
<clock_output id="PERCLK_CLK_ROOT.outFreq" value="62.5 MHz" locked="false" accuracy=""/>
<clock_output id="SAI1_CLK_ROOT.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
<clock_output id="SAI1_MCLK1.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
<clock_output id="SAI1_MCLK2.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
<clock_output id="SAI1_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/>
<clock_output id="SAI2_CLK_ROOT.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
<clock_output id="SAI2_MCLK1.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
<clock_output id="SAI2_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/>
<clock_output id="SAI3_CLK_ROOT.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
<clock_output id="SAI3_MCLK1.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
<clock_output id="SAI3_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/>
<clock_output id="SPDIF0_CLK_ROOT.outFreq" value="30 MHz" locked="false" accuracy=""/>
<clock_output id="TRACE_CLK_ROOT.outFreq" value="352/3 MHz" locked="false" accuracy=""/>
<clock_output id="UART_CLK_ROOT.outFreq" value="80 MHz" locked="false" accuracy=""/>
<clock_output id="USBPHY1_CLK.outFreq" value="480 MHz" locked="false" accuracy=""/>
</clock_outputs>
<clock_settings>
<setting id="CCM.AHB_PODF.scale" value="1" locked="true"/>
<setting id="CCM.ARM_PODF.scale" value="1" locked="true"/>
<setting id="CCM.CLKO2_SEL.sel" value="CCM.LPI2C_CLK_ROOT" locked="false"/>
<setting id="CCM.FLEXSPI_PODF.scale" value="2" locked="true"/>
<setting id="CCM.FLEXSPI_SEL.sel" value="CCM_ANALOG.PLL3_PFD0_CLK" locked="false"/>
<setting id="CCM.IPG_PODF.scale" value="4" locked="false"/>
<setting id="CCM.LPSPI_PODF.scale" value="5" locked="true"/>
<setting id="CCM.PERCLK_PODF.scale" value="2" locked="true"/>
<setting id="CCM.PRE_PERIPH_CLK_SEL.sel" value="CCM.ARM_PODF" locked="false"/>
<setting id="CCM.SEMC_PODF.scale" value="2" locked="false"/>
<setting id="CCM.TRACE_PODF.scale" value="3" locked="true"/>
<setting id="CCM_ANALOG.PLL2.denom" value="1" locked="true"/>
<setting id="CCM_ANALOG.PLL2.num" value="0" locked="true"/>
<setting id="CCM_ANALOG.PLL2_BYPASS.sel" value="CCM_ANALOG.PLL2_OUT_CLK" locked="false"/>
<setting id="CCM_ANALOG.PLL2_PFD0_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD0" locked="false"/>
<setting id="CCM_ANALOG.PLL2_PFD1_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD1" locked="false"/>
<setting id="CCM_ANALOG.PLL2_PFD2_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD2" locked="false"/>
<setting id="CCM_ANALOG.PLL2_PFD2_DIV.scale" value="18" locked="true"/>
<setting id="CCM_ANALOG.PLL2_PFD2_MUL.scale" value="18" locked="true"/>
<setting id="CCM_ANALOG.PLL2_PFD3_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD3" locked="false"/>
<setting id="CCM_ANALOG.PLL2_PFD3_DIV.scale" value="18" locked="true"/>
<setting id="CCM_ANALOG.PLL2_PFD3_MUL.scale" value="18" locked="true"/>
<setting id="CCM_ANALOG.PLL3_BYPASS.sel" value="CCM_ANALOG.PLL3" locked="false"/>
<setting id="CCM_ANALOG.PLL3_PFD0_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD0" locked="false"/>
<setting id="CCM_ANALOG.PLL3_PFD0_DIV.scale" value="22" locked="true"/>
<setting id="CCM_ANALOG.PLL3_PFD0_MUL.scale" value="18" locked="true"/>
<setting id="CCM_ANALOG.PLL3_PFD1_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD1" locked="false"/>
<setting id="CCM_ANALOG.PLL3_PFD2_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD2" locked="false"/>
<setting id="CCM_ANALOG.PLL3_PFD3_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD3" locked="false"/>
<setting id="CCM_ANALOG.PLL3_PFD3_DIV.scale" value="18" locked="true"/>
<setting id="CCM_ANALOG.PLL3_PFD3_MUL.scale" value="18" locked="true"/>
<setting id="CCM_ANALOG.PLL4.denom" value="50" locked="false"/>
<setting id="CCM_ANALOG.PLL4.div" value="47" locked="false"/>
<setting id="CCM_ANALOG.PLL6_BYPASS.sel" value="CCM_ANALOG.PLL6" locked="false"/>
<setting id="CCM_ANALOG_PLL_USB1_EN_USB_CLKS_CFG" value="Enabled" locked="false"/>
<setting id="CCM_ANALOG_PLL_USB1_EN_USB_CLKS_OUT_CFG" value="Enabled" locked="false"/>
<setting id="CCM_ANALOG_PLL_USB1_POWER_CFG" value="Yes" locked="false"/>
</clock_settings>
<called_from_default_init>true</called_from_default_init>
</clock_configuration>
</clock_configurations>
</clocks>
<dcdx name="DCDx" version="3.0" enabled="false" update_project_code="true">
<generated_project_files/>
<dcdx_profile>
<processor_version>N/A</processor_version>
</dcdx_profile>
<dcdx_configurations/>
</dcdx>
<periphs name="Peripherals" version="12.0" enabled="false" update_project_code="true">
<generated_project_files/>
<peripherals_profile>
<processor_version>13.0.2</processor_version>
</peripherals_profile>
<functional_groups>
<functional_group name="BOARD_InitPeripherals" uuid="57fc488c-a9f7-4a03-8ab3-5d2a3fd16a50" called_from_default_init="true" id_prefix="" core="core0">
<description></description>
<options/>
<dependencies/>
<instances>
<instance name="DEBUG_UART" uuid="600d7aee-5a2d-4373-9763-ce007b981c15" type="lpuart" type_id="lpuart_bebe3e12b6ec22bbd14199038f2bf459" mode="polling" peripheral="LPUART1" enabled="false" comment="" custom_name_enabled="true" editing_lock="false">
<config_set name="lpuartConfig_t" quick_selection="QuickSelection1">
<struct name="lpuartConfig">
<setting name="clockSource" value="LpuartClock"/>
<setting name="lpuartSrcClkFreq" value="ClocksTool_DefaultInit"/>
<setting name="baudRate_Bps" value="115200"/>
<setting name="parityMode" value="kLPUART_ParityDisabled"/>
<setting name="dataBitsCount" value="kLPUART_EightDataBits"/>
<setting name="isMsb" value="false"/>
<setting name="stopBitCount" value="kLPUART_OneStopBit"/>
<setting name="txFifoWatermark" value="0"/>
<setting name="rxFifoWatermark" value="1"/>
<setting name="enableRxRTS" value="false"/>
<setting name="enableTxCTS" value="false"/>
<setting name="txCtsSource" value="kLPUART_CtsSourcePin"/>
<setting name="txCtsConfig" value="kLPUART_CtsSampleAtStart"/>
<setting name="rxIdleType" value="kLPUART_IdleTypeStartBit"/>
<setting name="rxIdleConfig" value="kLPUART_IdleCharacter1"/>
<setting name="enableTx" value="true"/>
<setting name="enableRx" value="true"/>
</struct>
</config_set>
</instance>
<instance name="COMBO_SENSOR" uuid="96f9e552-25e5-434a-9454-5cf9e614733d" type="lpi2c" type_id="lpi2c_db68d4f4f06a22e25ab51fe9bd6db4d2" mode="master" peripheral="LPI2C1" enabled="false" comment="" custom_name_enabled="true" editing_lock="false">
<config_set name="main" quick_selection="qs_interrupt">
<setting name="clockSource" value="Lpi2cClock"/>
<setting name="clockSourceFreq" value="ClocksTool_DefaultInit"/>
<struct name="interrupt">
<setting name="IRQn" value="LPI2C1_IRQn"/>
<setting name="enable_interrrupt" value="enabled"/>
<setting name="enable_priority" value="false"/>
<setting name="priority" value="0"/>
<setting name="enable_custom_name" value="false"/>
</struct>
</config_set>
<config_set name="master" quick_selection="qs_master_transfer">
<setting name="mode" value="transfer"/>
<struct name="config">
<setting name="enableMaster" value="true"/>
<setting name="enableDoze" value="true"/>
<setting name="debugEnable" value="false"/>
<setting name="ignoreAck" value="false"/>
<setting name="pinConfig" value="kLPI2C_2PinOpenDrain"/>
<setting name="baudRate_Hz" value="100000"/>
<setting name="busIdleTimeout_ns" value="0"/>
<setting name="pinLowTimeout_ns" value="0"/>
<setting name="sdaGlitchFilterWidth_ns" value="0"/>
<setting name="sclGlitchFilterWidth_ns" value="0"/>
<struct name="hostRequest">
<setting name="enable" value="false"/>
<setting name="source" value="kLPI2C_HostRequestExternalPin"/>
<setting name="polarity" value="kLPI2C_HostRequestPinActiveHigh"/>
</struct>
<set name="edmaRequestSources">
<selected/>
</set>
</struct>
<struct name="transfer">
<setting name="blocking" value="false"/>
<setting name="enable_custom_handle" value="false"/>
<struct name="callback">
<setting name="name" value=""/>
<setting name="userData" value=""/>
</struct>
<set name="flags">
<selected/>
</set>
<setting name="slaveAddress" value="0"/>
<setting name="direction" value="kLPI2C_Write"/>
<setting name="subaddress" value="0"/>
<setting name="subaddressSize" value="1"/>
<setting name="blocking_buffer" value="false"/>
<setting name="enable_custom_buffer" value="false"/>
<setting name="dataSize" value="1"/>
</struct>
</config_set>
</instance>
<instance name="USER_LED" uuid="5592aac0-ced9-4284-88a8-bbeb5083a92f" type="igpio" type_id="igpio_b1c1fa279aa7069dca167502b8589cb7" mode="GPIO" peripheral="GPIO3" enabled="false" comment="" custom_name_enabled="true" editing_lock="false">
<config_set name="fsl_gpio">
<setting name="enable_irq_comb_0_15" value="false"/>
<struct name="gpio_interrupt_comb_0_15">
<setting name="IRQn" value="GPIO3_Combined_0_15_IRQn"/>
<setting name="enable_interrrupt" value="enabled"/>
<setting name="enable_priority" value="false"/>
<setting name="priority" value="0"/>
<setting name="enable_custom_name" value="false"/>
</struct>
<setting name="enable_irq_comb_16_31" value="false"/>
<struct name="gpio_interrupt_comb_16_31">
<setting name="IRQn" value="GPIO3_Combined_16_31_IRQn"/>
<setting name="enable_interrrupt" value="enabled"/>
<setting name="enable_priority" value="false"/>
<setting name="priority" value="0"/>
<setting name="enable_custom_name" value="false"/>
</struct>
</config_set>
</instance>
<instance name="USER_BUTTON" uuid="e7774953-3606-41b8-8b72-6e09025369e0" type="igpio" type_id="igpio_b1c1fa279aa7069dca167502b8589cb7" mode="GPIO" peripheral="GPIO2" enabled="false" comment="" custom_name_enabled="true" editing_lock="false">
<config_set name="fsl_gpio">
<setting name="enable_irq_comb_0_15" value="false"/>
<struct name="gpio_interrupt_comb_0_15">
<setting name="IRQn" value="GPIO2_Combined_0_15_IRQn"/>
<setting name="enable_interrrupt" value="enabled"/>
<setting name="enable_priority" value="false"/>
<setting name="priority" value="0"/>
<setting name="enable_custom_name" value="false"/>
</struct>
<setting name="enable_irq_comb_16_31" value="false"/>
<struct name="gpio_interrupt_comb_16_31">
<setting name="IRQn" value="GPIO2_Combined_16_31_IRQn"/>
<setting name="enable_interrrupt" value="enabled"/>
<setting name="enable_priority" value="false"/>
<setting name="priority" value="0"/>
<setting name="enable_custom_name" value="false"/>
</struct>
</config_set>
</instance>
<instance name="NVIC" uuid="0329fbca-00e5-4ec4-9f79-3cb65a7b267a" type="nvic" type_id="nvic_57b5eef3774cc60acaede6f5b8bddc67" mode="general" peripheral="NVIC" enabled="true" comment="" custom_name_enabled="false" editing_lock="false">
<config_set name="nvic">
<array name="interrupt_table"/>
<array name="interrupts"/>
</config_set>
</instance>
</instances>
</functional_group>
</functional_groups>
<components>
<component name="system" uuid="59cf1b09-8396-4bf9-bed6-03d5457c292f" type_id="system_54b53072540eeeb8f8e9343e71f28176">
<config_set_global name="global_system_definitions">
<setting name="user_definitions" value=""/>
<setting name="user_includes" value=""/>
</config_set_global>
</component>
<component name="msg" uuid="7d589e9f-7522-408c-b7c8-42770920766f" type_id="msg_6e2baaf3b97dbeef01c0043275f9a0e7">
<config_set_global name="global_messages"/>
</component>
<component name="gpio_adapter_common" uuid="e9da5e16-1f55-49be-87ec-af8cfd4a4105" type_id="gpio_adapter_common_57579b9ac814fe26bf95df0a384c36b6">
<config_set_global name="global_gpio_adapter_common" quick_selection="default"/>
</component>
<component name="generic_uart" uuid="9dc7a034-9408-4852-9990-a713693635ee" type_id="generic_uart_8cae00565451cf2346eb1b8c624e73a6">
<config_set_global name="global_uart"/>
</component>
<component name="generic_can" uuid="28ec81a8-d7ea-4363-9330-20b877c481f6" type_id="generic_can_1bfdd78b1af214566c1f23cf6a582d80">
<config_set_global name="global_can"/>
</component>
<component name="uart_cmsis_common" uuid="774dd0a0-63ed-4846-b9d7-dfd082d810e3" type_id="uart_cmsis_common_9cb8e302497aa696fdbb5a4fd622c2a8">
<config_set_global name="global_USART_CMSIS_common" quick_selection="default"/>
</component>
<component name="generic_enet" uuid="77cd333e-4adc-4c6e-8b18-bbe349d78182" type_id="generic_enet_74db5c914f0ddbe47d86af40cb77a619">
<config_set_global name="global_enet"/>
</component>
</components>
</periphs>
<tee name="TEE" version="4.0" enabled="false" update_project_code="true">
<generated_project_files/>
<tee_profile>
<processor_version>N/A</processor_version>
</tee_profile>
</tee>
</tools>
</configuration>

14
managed_components/espressif__tinyusb/hw/bsp/imxrt/boards/mimxrt1020_evk/board.cmake Normal file
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@@ -0,0 +1,14 @@
set(MCU_VARIANT MIMXRT1021)
set(JLINK_DEVICE MIMXRT1021xxx5A)
set(PYOCD_TARGET mimxrt1020)
set(NXPLINK_DEVICE MIMXRT1021xxxxx:EVK-MIMXRT1020)
function(update_board TARGET)
target_sources(${TARGET} PUBLIC
${CMAKE_CURRENT_FUNCTION_LIST_DIR}/evkmimxrt1020_flexspi_nor_config.c
)
target_compile_definitions(${TARGET} PUBLIC
CPU_MIMXRT1021DAG5A
)
endfunction()

55
managed_components/espressif__tinyusb/hw/bsp/imxrt/boards/mimxrt1020_evk/board.h Normal file
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@@ -0,0 +1,55 @@
/*
* The MIT License (MIT)
*
* Copyright (c) 2019, Ha Thach (tinyusb.org)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* This file is part of the TinyUSB stack.
*/
/* metadata:
name: i.MX RT1020 Evaluation Kit
url: https://www.nxp.com/design/design-center/development-boards-and-designs/MIMXRT1020-EVK
*/
#ifndef BOARD_MIMXRT1020_EVK_H_
#define BOARD_MIMXRT1020_EVK_H_
// required since iMXRT MCUX-SDK include this file for board size
#define BOARD_FLASH_SIZE (0x800000U)
// LED: IOMUXC_GPIO_AD_B0_05_GPIO1_IO05
#define LED_PORT BOARD_INITPINS_USER_LED_PERIPHERAL
#define LED_PIN BOARD_INITPINS_USER_LED_CHANNEL
#define LED_STATE_ON 0
// SW8 button: IOMUXC_SNVS_WAKEUP_GPIO5_IO00
#define BUTTON_PORT BOARD_INITPINS_USER_BUTTON_GPIO
#define BUTTON_PIN BOARD_INITPINS_USER_BUTTON_GPIO_PIN
#define BUTTON_STATE_ACTIVE 0
// UART: IOMUXC_GPIO_AD_B0_07_LPUART1_RX, IOMUXC_GPIO_AD_B0_06_LPUART1_TX
#define UART_PORT LPUART1
#define UART_CLK_ROOT BOARD_BOOTCLOCKRUN_UART_CLK_ROOT
static inline void BOARD_ConfigMPU(void) {
}
#endif

11
managed_components/espressif__tinyusb/hw/bsp/imxrt/boards/mimxrt1020_evk/board.mk Normal file
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@@ -0,0 +1,11 @@
CFLAGS += -DCPU_MIMXRT1021DAG5A
MCU_VARIANT = MIMXRT1021
# For flash-jlink target
JLINK_DEVICE = MIMXRT1021xxx5A
# For flash-pyocd target
PYOCD_TARGET = mimxrt1020
# flash using pyocd
flash: flash-pyocd

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managed_components/espressif__tinyusb/hw/bsp/imxrt/boards/mimxrt1020_evk/board/clock_config.c Normal file
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/*
* How to setup clock using clock driver functions:
*
* 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock.
*
* 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock.
*
* 3. Call CLOCK_SetMux() to configure corresponding clock source for target clock out.
*
* 4. Call CLOCK_SetDiv() to configure corresponding clock divider for target clock out.
*
* 5. Call CLOCK_SetXtalFreq() to set XTAL frequency based on board settings.
*
*/
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!GlobalInfo
product: Clocks v11.0
processor: MIMXRT1021xxxxx
package_id: MIMXRT1021DAG5A
mcu_data: ksdk2_0
processor_version: 13.0.2
board: MIMXRT1020-EVK
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
#include "clock_config.h"
#include "fsl_iomuxc.h"
/*******************************************************************************
* Definitions
******************************************************************************/
/*******************************************************************************
* Variables
******************************************************************************/
/*******************************************************************************
************************ BOARD_InitBootClocks function ************************
******************************************************************************/
void BOARD_InitBootClocks(void)
{
BOARD_BootClockRUN();
}
/*******************************************************************************
********************** Configuration BOARD_BootClockRUN ***********************
******************************************************************************/
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!Configuration
name: BOARD_BootClockRUN
called_from_default_init: true
outputs:
- {id: AHB_CLK_ROOT.outFreq, value: 500 MHz}
- {id: CAN_CLK_ROOT.outFreq, value: 40 MHz}
- {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz}
- {id: CLK_1M.outFreq, value: 1 MHz}
- {id: CLK_24M.outFreq, value: 24 MHz}
- {id: ENET_500M_REF_CLK.outFreq, value: 500 MHz}
- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz}
- {id: FLEXSPI_CLK_ROOT.outFreq, value: 132 MHz}
- {id: GPT1_ipg_clk_highfreq.outFreq, value: 62.5 MHz}
- {id: GPT2_ipg_clk_highfreq.outFreq, value: 62.5 MHz}
- {id: IPG_CLK_ROOT.outFreq, value: 125 MHz}
- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz}
- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz}
- {id: MQS_MCLK.outFreq, value: 1080/17 MHz}
- {id: PERCLK_CLK_ROOT.outFreq, value: 62.5 MHz}
- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz}
- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz}
- {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz}
- {id: SAI1_MCLK3.outFreq, value: 30 MHz}
- {id: SAI2_CLK_ROOT.outFreq, value: 1080/17 MHz}
- {id: SAI2_MCLK1.outFreq, value: 1080/17 MHz}
- {id: SAI2_MCLK3.outFreq, value: 30 MHz}
- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz}
- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz}
- {id: SAI3_MCLK3.outFreq, value: 30 MHz}
- {id: SEMC_CLK_ROOT.outFreq, value: 62.5 MHz}
- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz}
- {id: TRACE_CLK_ROOT.outFreq, value: 132 MHz}
- {id: UART_CLK_ROOT.outFreq, value: 80 MHz}
- {id: USBPHY1_CLK.outFreq, value: 480 MHz}
- {id: USDHC1_CLK_ROOT.outFreq, value: 176 MHz}
- {id: USDHC2_CLK_ROOT.outFreq, value: 176 MHz}
settings:
- {id: CCM.AHB_PODF.scale, value: '1', locked: true}
- {id: CCM.ARM_PODF.scale, value: '1', locked: true}
- {id: CCM.FLEXSPI_PODF.scale, value: '4', locked: true}
- {id: CCM.FLEXSPI_SEL.sel, value: CCM_ANALOG.PLL2_PFD2_CLK}
- {id: CCM.IPG_PODF.scale, value: '4'}
- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true}
- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true}
- {id: CCM.PRE_PERIPH_CLK_SEL.sel, value: CCM.ARM_PODF}
- {id: CCM.SEMC_PODF.scale, value: '8'}
- {id: CCM.TRACE_CLK_SEL.sel, value: CCM_ANALOG.PLL2_MAIN_CLK}
- {id: CCM.TRACE_PODF.scale, value: '4', locked: true}
- {id: CCM.USDHC1_PODF.scale, value: '3', locked: true}
- {id: CCM.USDHC2_PODF.scale, value: '3', locked: true}
- {id: CCM_ANALOG.PLL2.denom, value: '1', locked: true}
- {id: CCM_ANALOG.PLL2.num, value: '0', locked: true}
- {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK}
- {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0}
- {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1}
- {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2}
- {id: CCM_ANALOG.PLL2_PFD2_DIV.scale, value: '18', locked: true}
- {id: CCM_ANALOG.PLL2_PFD2_MUL.scale, value: '18', locked: true}
- {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3}
- {id: CCM_ANALOG.PLL2_PFD3_DIV.scale, value: '18', locked: true}
- {id: CCM_ANALOG.PLL2_PFD3_MUL.scale, value: '18', locked: true}
- {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3}
- {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0}
- {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '22', locked: true}
- {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true}
- {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1}
- {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2}
- {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3}
- {id: CCM_ANALOG.PLL3_PFD3_DIV.scale, value: '18', locked: true}
- {id: CCM_ANALOG.PLL3_PFD3_MUL.scale, value: '18', locked: true}
- {id: CCM_ANALOG.PLL4.denom, value: '50'}
- {id: CCM_ANALOG.PLL4.div, value: '47'}
- {id: CCM_ANALOG.PLL6_BYPASS.sel, value: CCM_ANALOG.PLL6}
- {id: CCM_ANALOG_PLL_ENET_ENABLE_CFG, value: Disabled}
- {id: CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_CFG, value: Disabled}
- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_CFG, value: Enabled}
- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_OUT_CFG, value: Enabled}
- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'}
sources:
- {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/*******************************************************************************
* Variables for BOARD_BootClockRUN configuration
******************************************************************************/
const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN =
{
.loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */
.numerator = 0, /* 30 bit numerator of fractional loop divider */
.denominator = 1, /* 30 bit denominator of fractional loop divider */
.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
};
const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN =
{
.loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */
.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
};
const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN =
{
.enableClkOutput = false, /* Disable the PLL providing the ENET 125MHz reference clock */
.enableClkOutput500M = true, /* Enable the PLL providing the ENET 500MHz reference clock */
.enableClkOutput25M = false, /* Disable the PLL providing the ENET 25MHz reference clock */
.loopDivider = 1, /* Set frequency of ethernet reference clock to 50 MHz */
.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
};
/*******************************************************************************
* Code for BOARD_BootClockRUN configuration
******************************************************************************/
void BOARD_BootClockRUN(void)
{
/* Init RTC OSC clock frequency. */
CLOCK_SetRtcXtalFreq(32768U);
/* Enable 1MHz clock output. */
XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK;
/* Use free 1MHz clock output. */
XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK;
/* Set XTAL 24MHz clock frequency. */
CLOCK_SetXtalFreq(24000000U);
/* Enable XTAL 24MHz clock source. */
CLOCK_InitExternalClk(0);
/* Enable internal RC. */
CLOCK_InitRcOsc24M();
/* Switch clock source to external OSC. */
CLOCK_SwitchOsc(kCLOCK_XtalOsc);
/* Set Oscillator ready counter value. */
CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127);
/* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */
CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */
CLOCK_SetMux(kCLOCK_PeriphMux, 1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */
/* Setting the VDD_SOC to 1.25V. It is necessary to config AHB to 500Mhz. */
DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x12);
/* Waiting for DCDC_STS_DC_OK bit is asserted */
while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0))
{
}
/* Set AHB_PODF. */
CLOCK_SetDiv(kCLOCK_AhbDiv, 0);
/* Disable IPG clock gate. */
CLOCK_DisableClock(kCLOCK_Adc1);
CLOCK_DisableClock(kCLOCK_Adc2);
CLOCK_DisableClock(kCLOCK_Xbar1);
CLOCK_DisableClock(kCLOCK_Xbar2);
/* Set IPG_PODF. */
CLOCK_SetDiv(kCLOCK_IpgDiv, 3);
/* Set ARM_PODF. */
CLOCK_SetDiv(kCLOCK_ArmDiv, 0);
/* Set PERIPH_CLK2_PODF. */
CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0);
/* Disable PERCLK clock gate. */
CLOCK_DisableClock(kCLOCK_Gpt1);
CLOCK_DisableClock(kCLOCK_Gpt1S);
CLOCK_DisableClock(kCLOCK_Gpt2);
CLOCK_DisableClock(kCLOCK_Gpt2S);
CLOCK_DisableClock(kCLOCK_Pit);
/* Set PERCLK_PODF. */
CLOCK_SetDiv(kCLOCK_PerclkDiv, 1);
/* Disable USDHC1 clock gate. */
CLOCK_DisableClock(kCLOCK_Usdhc1);
/* Set USDHC1_PODF. */
CLOCK_SetDiv(kCLOCK_Usdhc1Div, 2);
/* Set Usdhc1 clock source. */
CLOCK_SetMux(kCLOCK_Usdhc1Mux, 0);
/* Disable USDHC2 clock gate. */
CLOCK_DisableClock(kCLOCK_Usdhc2);
/* Set USDHC2_PODF. */
CLOCK_SetDiv(kCLOCK_Usdhc2Div, 2);
/* Set Usdhc2 clock source. */
CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0);
/* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
* With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
* Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
#ifndef SKIP_SYSCLK_INIT
/* Disable Semc clock gate. */
CLOCK_DisableClock(kCLOCK_Semc);
/* Set SEMC_PODF. */
CLOCK_SetDiv(kCLOCK_SemcDiv, 7);
/* Set Semc alt clock source. */
CLOCK_SetMux(kCLOCK_SemcAltMux, 0);
/* Set Semc clock source. */
CLOCK_SetMux(kCLOCK_SemcMux, 0);
#endif
/* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
* With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
* Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
/* Disable Flexspi clock gate. */
CLOCK_DisableClock(kCLOCK_FlexSpi);
/* Set FLEXSPI_PODF. */
CLOCK_SetDiv(kCLOCK_FlexspiDiv, 3);
/* Set Flexspi clock source. */
CLOCK_SetMux(kCLOCK_FlexspiMux, 2);
#endif
/* Disable LPSPI clock gate. */
CLOCK_DisableClock(kCLOCK_Lpspi1);
CLOCK_DisableClock(kCLOCK_Lpspi2);
CLOCK_DisableClock(kCLOCK_Lpspi3);
CLOCK_DisableClock(kCLOCK_Lpspi4);
/* Set LPSPI_PODF. */
CLOCK_SetDiv(kCLOCK_LpspiDiv, 4);
/* Set Lpspi clock source. */
CLOCK_SetMux(kCLOCK_LpspiMux, 2);
/* Disable TRACE clock gate. */
CLOCK_DisableClock(kCLOCK_Trace);
/* Set TRACE_PODF. */
CLOCK_SetDiv(kCLOCK_TraceDiv, 3);
/* Set Trace clock source. */
CLOCK_SetMux(kCLOCK_TraceMux, 0);
/* Disable SAI1 clock gate. */
CLOCK_DisableClock(kCLOCK_Sai1);
/* Set SAI1_CLK_PRED. */
CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3);
/* Set SAI1_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_Sai1Div, 1);
/* Set Sai1 clock source. */
CLOCK_SetMux(kCLOCK_Sai1Mux, 0);
/* Disable SAI2 clock gate. */
CLOCK_DisableClock(kCLOCK_Sai2);
/* Set SAI2_CLK_PRED. */
CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3);
/* Set SAI2_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_Sai2Div, 1);
/* Set Sai2 clock source. */
CLOCK_SetMux(kCLOCK_Sai2Mux, 0);
/* Disable SAI3 clock gate. */
CLOCK_DisableClock(kCLOCK_Sai3);
/* Set SAI3_CLK_PRED. */
CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3);
/* Set SAI3_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_Sai3Div, 1);
/* Set Sai3 clock source. */
CLOCK_SetMux(kCLOCK_Sai3Mux, 0);
/* Disable Lpi2c clock gate. */
CLOCK_DisableClock(kCLOCK_Lpi2c1);
CLOCK_DisableClock(kCLOCK_Lpi2c2);
CLOCK_DisableClock(kCLOCK_Lpi2c3);
/* Set LPI2C_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0);
/* Set Lpi2c clock source. */
CLOCK_SetMux(kCLOCK_Lpi2cMux, 0);
/* Disable CAN clock gate. */
CLOCK_DisableClock(kCLOCK_Can1);
CLOCK_DisableClock(kCLOCK_Can2);
CLOCK_DisableClock(kCLOCK_Can1S);
CLOCK_DisableClock(kCLOCK_Can2S);
/* Set CAN_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_CanDiv, 1);
/* Set Can clock source. */
CLOCK_SetMux(kCLOCK_CanMux, 2);
/* Disable UART clock gate. */
CLOCK_DisableClock(kCLOCK_Lpuart1);
CLOCK_DisableClock(kCLOCK_Lpuart2);
CLOCK_DisableClock(kCLOCK_Lpuart3);
CLOCK_DisableClock(kCLOCK_Lpuart4);
CLOCK_DisableClock(kCLOCK_Lpuart5);
CLOCK_DisableClock(kCLOCK_Lpuart6);
CLOCK_DisableClock(kCLOCK_Lpuart7);
CLOCK_DisableClock(kCLOCK_Lpuart8);
/* Set UART_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_UartDiv, 0);
/* Set Uart clock source. */
CLOCK_SetMux(kCLOCK_UartMux, 0);
/* Disable SPDIF clock gate. */
CLOCK_DisableClock(kCLOCK_Spdif);
/* Set SPDIF0_CLK_PRED. */
CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1);
/* Set SPDIF0_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_Spdif0Div, 7);
/* Set Spdif clock source. */
CLOCK_SetMux(kCLOCK_SpdifMux, 3);
/* Disable Flexio1 clock gate. */
CLOCK_DisableClock(kCLOCK_Flexio1);
/* Set FLEXIO1_CLK_PRED. */
CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1);
/* Set FLEXIO1_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_Flexio1Div, 7);
/* Set Flexio1 clock source. */
CLOCK_SetMux(kCLOCK_Flexio1Mux, 3);
/* Set Pll3 sw clock source. */
CLOCK_SetMux(kCLOCK_Pll3SwMux, 0);
/* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
* With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
* Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
#ifndef SKIP_SYSCLK_INIT
#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1)
#warning "SKIP_SYSCLK_INIT should be defined to keep system pll (selected to be SEMC source clock in SDK projects) unchanged."
#endif
/* Init System PLL. */
CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN);
/* Init System pfd0. */
CLOCK_InitSysPfd(kCLOCK_Pfd0, 27);
/* Init System pfd1. */
CLOCK_InitSysPfd(kCLOCK_Pfd1, 16);
/* Init System pfd2. */
CLOCK_InitSysPfd(kCLOCK_Pfd2, 18);
/* Init System pfd3. */
CLOCK_InitSysPfd(kCLOCK_Pfd3, 18);
#endif
/* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
* With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
* Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
/* Init Usb1 PLL. */
CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN);
/* Init Usb1 pfd0. */
CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 22);
/* Init Usb1 pfd1. */
CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16);
/* Init Usb1 pfd2. */
CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17);
/* Init Usb1 pfd3. */
CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 18);
#endif
/* DeInit Audio PLL. */
CLOCK_DeinitAudioPll();
/* Bypass Audio PLL. */
CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1);
/* Set divider for Audio PLL. */
CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK;
CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK;
/* Enable Audio PLL output. */
CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK;
/* Init Enet PLL. */
CLOCK_InitEnetPll(&enetPllConfig_BOARD_BootClockRUN);
/* Set preperiph clock source. */
CLOCK_SetMux(kCLOCK_PrePeriphMux, 3);
/* Set periph clock source. */
CLOCK_SetMux(kCLOCK_PeriphMux, 0);
/* Set periph clock2 clock source. */
CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
/* Set per clock source. */
CLOCK_SetMux(kCLOCK_PerclkMux, 0);
/* Set clock out1 divider. */
CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0);
/* Set clock out1 source. */
CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1);
/* Set clock out2 divider. */
CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0);
/* Set clock out2 source. */
CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(3);
/* Set clock out1 drives clock out1. */
CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK;
/* Disable clock out1. */
CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK;
/* Disable clock out2. */
CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK;
/* Set SAI1 MCLK1 clock source. */
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0);
/* Set SAI1 MCLK2 clock source. */
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0);
/* Set SAI1 MCLK3 clock source. */
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0);
/* Set SAI2 MCLK3 clock source. */
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0);
/* Set SAI3 MCLK3 clock source. */
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
/* Set MQS configuration. */
IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0);
/* Set ENET Ref clock source. */
#if defined(IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK)
IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK;
#elif defined(IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK)
/* Backward compatibility for original bitfield name */
IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK;
#else
#error "Neither IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK nor IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK is defined."
#endif /* defined(IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK) */
/* Set GPT1 High frequency reference clock source. */
IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK;
/* Set GPT2 High frequency reference clock source. */
IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK;
/* Set SystemCoreClock variable. */
SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
}

108
managed_components/espressif__tinyusb/hw/bsp/imxrt/boards/mimxrt1020_evk/board/clock_config.h Normal file
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#ifndef _CLOCK_CONFIG_H_
#define _CLOCK_CONFIG_H_
#include "fsl_common.h"
/*******************************************************************************
* Definitions
******************************************************************************/
#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */
#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */
/*******************************************************************************
************************ BOARD_InitBootClocks function ************************
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/
/*!
* @brief This function executes default configuration of clocks.
*
*/
void BOARD_InitBootClocks(void);
#if defined(__cplusplus)
}
#endif /* __cplusplus*/
/*******************************************************************************
********************** Configuration BOARD_BootClockRUN ***********************
******************************************************************************/
/*******************************************************************************
* Definitions for BOARD_BootClockRUN configuration
******************************************************************************/
#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 500000000U /*!< Core clock frequency: 500000000Hz */
/* Clock outputs (values are in Hz): */
#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT 500000000UL
#define BOARD_BOOTCLOCKRUN_CAN_CLK_ROOT 40000000UL
#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL
#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL
#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL
#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL
#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL
#define BOARD_BOOTCLOCKRUN_ENET_125M_CLK 0UL
#define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK 0UL
#define BOARD_BOOTCLOCKRUN_ENET_500M_REF_CLK 500000000UL
#define BOARD_BOOTCLOCKRUN_ENET_REF_CLK 0UL
#define BOARD_BOOTCLOCKRUN_ENET_TX_CLK 0UL
#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL
#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 132000000UL
#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 62500000UL
#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 62500000UL
#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 125000000UL
#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL
#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL
#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL
#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 62500000UL
#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL
#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 63529411UL
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 63529411UL
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 30000000UL
#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL
#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 62500000UL
#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL
#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL
#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 132000000UL
#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL
#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK 480000000UL
#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 176000000UL
#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 176000000UL
/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration.
*/
extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN;
/*! @brief Sys PLL for BOARD_BootClockRUN configuration.
*/
extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN;
/*! @brief Enet PLL set for BOARD_BootClockRUN configuration.
*/
extern const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN;
/*******************************************************************************
* API for BOARD_BootClockRUN configuration
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/
/*!
* @brief This function executes configuration of clocks.
*
*/
void BOARD_BootClockRUN(void);
#if defined(__cplusplus)
}
#endif /* __cplusplus*/
#endif /* _CLOCK_CONFIG_H_ */

342
managed_components/espressif__tinyusb/hw/bsp/imxrt/boards/mimxrt1020_evk/board/pin_mux.c Normal file
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@@ -0,0 +1,342 @@
/***********************************************************************************************************************
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
**********************************************************************************************************************/
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!GlobalInfo
product: Pins v13.1
processor: MIMXRT1021xxxxx
package_id: MIMXRT1021DAG5A
mcu_data: ksdk2_0
processor_version: 13.0.2
board: MIMXRT1020-EVK
external_user_signals: {}
pin_labels:
- {pin_num: '52', pin_signal: WAKEUP, label: USER_BUTTON, identifier: USER_BUTTON}
- {pin_num: '106', pin_signal: GPIO_AD_B0_05, label: 'JTAG_nTRST/J16[3]/USER_LED/J17[5]', identifier: USER_LED}
power_domains: {NVCC_GPIO: '3.3'}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
#include "fsl_common.h"
#include "fsl_iomuxc.h"
#include "fsl_gpio.h"
#include "pin_mux.h"
/* FUNCTION ************************************************************************************************************
*
* Function Name : BOARD_InitBootPins
* Description : Calls initialization functions.
*
* END ****************************************************************************************************************/
void BOARD_InitBootPins(void) {
BOARD_InitPins();
BOARD_InitDEBUG_UARTPins();
}
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
BOARD_InitPins:
- options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'}
- pin_list:
- {pin_num: '52', peripheral: GPIO5, signal: 'gpio_io, 00', pin_signal: WAKEUP, direction: INPUT}
- {pin_num: '106', peripheral: GPIO1, signal: 'gpio_io, 05', pin_signal: GPIO_AD_B0_05, direction: OUTPUT, pull_keeper_select: Keeper}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
/* FUNCTION ************************************************************************************************************
*
* Function Name : BOARD_InitPins
* Description : Configures pin routing and optionally pin electrical features.
*
* END ****************************************************************************************************************/
void BOARD_InitPins(void) {
CLOCK_EnableClock(kCLOCK_Iomuxc);
CLOCK_EnableClock(kCLOCK_IomuxcSnvs);
/* GPIO configuration of USER_LED on GPIO_AD_B0_05 (pin 106) */
gpio_pin_config_t USER_LED_config = {
.direction = kGPIO_DigitalOutput,
.outputLogic = 0U,
.interruptMode = kGPIO_NoIntmode
};
/* Initialize GPIO functionality on GPIO_AD_B0_05 (pin 106) */
GPIO_PinInit(GPIO1, 5U, &USER_LED_config);
/* GPIO configuration of USER_BUTTON on WAKEUP (pin 52) */
gpio_pin_config_t USER_BUTTON_config = {
.direction = kGPIO_DigitalInput,
.outputLogic = 0U,
.interruptMode = kGPIO_NoIntmode
};
/* Initialize GPIO functionality on WAKEUP (pin 52) */
GPIO_PinInit(GPIO5, 0U, &USER_BUTTON_config);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_05_GPIO1_IO05, 0U);
IOMUXC_SetPinMux(IOMUXC_SNVS_WAKEUP_GPIO5_IO00, 0U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_05_GPIO1_IO05, 0x50A0U);
}
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
BOARD_InitDEBUG_UARTPins:
- options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'}
- pin_list:
- {pin_num: '101', peripheral: LPUART1, signal: RX, pin_signal: GPIO_AD_B0_07}
- {pin_num: '105', peripheral: LPUART1, signal: TX, pin_signal: GPIO_AD_B0_06}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
/* FUNCTION ************************************************************************************************************
*
* Function Name : BOARD_InitDEBUG_UARTPins
* Description : Configures pin routing and optionally pin electrical features.
*
* END ****************************************************************************************************************/
void BOARD_InitDEBUG_UARTPins(void) {
CLOCK_EnableClock(kCLOCK_Iomuxc);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_06_LPUART1_TX, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_07_LPUART1_RX, 0U);
}
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
BOARD_InitSDRAMPins:
- options: {coreID: core0, enableClock: 'true'}
- pin_list:
- {pin_num: '142', peripheral: SEMC, signal: 'ADDR, 00', pin_signal: GPIO_EMC_16}
- {pin_num: '141', peripheral: SEMC, signal: 'ADDR, 01', pin_signal: GPIO_EMC_17}
- {pin_num: '140', peripheral: SEMC, signal: 'ADDR, 02', pin_signal: GPIO_EMC_18}
- {pin_num: '139', peripheral: SEMC, signal: 'ADDR, 03', pin_signal: GPIO_EMC_19}
- {pin_num: '138', peripheral: SEMC, signal: 'ADDR, 04', pin_signal: GPIO_EMC_20}
- {pin_num: '136', peripheral: SEMC, signal: 'ADDR, 06', pin_signal: GPIO_EMC_22}
- {pin_num: '137', peripheral: SEMC, signal: 'ADDR, 05', pin_signal: GPIO_EMC_21}
- {pin_num: '133', peripheral: SEMC, signal: 'ADDR, 07', pin_signal: GPIO_EMC_23}
- {pin_num: '132', peripheral: SEMC, signal: 'ADDR, 08', pin_signal: GPIO_EMC_24}
- {pin_num: '131', peripheral: SEMC, signal: 'ADDR, 09', pin_signal: GPIO_EMC_25}
- {pin_num: '143', peripheral: SEMC, signal: 'ADDR, 10', pin_signal: GPIO_EMC_15}
- {pin_num: '130', peripheral: SEMC, signal: 'ADDR, 11', pin_signal: GPIO_EMC_26}
- {pin_num: '129', peripheral: SEMC, signal: 'ADDR, 12', pin_signal: GPIO_EMC_27}
- {pin_num: '2', peripheral: SEMC, signal: 'BA, 0', pin_signal: GPIO_EMC_13}
- {pin_num: '1', peripheral: SEMC, signal: 'BA, 1', pin_signal: GPIO_EMC_14}
- {pin_num: '7', peripheral: SEMC, signal: semc_cas, pin_signal: GPIO_EMC_10}
- {pin_num: '127', peripheral: SEMC, signal: semc_cke, pin_signal: GPIO_EMC_29}
- {pin_num: '126', peripheral: SEMC, signal: semc_clk, pin_signal: GPIO_EMC_30}
- {pin_num: '3', peripheral: SEMC, signal: 'CS, 0', pin_signal: GPIO_EMC_12}
- {pin_num: '8', peripheral: SEMC, signal: semc_we, pin_signal: GPIO_EMC_09}
- {pin_num: '4', peripheral: SEMC, signal: semc_ras, pin_signal: GPIO_EMC_11}
- {pin_num: '128', peripheral: SEMC, signal: semc_dqs, pin_signal: GPIO_EMC_28}
- {pin_num: '125', peripheral: SEMC, signal: 'DM, 1', pin_signal: GPIO_EMC_31}
- {pin_num: '9', peripheral: SEMC, signal: 'DM, 0', pin_signal: GPIO_EMC_08}
- {pin_num: '117', peripheral: SEMC, signal: 'DATA, 15', pin_signal: GPIO_EMC_39}
- {pin_num: '118', peripheral: SEMC, signal: 'DATA, 14', pin_signal: GPIO_EMC_38}
- {pin_num: '119', peripheral: SEMC, signal: 'DATA, 13', pin_signal: GPIO_EMC_37}
- {pin_num: '120', peripheral: SEMC, signal: 'DATA, 12', pin_signal: GPIO_EMC_36}
- {pin_num: '122', peripheral: SEMC, signal: 'DATA, 10', pin_signal: GPIO_EMC_34}
- {pin_num: '121', peripheral: SEMC, signal: 'DATA, 11', pin_signal: GPIO_EMC_35}
- {pin_num: '123', peripheral: SEMC, signal: 'DATA, 09', pin_signal: GPIO_EMC_33}
- {pin_num: '124', peripheral: SEMC, signal: 'DATA, 08', pin_signal: GPIO_EMC_32}
- {pin_num: '10', peripheral: SEMC, signal: 'DATA, 07', pin_signal: GPIO_EMC_07}
- {pin_num: '12', peripheral: SEMC, signal: 'DATA, 06', pin_signal: GPIO_EMC_06}
- {pin_num: '13', peripheral: SEMC, signal: 'DATA, 05', pin_signal: GPIO_EMC_05}
- {pin_num: '14', peripheral: SEMC, signal: 'DATA, 04', pin_signal: GPIO_EMC_04}
- {pin_num: '15', peripheral: SEMC, signal: 'DATA, 03', pin_signal: GPIO_EMC_03}
- {pin_num: '16', peripheral: SEMC, signal: 'DATA, 02', pin_signal: GPIO_EMC_02}
- {pin_num: '17', peripheral: SEMC, signal: 'DATA, 01', pin_signal: GPIO_EMC_01}
- {pin_num: '18', peripheral: SEMC, signal: 'DATA, 00', pin_signal: GPIO_EMC_00}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
/* FUNCTION ************************************************************************************************************
*
* Function Name : BOARD_InitSDRAMPins
* Description : Configures pin routing and optionally pin electrical features.
*
* END ****************************************************************************************************************/
void BOARD_InitSDRAMPins(void) {
CLOCK_EnableClock(kCLOCK_Iomuxc);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_00_SEMC_DATA00, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_01_SEMC_DATA01, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_02_SEMC_DATA02, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_03_SEMC_DATA03, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_04_SEMC_DATA04, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_05_SEMC_DATA05, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_06_SEMC_DATA06, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_07_SEMC_DATA07, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_08_SEMC_DM00, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_09_SEMC_WE, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_10_SEMC_CAS, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_11_SEMC_RAS, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_12_SEMC_CS0, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_13_SEMC_BA0, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_14_SEMC_BA1, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_15_SEMC_ADDR10, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_16_SEMC_ADDR00, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_17_SEMC_ADDR01, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_18_SEMC_ADDR02, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_19_SEMC_ADDR03, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_20_SEMC_ADDR04, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_21_SEMC_ADDR05, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_22_SEMC_ADDR06, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_23_SEMC_ADDR07, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_24_SEMC_ADDR08, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_25_SEMC_ADDR09, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_26_SEMC_ADDR11, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_27_SEMC_ADDR12, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_28_SEMC_DQS, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_29_SEMC_CKE, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_30_SEMC_CLK, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_31_SEMC_DM01, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_32_SEMC_DATA08, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_33_SEMC_DATA09, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_34_SEMC_DATA10, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_35_SEMC_DATA11, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_36_SEMC_DATA12, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_37_SEMC_DATA13, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_38_SEMC_DATA14, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_39_SEMC_DATA15, 0U);
}
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
BOARD_InitCANPins:
- options: {coreID: core0, enableClock: 'true'}
- pin_list:
- {pin_num: '32', peripheral: CAN1, signal: RX, pin_signal: GPIO_SD_B1_01}
- {pin_num: '33', peripheral: CAN1, signal: TX, pin_signal: GPIO_SD_B1_00}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
/* FUNCTION ************************************************************************************************************
*
* Function Name : BOARD_InitCANPins
* Description : Configures pin routing and optionally pin electrical features.
*
* END ****************************************************************************************************************/
void BOARD_InitCANPins(void) {
CLOCK_EnableClock(kCLOCK_Iomuxc);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_00_FLEXCAN1_TX, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_01_FLEXCAN1_RX, 0U);
}
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
BOARD_InitENETPins:
- options: {coreID: core0, enableClock: 'true'}
- pin_list:
- {pin_num: '97', peripheral: ENET, signal: enet_rx_en, pin_signal: GPIO_AD_B0_11}
- {pin_num: '84', peripheral: GPIO1, signal: 'gpio_io, 22', pin_signal: GPIO_AD_B1_06}
- {pin_num: '107', peripheral: GPIO1, signal: 'gpio_io, 04', pin_signal: GPIO_AD_B0_04}
- {pin_num: '100', peripheral: ENET, signal: enet_tx_clk, pin_signal: GPIO_AD_B0_08}
- {pin_num: '95', peripheral: ENET, signal: enet_tx_en, pin_signal: GPIO_AD_B0_13}
- {pin_num: '93', peripheral: ENET, signal: 'enet_tx_data, 1', pin_signal: GPIO_AD_B0_15}
- {pin_num: '94', peripheral: ENET, signal: 'enet_tx_data, 0', pin_signal: GPIO_AD_B0_14}
- {pin_num: '96', peripheral: ENET, signal: enet_rx_er, pin_signal: GPIO_AD_B0_12}
- {pin_num: '99', peripheral: ENET, signal: 'enet_rx_data, 1', pin_signal: GPIO_AD_B0_09}
- {pin_num: '98', peripheral: ENET, signal: 'enet_rx_data, 0', pin_signal: GPIO_AD_B0_10}
- {pin_num: '116', peripheral: ENET, signal: enet_mdio, pin_signal: GPIO_EMC_40}
- {pin_num: '115', peripheral: ENET, signal: enet_mdc, pin_signal: GPIO_EMC_41}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
/* FUNCTION ************************************************************************************************************
*
* Function Name : BOARD_InitENETPins
* Description : Configures pin routing and optionally pin electrical features.
*
* END ****************************************************************************************************************/
void BOARD_InitENETPins(void) {
CLOCK_EnableClock(kCLOCK_Iomuxc);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_04_GPIO1_IO04, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_08_ENET_TX_CLK, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_09_ENET_RDATA01, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_10_ENET_RDATA00, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_11_ENET_RX_EN, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_12_ENET_RX_ER, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_13_ENET_TX_EN, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_14_ENET_TDATA00, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_15_ENET_TDATA01, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_06_GPIO1_IO22, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_40_ENET_MDIO, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_41_ENET_MDC, 0U);
}
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
BOARD_InitUSDHCPins:
- options: {coreID: core0, enableClock: 'true'}
- pin_list:
- {pin_num: '45', peripheral: USDHC1, signal: usdhc_clk, pin_signal: GPIO_SD_B0_03}
- {pin_num: '46', peripheral: USDHC1, signal: usdhc_cmd, pin_signal: GPIO_SD_B0_02}
- {pin_num: '43', peripheral: USDHC1, signal: 'usdhc_data, 0', pin_signal: GPIO_SD_B0_04}
- {pin_num: '42', peripheral: USDHC1, signal: 'usdhc_data, 1', pin_signal: GPIO_SD_B0_05}
- {pin_num: '48', peripheral: USDHC1, signal: 'usdhc_data, 2', pin_signal: GPIO_SD_B0_00}
- {pin_num: '47', peripheral: USDHC1, signal: 'usdhc_data, 3', pin_signal: GPIO_SD_B0_01}
- {pin_num: '41', peripheral: GPIO3, signal: 'gpio_io, 19', pin_signal: GPIO_SD_B0_06}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
/* FUNCTION ************************************************************************************************************
*
* Function Name : BOARD_InitUSDHCPins
* Description : Configures pin routing and optionally pin electrical features.
*
* END ****************************************************************************************************************/
void BOARD_InitUSDHCPins(void) {
CLOCK_EnableClock(kCLOCK_Iomuxc);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_00_USDHC1_DATA2, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_01_USDHC1_DATA3, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_02_USDHC1_CMD, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_03_USDHC1_CLK, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_04_USDHC1_DATA0, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_05_USDHC1_DATA1, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_06_GPIO3_IO19, 0U);
}
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
BOARD_InitQSPIPins:
- options: {coreID: core0, enableClock: 'true'}
- pin_list:
- {pin_num: '24', peripheral: FLEXSPI, signal: FLEXSPI_A_SCLK, pin_signal: GPIO_SD_B1_07}
- {pin_num: '23', peripheral: FLEXSPI, signal: FLEXSPI_A_DATA0, pin_signal: GPIO_SD_B1_08}
- {pin_num: '21', peripheral: FLEXSPI, signal: FLEXSPI_A_DATA1, pin_signal: GPIO_SD_B1_10}
- {pin_num: '22', peripheral: FLEXSPI, signal: FLEXSPI_A_DATA2, pin_signal: GPIO_SD_B1_09}
- {pin_num: '25', peripheral: FLEXSPI, signal: FLEXSPI_A_DATA3, pin_signal: GPIO_SD_B1_06}
- {pin_num: '19', peripheral: FLEXSPI, signal: FLEXSPI_A_SS0_B, pin_signal: GPIO_SD_B1_11}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
/* FUNCTION ************************************************************************************************************
*
* Function Name : BOARD_InitQSPIPins
* Description : Configures pin routing and optionally pin electrical features.
*
* END ****************************************************************************************************************/
void BOARD_InitQSPIPins(void) {
CLOCK_EnableClock(kCLOCK_Iomuxc);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_06_FLEXSPI_A_DATA03, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_07_FLEXSPI_A_SCLK, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_08_FLEXSPI_A_DATA00, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_09_FLEXSPI_A_DATA02, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_10_FLEXSPI_A_DATA01, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_11_FLEXSPI_A_SS0_B, 0U);
}
/***********************************************************************************************************************
* EOF
**********************************************************************************************************************/

542
managed_components/espressif__tinyusb/hw/bsp/imxrt/boards/mimxrt1020_evk/board/pin_mux.h Normal file
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/***********************************************************************************************************************
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
**********************************************************************************************************************/
#ifndef _PIN_MUX_H_
#define _PIN_MUX_H_
/***********************************************************************************************************************
* Definitions
**********************************************************************************************************************/
/*! @brief Direction type */
typedef enum _pin_mux_direction
{
kPIN_MUX_DirectionInput = 0U, /* Input direction */
kPIN_MUX_DirectionOutput = 1U, /* Output direction */
kPIN_MUX_DirectionInputOrOutput = 2U /* Input or output direction */
} pin_mux_direction_t;
/*!
* @addtogroup pin_mux
* @{
*/
/***********************************************************************************************************************
* API
**********************************************************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif
/*!
* @brief Calls initialization functions.
*
*/
void BOARD_InitBootPins(void);
/* WAKEUP (number 52), USER_BUTTON */
/* Routed pin properties */
#define BOARD_INITPINS_USER_BUTTON_PERIPHERAL GPIO5 /*!< Peripheral name */
#define BOARD_INITPINS_USER_BUTTON_SIGNAL gpio_io /*!< Signal name */
#define BOARD_INITPINS_USER_BUTTON_CHANNEL 0U /*!< Signal channel */
/* Symbols to be used with GPIO driver */
#define BOARD_INITPINS_USER_BUTTON_GPIO GPIO5 /*!< GPIO peripheral base pointer */
#define BOARD_INITPINS_USER_BUTTON_GPIO_PIN 0U /*!< GPIO pin number */
#define BOARD_INITPINS_USER_BUTTON_GPIO_PIN_MASK (1U << 0U) /*!< GPIO pin mask */
#define BOARD_INITPINS_USER_BUTTON_PORT GPIO5 /*!< PORT peripheral base pointer */
#define BOARD_INITPINS_USER_BUTTON_PIN 0U /*!< PORT pin number */
#define BOARD_INITPINS_USER_BUTTON_PIN_MASK (1U << 0U) /*!< PORT pin mask */
/* GPIO_AD_B0_05 (number 106), JTAG_nTRST/J16[3]/USER_LED/J17[5] */
/* Routed pin properties */
#define BOARD_INITPINS_USER_LED_PERIPHERAL GPIO1 /*!< Peripheral name */
#define BOARD_INITPINS_USER_LED_SIGNAL gpio_io /*!< Signal name */
#define BOARD_INITPINS_USER_LED_CHANNEL 5U /*!< Signal channel */
/* Symbols to be used with GPIO driver */
#define BOARD_INITPINS_USER_LED_GPIO GPIO1 /*!< GPIO peripheral base pointer */
#define BOARD_INITPINS_USER_LED_GPIO_PIN 5U /*!< GPIO pin number */
#define BOARD_INITPINS_USER_LED_GPIO_PIN_MASK (1U << 5U) /*!< GPIO pin mask */
#define BOARD_INITPINS_USER_LED_PORT GPIO1 /*!< PORT peripheral base pointer */
#define BOARD_INITPINS_USER_LED_PIN 5U /*!< PORT pin number */
#define BOARD_INITPINS_USER_LED_PIN_MASK (1U << 5U) /*!< PORT pin mask */
/*!
* @brief Configures pin routing and optionally pin electrical features.
*
*/
void BOARD_InitPins(void);
/* GPIO_AD_B0_07 (number 101), UART1_RXD/J17[4] */
/* Routed pin properties */
#define BOARD_INITDEBUG_UARTPINS_UART1_RXD_PERIPHERAL LPUART1 /*!< Peripheral name */
#define BOARD_INITDEBUG_UARTPINS_UART1_RXD_SIGNAL RX /*!< Signal name */
/* GPIO_AD_B0_06 (number 105), UART1_TXD/J17[6] */
/* Routed pin properties */
#define BOARD_INITDEBUG_UARTPINS_UART1_TXD_PERIPHERAL LPUART1 /*!< Peripheral name */
#define BOARD_INITDEBUG_UARTPINS_UART1_TXD_SIGNAL TX /*!< Signal name */
/*!
* @brief Configures pin routing and optionally pin electrical features.
*
*/
void BOARD_InitDEBUG_UARTPins(void);
/* GPIO_EMC_16 (number 142), SEMC_A0/U14[23]/BOOT_MODE[0] */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_A0_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_A0_SIGNAL ADDR /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_A0_CHANNEL 0U /*!< Signal channel */
/* GPIO_EMC_17 (number 141), SEMC_A1/U14[24]/BOOT_MODE[1] */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_A1_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_A1_SIGNAL ADDR /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_A1_CHANNEL 1U /*!< Signal channel */
/* GPIO_EMC_18 (number 140), SEMC_A2/U14[25]/BT_CFG[0] */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_A2_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_A2_SIGNAL ADDR /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_A2_CHANNEL 2U /*!< Signal channel */
/* GPIO_EMC_19 (number 139), SEMC_A3/U14[26]/BT_CFG[1] */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_A3_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_A3_SIGNAL ADDR /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_A3_CHANNEL 3U /*!< Signal channel */
/* GPIO_EMC_20 (number 138), SEMC_A4/U14[29]/BT_CFG[2] */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_A4_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_A4_SIGNAL ADDR /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_A4_CHANNEL 4U /*!< Signal channel */
/* GPIO_EMC_22 (number 136), SEMC_A6/U14[31]/BT_CFG[4] */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_A6_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_A6_SIGNAL ADDR /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_A6_CHANNEL 6U /*!< Signal channel */
/* GPIO_EMC_21 (number 137), SEMC_A5/U14[30]/BT_CFG[3] */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_A5_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_A5_SIGNAL ADDR /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_A5_CHANNEL 5U /*!< Signal channel */
/* GPIO_EMC_23 (number 133), SEMC_A7/U14[32]/BT_CFG[5] */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_A7_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_A7_SIGNAL ADDR /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_A7_CHANNEL 7U /*!< Signal channel */
/* GPIO_EMC_24 (number 132), SEMC_A8/U14[33]/BT_CFG[6] */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_A8_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_A8_SIGNAL ADDR /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_A8_CHANNEL 8U /*!< Signal channel */
/* GPIO_EMC_25 (number 131), SEMC_A9/U14[34]/BT_CFG[7] */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_A9_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_A9_SIGNAL ADDR /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_A9_CHANNEL 9U /*!< Signal channel */
/* GPIO_EMC_15 (number 143), SEMC_A10/U14[22] */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_A10_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_A10_SIGNAL ADDR /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_A10_CHANNEL 10U /*!< Signal channel */
/* GPIO_EMC_26 (number 130), SEMC_A11/U14[35]/BT_CFG[8] */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_A11_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_A11_SIGNAL ADDR /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_A11_CHANNEL 11U /*!< Signal channel */
/* GPIO_EMC_27 (number 129), SEMC_A12/U14[36]/BT_CFG[9] */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_A12_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_A12_SIGNAL ADDR /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_A12_CHANNEL 12U /*!< Signal channel */
/* GPIO_EMC_13 (number 2), SEMC_BA0/U14[20] */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_BA0_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_BA0_SIGNAL BA /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_BA0_CHANNEL 0U /*!< Signal channel */
/* GPIO_EMC_14 (number 1), SEMC_BA1/U14[21] */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_BA1_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_BA1_SIGNAL BA /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_BA1_CHANNEL 1U /*!< Signal channel */
/* GPIO_EMC_10 (number 7), SEMC_CAS/U14[17] */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_CAS_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_CAS_SIGNAL semc_cas /*!< Signal name */
/* GPIO_EMC_29 (number 127), SEMC_CKE/U14[37] */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_CKE_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_CKE_SIGNAL semc_cke /*!< Signal name */
/* GPIO_EMC_30 (number 126), SEMC_CLK/U14[38] */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_CLK_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_CLK_SIGNAL semc_clk /*!< Signal name */
/* GPIO_EMC_12 (number 3), SEMC_CS0/U14[19] */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_CS0_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_CS0_SIGNAL CS /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_CS0_CHANNEL 0U /*!< Signal channel */
/* GPIO_EMC_09 (number 8), SEMC_WE/U14[16] */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_WE_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_WE_SIGNAL semc_we /*!< Signal name */
/* GPIO_EMC_11 (number 4), SEMC_RAS/U14[18] */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_RAS_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_RAS_SIGNAL semc_ras /*!< Signal name */
/* GPIO_EMC_28 (number 128), SEMC_DQS */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_DQS_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_DQS_SIGNAL semc_dqs /*!< Signal name */
/* GPIO_EMC_31 (number 125), SEMC_DM1/U14[39] */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_DM1_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_DM1_SIGNAL DM /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_DM1_CHANNEL 1U /*!< Signal channel */
/* GPIO_EMC_08 (number 9), SEMC_DM0/U14[15] */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_DM0_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_DM0_SIGNAL DM /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_DM0_CHANNEL 0U /*!< Signal channel */
/* GPIO_EMC_39 (number 117), SEMC_D15/U14[53] */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_D15_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_D15_SIGNAL DATA /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_D15_CHANNEL 15U /*!< Signal channel */
/* GPIO_EMC_38 (number 118), SEMC_D14/U14[51] */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_D14_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_D14_SIGNAL DATA /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_D14_CHANNEL 14U /*!< Signal channel */
/* GPIO_EMC_37 (number 119), SEMC_D13/U14[50] */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_D13_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_D13_SIGNAL DATA /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_D13_CHANNEL 13U /*!< Signal channel */
/* GPIO_EMC_36 (number 120), SEMC_D12/U14[48] */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_D12_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_D12_SIGNAL DATA /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_D12_CHANNEL 12U /*!< Signal channel */
/* GPIO_EMC_34 (number 122), SEMC_D10/U14[45] */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_D10_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_D10_SIGNAL DATA /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_D10_CHANNEL 10U /*!< Signal channel */
/* GPIO_EMC_35 (number 121), SEMC_D11/U14[47] */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_D11_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_D11_SIGNAL DATA /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_D11_CHANNEL 11U /*!< Signal channel */
/* GPIO_EMC_33 (number 123), SEMC_D9/U14[44] */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_D9_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_D9_SIGNAL DATA /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_D9_CHANNEL 9U /*!< Signal channel */
/* GPIO_EMC_32 (number 124), SEMC_D8/U14[42] */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_D8_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_D8_SIGNAL DATA /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_D8_CHANNEL 8U /*!< Signal channel */
/* GPIO_EMC_07 (number 10), SEMC_D7/U14[13] */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_D7_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_D7_SIGNAL DATA /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_D7_CHANNEL 7U /*!< Signal channel */
/* GPIO_EMC_06 (number 12), SEMC_D6/U14[11] */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_D6_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_D6_SIGNAL DATA /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_D6_CHANNEL 6U /*!< Signal channel */
/* GPIO_EMC_05 (number 13), SEMC_D5/U14[10] */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_D5_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_D5_SIGNAL DATA /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_D5_CHANNEL 5U /*!< Signal channel */
/* GPIO_EMC_04 (number 14), SEMC_D4/U14[8] */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_D4_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_D4_SIGNAL DATA /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_D4_CHANNEL 4U /*!< Signal channel */
/* GPIO_EMC_03 (number 15), SEMC_D3/U14[7] */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_D3_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_D3_SIGNAL DATA /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_D3_CHANNEL 3U /*!< Signal channel */
/* GPIO_EMC_02 (number 16), SEMC_D2/U14[5] */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_D2_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_D2_SIGNAL DATA /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_D2_CHANNEL 2U /*!< Signal channel */
/* GPIO_EMC_01 (number 17), SEMC_D1/U14[4] */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_D1_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_D1_SIGNAL DATA /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_D1_CHANNEL 1U /*!< Signal channel */
/* GPIO_EMC_00 (number 18), SEMC_D0/U14[2] */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_D0_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_D0_SIGNAL DATA /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_D0_CHANNEL 0U /*!< Signal channel */
/*!
* @brief Configures pin routing and optionally pin electrical features.
*
*/
void BOARD_InitSDRAMPins(void);
/* GPIO_SD_B1_01 (number 32), CAN1_RX/U9[4] */
/* Routed pin properties */
#define BOARD_INITCANPINS_CAN1_RX_PERIPHERAL CAN1 /*!< Peripheral name */
#define BOARD_INITCANPINS_CAN1_RX_SIGNAL RX /*!< Signal name */
/* GPIO_SD_B1_00 (number 33), CAN1_TX/U9[1] */
/* Routed pin properties */
#define BOARD_INITCANPINS_CAN1_TX_PERIPHERAL CAN1 /*!< Peripheral name */
#define BOARD_INITCANPINS_CAN1_TX_SIGNAL TX /*!< Signal name */
/*!
* @brief Configures pin routing and optionally pin electrical features.
*
*/
void BOARD_InitCANPins(void);
/* GPIO_AD_B0_11 (number 97), ENET_CRS_DV/U11[18]/J19[3] */
/* Routed pin properties */
#define BOARD_INITENETPINS_ENET_CRS_DV_PERIPHERAL ENET /*!< Peripheral name */
#define BOARD_INITENETPINS_ENET_CRS_DV_SIGNAL enet_rx_en /*!< Signal name */
/* GPIO_AD_B1_06 (number 84), ENET_INT/U11[21]/J17[8] */
/* Routed pin properties */
#define BOARD_INITENETPINS_ENET_INT_PERIPHERAL GPIO1 /*!< Peripheral name */
#define BOARD_INITENETPINS_ENET_INT_SIGNAL gpio_io /*!< Signal name */
#define BOARD_INITENETPINS_ENET_INT_CHANNEL 22U /*!< Signal channel */
/* Symbols to be used with GPIO driver */
#define BOARD_INITENETPINS_ENET_INT_GPIO GPIO1 /*!< GPIO peripheral base pointer */
#define BOARD_INITENETPINS_ENET_INT_GPIO_PIN 22U /*!< GPIO pin number */
#define BOARD_INITENETPINS_ENET_INT_GPIO_PIN_MASK (1U << 22U) /*!< GPIO pin mask */
#define BOARD_INITENETPINS_ENET_INT_PORT GPIO1 /*!< PORT peripheral base pointer */
#define BOARD_INITENETPINS_ENET_INT_PIN 22U /*!< PORT pin number */
#define BOARD_INITENETPINS_ENET_INT_PIN_MASK (1U << 22U) /*!< PORT pin mask */
/* GPIO_AD_B0_04 (number 107), JTAG_TDO/J16[13]/ENET_RST/U11[32] */
/* Routed pin properties */
#define BOARD_INITENETPINS_ENET_RST_PERIPHERAL GPIO1 /*!< Peripheral name */
#define BOARD_INITENETPINS_ENET_RST_SIGNAL gpio_io /*!< Signal name */
#define BOARD_INITENETPINS_ENET_RST_CHANNEL 4U /*!< Signal channel */
/* Symbols to be used with GPIO driver */
#define BOARD_INITENETPINS_ENET_RST_GPIO GPIO1 /*!< GPIO peripheral base pointer */
#define BOARD_INITENETPINS_ENET_RST_GPIO_PIN 4U /*!< GPIO pin number */
#define BOARD_INITENETPINS_ENET_RST_GPIO_PIN_MASK (1U << 4U) /*!< GPIO pin mask */
#define BOARD_INITENETPINS_ENET_RST_PORT GPIO1 /*!< PORT peripheral base pointer */
#define BOARD_INITENETPINS_ENET_RST_PIN 4U /*!< PORT pin number */
#define BOARD_INITENETPINS_ENET_RST_PIN_MASK (1U << 4U) /*!< PORT pin mask */
/* GPIO_AD_B0_08 (number 100), ENET_TX_CLK/U11[9] */
/* Routed pin properties */
#define BOARD_INITENETPINS_ENET_TX_CLK_PERIPHERAL ENET /*!< Peripheral name */
#define BOARD_INITENETPINS_ENET_TX_CLK_SIGNAL enet_tx_clk /*!< Signal name */
/* GPIO_AD_B0_13 (number 95), ENET_TXEN/U11[23]/J19[5] */
/* Routed pin properties */
#define BOARD_INITENETPINS_ENET_TXEN_PERIPHERAL ENET /*!< Peripheral name */
#define BOARD_INITENETPINS_ENET_TXEN_SIGNAL enet_tx_en /*!< Signal name */
/* GPIO_AD_B0_15 (number 93), ENET_TXD1/U11[25]/J19[2] */
/* Routed pin properties */
#define BOARD_INITENETPINS_ENET_TXD1_PERIPHERAL ENET /*!< Peripheral name */
#define BOARD_INITENETPINS_ENET_TXD1_SIGNAL enet_tx_data /*!< Signal name */
#define BOARD_INITENETPINS_ENET_TXD1_CHANNEL 1U /*!< Signal channel */
/* GPIO_AD_B0_14 (number 94), ENET_TXD0/U11[24]/J17[7] */
/* Routed pin properties */
#define BOARD_INITENETPINS_ENET_TXD0_PERIPHERAL ENET /*!< Peripheral name */
#define BOARD_INITENETPINS_ENET_TXD0_SIGNAL enet_tx_data /*!< Signal name */
#define BOARD_INITENETPINS_ENET_TXD0_CHANNEL 0U /*!< Signal channel */
/* GPIO_AD_B0_12 (number 96), ENET_RXER/U11[20]/J19[4] */
/* Routed pin properties */
#define BOARD_INITENETPINS_ENET_RXER_PERIPHERAL ENET /*!< Peripheral name */
#define BOARD_INITENETPINS_ENET_RXER_SIGNAL enet_rx_er /*!< Signal name */
/* GPIO_AD_B0_09 (number 99), ENET_RXD1/U11[15]/J17[3] */
/* Routed pin properties */
#define BOARD_INITENETPINS_ENET_RXD1_PERIPHERAL ENET /*!< Peripheral name */
#define BOARD_INITENETPINS_ENET_RXD1_SIGNAL enet_rx_data /*!< Signal name */
#define BOARD_INITENETPINS_ENET_RXD1_CHANNEL 1U /*!< Signal channel */
/* GPIO_AD_B0_10 (number 98), ENET_RXD0/U11[16]/J19[6] */
/* Routed pin properties */
#define BOARD_INITENETPINS_ENET_RXD0_PERIPHERAL ENET /*!< Peripheral name */
#define BOARD_INITENETPINS_ENET_RXD0_SIGNAL enet_rx_data /*!< Signal name */
#define BOARD_INITENETPINS_ENET_RXD0_CHANNEL 0U /*!< Signal channel */
/* GPIO_EMC_40 (number 116), ENET_MDIO/U11[11] */
/* Routed pin properties */
#define BOARD_INITENETPINS_ENET_MDIO_PERIPHERAL ENET /*!< Peripheral name */
#define BOARD_INITENETPINS_ENET_MDIO_SIGNAL enet_mdio /*!< Signal name */
/* GPIO_EMC_41 (number 115), ENET_MDC/U11[12] */
/* Routed pin properties */
#define BOARD_INITENETPINS_ENET_MDC_PERIPHERAL ENET /*!< Peripheral name */
#define BOARD_INITENETPINS_ENET_MDC_SIGNAL enet_mdc /*!< Signal name */
/*!
* @brief Configures pin routing and optionally pin electrical features.
*
*/
void BOARD_InitENETPins(void);
/* GPIO_SD_B0_03 (number 45), SD1_CLK/J15[5] */
/* Routed pin properties */
#define BOARD_INITUSDHCPINS_SD1_CLK_PERIPHERAL USDHC1 /*!< Peripheral name */
#define BOARD_INITUSDHCPINS_SD1_CLK_SIGNAL usdhc_clk /*!< Signal name */
/* GPIO_SD_B0_02 (number 46), SD1_CMD/J15[3] */
/* Routed pin properties */
#define BOARD_INITUSDHCPINS_SD1_CMD_PERIPHERAL USDHC1 /*!< Peripheral name */
#define BOARD_INITUSDHCPINS_SD1_CMD_SIGNAL usdhc_cmd /*!< Signal name */
/* GPIO_SD_B0_04 (number 43), SD1_D0/J15[7] */
/* Routed pin properties */
#define BOARD_INITUSDHCPINS_SD1_D0_PERIPHERAL USDHC1 /*!< Peripheral name */
#define BOARD_INITUSDHCPINS_SD1_D0_SIGNAL usdhc_data /*!< Signal name */
#define BOARD_INITUSDHCPINS_SD1_D0_CHANNEL 0U /*!< Signal channel */
/* GPIO_SD_B0_05 (number 42), SD1_D1/J15[8] */
/* Routed pin properties */
#define BOARD_INITUSDHCPINS_SD1_D1_PERIPHERAL USDHC1 /*!< Peripheral name */
#define BOARD_INITUSDHCPINS_SD1_D1_SIGNAL usdhc_data /*!< Signal name */
#define BOARD_INITUSDHCPINS_SD1_D1_CHANNEL 1U /*!< Signal channel */
/* GPIO_SD_B0_00 (number 48), SD1_D2/J15[1] */
/* Routed pin properties */
#define BOARD_INITUSDHCPINS_SD1_D2_PERIPHERAL USDHC1 /*!< Peripheral name */
#define BOARD_INITUSDHCPINS_SD1_D2_SIGNAL usdhc_data /*!< Signal name */
#define BOARD_INITUSDHCPINS_SD1_D2_CHANNEL 2U /*!< Signal channel */
/* GPIO_SD_B0_01 (number 47), SD1_D3/J15[2] */
/* Routed pin properties */
#define BOARD_INITUSDHCPINS_SD1_D3_PERIPHERAL USDHC1 /*!< Peripheral name */
#define BOARD_INITUSDHCPINS_SD1_D3_SIGNAL usdhc_data /*!< Signal name */
#define BOARD_INITUSDHCPINS_SD1_D3_CHANNEL 3U /*!< Signal channel */
/* GPIO_SD_B0_06 (number 41), SD_CD_SW/J15[9] */
/* Routed pin properties */
#define BOARD_INITUSDHCPINS_SD_CD_SW_PERIPHERAL GPIO3 /*!< Peripheral name */
#define BOARD_INITUSDHCPINS_SD_CD_SW_SIGNAL gpio_io /*!< Signal name */
#define BOARD_INITUSDHCPINS_SD_CD_SW_CHANNEL 19U /*!< Signal channel */
/* Symbols to be used with GPIO driver */
#define BOARD_INITUSDHCPINS_SD_CD_SW_GPIO GPIO3 /*!< GPIO peripheral base pointer */
#define BOARD_INITUSDHCPINS_SD_CD_SW_GPIO_PIN 19U /*!< GPIO pin number */
#define BOARD_INITUSDHCPINS_SD_CD_SW_GPIO_PIN_MASK (1U << 19U) /*!< GPIO pin mask */
#define BOARD_INITUSDHCPINS_SD_CD_SW_PORT GPIO3 /*!< PORT peripheral base pointer */
#define BOARD_INITUSDHCPINS_SD_CD_SW_PIN 19U /*!< PORT pin number */
#define BOARD_INITUSDHCPINS_SD_CD_SW_PIN_MASK (1U << 19U) /*!< PORT pin mask */
/*!
* @brief Configures pin routing and optionally pin electrical features.
*
*/
void BOARD_InitUSDHCPins(void);
/* GPIO_SD_B1_07 (number 24), FlexSPI_CLK/U13[6] */
/* Routed pin properties */
#define BOARD_INITQSPIPINS_FlexSPI_CLK_PERIPHERAL FLEXSPI /*!< Peripheral name */
#define BOARD_INITQSPIPINS_FlexSPI_CLK_SIGNAL FLEXSPI_A_SCLK /*!< Signal name */
/* GPIO_SD_B1_08 (number 23), FlexSPI_D0_A/U13[5] */
/* Routed pin properties */
#define BOARD_INITQSPIPINS_FlexSPI_D0_A_PERIPHERAL FLEXSPI /*!< Peripheral name */
#define BOARD_INITQSPIPINS_FlexSPI_D0_A_SIGNAL FLEXSPI_A_DATA0 /*!< Signal name */
/* GPIO_SD_B1_10 (number 21), FlexSPI_D1_A/U13[2] */
/* Routed pin properties */
#define BOARD_INITQSPIPINS_FlexSPI_D1_A_PERIPHERAL FLEXSPI /*!< Peripheral name */
#define BOARD_INITQSPIPINS_FlexSPI_D1_A_SIGNAL FLEXSPI_A_DATA1 /*!< Signal name */
/* GPIO_SD_B1_09 (number 22), FlexSPI_D2_A/U13[3] */
/* Routed pin properties */
#define BOARD_INITQSPIPINS_FlexSPI_D2_A_PERIPHERAL FLEXSPI /*!< Peripheral name */
#define BOARD_INITQSPIPINS_FlexSPI_D2_A_SIGNAL FLEXSPI_A_DATA2 /*!< Signal name */
/* GPIO_SD_B1_06 (number 25), FlexSPI_D3_A/U13[7] */
/* Routed pin properties */
#define BOARD_INITQSPIPINS_FlexSPI_D3_A_PERIPHERAL FLEXSPI /*!< Peripheral name */
#define BOARD_INITQSPIPINS_FlexSPI_D3_A_SIGNAL FLEXSPI_A_DATA3 /*!< Signal name */
/* GPIO_SD_B1_11 (number 19), FlexSPI_SS0/U13[1] */
/* Routed pin properties */
#define BOARD_INITQSPIPINS_FlexSPI_SS0_PERIPHERAL FLEXSPI /*!< Peripheral name */
#define BOARD_INITQSPIPINS_FlexSPI_SS0_SIGNAL FLEXSPI_A_SS0_B /*!< Signal name */
/*!
* @brief Configures pin routing and optionally pin electrical features.
*
*/
void BOARD_InitQSPIPins(void);
#if defined(__cplusplus)
}
#endif
/*!
* @}
*/
#endif /* _PIN_MUX_H_ */
/***********************************************************************************************************************
* EOF
**********************************************************************************************************************/

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managed_components/espressif__tinyusb/hw/bsp/imxrt/boards/mimxrt1020_evk/evkmimxrt1020_flexspi_nor_config.c Normal file
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/*
* Copyright 2018 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "evkmimxrt1020_flexspi_nor_config.h"
/* Component ID definition, used by tools. */
#ifndef FSL_COMPONENT_ID
#define FSL_COMPONENT_ID "platform.drivers.xip_board"
#endif
/*******************************************************************************
* Code
******************************************************************************/
#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
__attribute__((section(".boot_hdr.conf")))
#elif defined(__ICCARM__)
#pragma location = ".boot_hdr.conf"
#endif
const flexspi_nor_config_t qspiflash_config = {
.memConfig =
{
.tag = FLEXSPI_CFG_BLK_TAG,
.version = FLEXSPI_CFG_BLK_VERSION,
.readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad,
.csHoldTime = 3u,
.csSetupTime = 3u,
// Enable DDR mode, Wordaddassable, Safe configuration, Differential clock
.sflashPadType = kSerialFlash_4Pads,
.serialClkFreq = kFlexSpiSerialClk_100MHz,
.sflashA1Size = 8u * 1024u * 1024u,
.lookupTable =
{
// Read LUTs
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18),
FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04),
},
},
.pageSize = 256u,
.sectorSize = 4u * 1024u,
.blockSize = 256u * 1024u,
.isUniformBlockSize = false,
};
#endif /* XIP_BOOT_HEADER_ENABLE */

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/*
* Copyright 2018 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __EVKMIMXRT1020_FLEXSPI_NOR_CONFIG__
#define __EVKMIMXRT1020_FLEXSPI_NOR_CONFIG__
#include <stdint.h>
#include <stdbool.h>
#include "fsl_common.h"
/*! @name Driver version */
/*@{*/
/*! @brief XIP_BOARD driver version 2.0.0. */
#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
/*@}*/
/* FLEXSPI memory config block related definitions */
#define FLEXSPI_CFG_BLK_TAG (0x42464346UL) // ascii "FCFB" Big Endian
#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0
#define FLEXSPI_CFG_BLK_SIZE (512)
/* FLEXSPI Feature related definitions */
#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1
/* Lookup table related definitions */
#define CMD_INDEX_READ 0
#define CMD_INDEX_READSTATUS 1
#define CMD_INDEX_WRITEENABLE 2
#define CMD_INDEX_WRITE 4
#define CMD_LUT_SEQ_IDX_READ 0
#define CMD_LUT_SEQ_IDX_READSTATUS 1
#define CMD_LUT_SEQ_IDX_WRITEENABLE 3
#define CMD_LUT_SEQ_IDX_WRITE 9
#define CMD_SDR 0x01
#define CMD_DDR 0x21
#define RADDR_SDR 0x02
#define RADDR_DDR 0x22
#define CADDR_SDR 0x03
#define CADDR_DDR 0x23
#define MODE1_SDR 0x04
#define MODE1_DDR 0x24
#define MODE2_SDR 0x05
#define MODE2_DDR 0x25
#define MODE4_SDR 0x06
#define MODE4_DDR 0x26
#define MODE8_SDR 0x07
#define MODE8_DDR 0x27
#define WRITE_SDR 0x08
#define WRITE_DDR 0x28
#define READ_SDR 0x09
#define READ_DDR 0x29
#define LEARN_SDR 0x0A
#define LEARN_DDR 0x2A
#define DATSZ_SDR 0x0B
#define DATSZ_DDR 0x2B
#define DUMMY_SDR 0x0C
#define DUMMY_DDR 0x2C
#define DUMMY_RWDS_SDR 0x0D
#define DUMMY_RWDS_DDR 0x2D
#define JMP_ON_CS 0x1F
#define STOP 0
#define FLEXSPI_1PAD 0
#define FLEXSPI_2PAD 1
#define FLEXSPI_4PAD 2
#define FLEXSPI_8PAD 3
#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \
(FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \
FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))
//!@brief Definitions for FlexSPI Serial Clock Frequency
typedef enum _FlexSpiSerialClockFreq
{
kFlexSpiSerialClk_30MHz = 1,
kFlexSpiSerialClk_50MHz = 2,
kFlexSpiSerialClk_60MHz = 3,
kFlexSpiSerialClk_75MHz = 4,
kFlexSpiSerialClk_80MHz = 5,
kFlexSpiSerialClk_100MHz = 6,
kFlexSpiSerialClk_133MHz = 7,
kFlexSpiSerialClk_166MHz = 8,
kFlexSpiSerialClk_200MHz = 9,
} flexspi_serial_clk_freq_t;
//!@brief FlexSPI clock configuration type
enum
{
kFlexSpiClk_SDR, //!< Clock configure for SDR mode
kFlexSpiClk_DDR, //!< Clock configurat for DDR mode
};
//!@brief FlexSPI Read Sample Clock Source definition
typedef enum _FlashReadSampleClkSource
{
kFlexSPIReadSampleClk_LoopbackInternally = 0,
kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1,
kFlexSPIReadSampleClk_LoopbackFromSckPad = 2,
kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3,
} flexspi_read_sample_clk_t;
//!@brief Misc feature bit definitions
enum
{
kFlexSpiMiscOffset_DiffClkEnable = 0, //!< Bit for Differential clock enable
kFlexSpiMiscOffset_Ck2Enable = 1, //!< Bit for CK2 enable
kFlexSpiMiscOffset_ParallelEnable = 2, //!< Bit for Parallel mode enable
kFlexSpiMiscOffset_WordAddressableEnable = 3, //!< Bit for Word Addressable enable
kFlexSpiMiscOffset_SafeConfigFreqEnable = 4, //!< Bit for Safe Configuration Frequency enable
kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, //!< Bit for Pad setting override enable
kFlexSpiMiscOffset_DdrModeEnable = 6, //!< Bit for DDR clock confiuration indication.
};
//!@brief Flash Type Definition
enum
{
kFlexSpiDeviceType_SerialNOR = 1, //!< Flash devices are Serial NOR
kFlexSpiDeviceType_SerialNAND = 2, //!< Flash devices are Serial NAND
kFlexSpiDeviceType_SerialRAM = 3, //!< Flash devices are Serial RAM/HyperFLASH
kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND
kFlexSpiDeviceType_MCP_NOR_RAM = 0x13, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial RAMs
};
//!@brief Flash Pad Definitions
enum
{
kSerialFlash_1Pad = 1,
kSerialFlash_2Pads = 2,
kSerialFlash_4Pads = 4,
kSerialFlash_8Pads = 8,
};
//!@brief FlexSPI LUT Sequence structure
typedef struct _lut_sequence
{
uint8_t seqNum; //!< Sequence Number, valid number: 1-16
uint8_t seqId; //!< Sequence Index, valid number: 0-15
uint16_t reserved;
} flexspi_lut_seq_t;
//!@brief Flash Configuration Command Type
enum
{
kDeviceConfigCmdType_Generic, //!< Generic command, for example: configure dummy cycles, drive strength, etc
kDeviceConfigCmdType_QuadEnable, //!< Quad Enable command
kDeviceConfigCmdType_Spi2Xpi, //!< Switch from SPI to DPI/QPI/OPI mode
kDeviceConfigCmdType_Xpi2Spi, //!< Switch from DPI/QPI/OPI to SPI mode
kDeviceConfigCmdType_Spi2NoCmd, //!< Switch to 0-4-4/0-8-8 mode
kDeviceConfigCmdType_Reset, //!< Reset device command
};
//!@brief FlexSPI Memory Configuration Block
typedef struct _FlexSPIConfig
{
uint32_t tag; //!< [0x000-0x003] Tag, fixed value 0x42464346UL
uint32_t version; //!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix
uint32_t reserved0; //!< [0x008-0x00b] Reserved for future use
uint8_t readSampleClkSrc; //!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3
uint8_t csHoldTime; //!< [0x00d-0x00d] CS hold time, default value: 3
uint8_t csSetupTime; //!< [0x00e-0x00e] CS setup time, default value: 3
uint8_t columnAddressWidth; //!< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For
//! Serial NAND, need to refer to datasheet
uint8_t deviceModeCfgEnable; //!< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable
uint8_t deviceModeType; //!< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch,
//! Generic configuration, etc.
uint16_t waitTimeCfgCommands; //!< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for
//! DPI/QPI/OPI switch or reset command
flexspi_lut_seq_t deviceModeSeq; //!< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt
//! sequence number, [31:16] Reserved
uint32_t deviceModeArg; //!< [0x018-0x01b] Argument/Parameter for device configuration
uint8_t configCmdEnable; //!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable
uint8_t configModeType[3]; //!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe
flexspi_lut_seq_t
configCmdSeqs[3]; //!< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq
uint32_t reserved1; //!< [0x02c-0x02f] Reserved for future use
uint32_t configCmdArgs[3]; //!< [0x030-0x03b] Arguments/Parameters for device Configuration commands
uint32_t reserved2; //!< [0x03c-0x03f] Reserved for future use
uint32_t controllerMiscOption; //!< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more
//! details
uint8_t deviceType; //!< [0x044-0x044] Device Type: See Flash Type Definition for more details
uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal
uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequency, device specific definitions, See System Boot
//! Chapter for more details
uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot
//! be done using 1 LUT sequence, currently, only applicable to HyperFLASH
uint32_t reserved3[2]; //!< [0x048-0x04f] Reserved for future use
uint32_t sflashA1Size; //!< [0x050-0x053] Size of Flash connected to A1
uint32_t sflashA2Size; //!< [0x054-0x057] Size of Flash connected to A2
uint32_t sflashB1Size; //!< [0x058-0x05b] Size of Flash connected to B1
uint32_t sflashB2Size; //!< [0x05c-0x05f] Size of Flash connected to B2
uint32_t csPadSettingOverride; //!< [0x060-0x063] CS pad setting override value
uint32_t sclkPadSettingOverride; //!< [0x064-0x067] SCK pad setting override value
uint32_t dataPadSettingOverride; //!< [0x068-0x06b] data pad setting override value
uint32_t dqsPadSettingOverride; //!< [0x06c-0x06f] DQS pad setting override value
uint32_t timeoutInMs; //!< [0x070-0x073] Timeout threshold for read status command
uint32_t commandInterval; //!< [0x074-0x077] CS deselect interval between two commands
uint16_t dataValidTime[2]; //!< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns
uint16_t busyOffset; //!< [0x07c-0x07d] Busy offset, valid value: 0-31
uint16_t busyBitPolarity; //!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 -
//! busy flag is 0 when flash device is busy
uint32_t lookupTable[64]; //!< [0x080-0x17f] Lookup table holds Flash command sequences
flexspi_lut_seq_t lutCustomSeq[12]; //!< [0x180-0x1af] Customizable LUT Sequences
uint32_t reserved4[4]; //!< [0x1b0-0x1bf] Reserved for future use
} flexspi_mem_config_t;
/* */
#define NOR_CMD_INDEX_READ CMD_INDEX_READ //!< 0
#define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS //!< 1
#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE //!< 2
#define NOR_CMD_INDEX_ERASESECTOR 3 //!< 3
#define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE //!< 4
#define NOR_CMD_INDEX_CHIPERASE 5 //!< 5
#define NOR_CMD_INDEX_DUMMY 6 //!< 6
#define NOR_CMD_INDEX_ERASEBLOCK 7 //!< 7
#define NOR_CMD_LUT_SEQ_IDX_READ CMD_LUT_SEQ_IDX_READ //!< 0 READ LUT sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_READSTATUS \
CMD_LUT_SEQ_IDX_READSTATUS //!< 1 Read Status LUT sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \
2 //!< 2 Read status DPI/QPI/OPI sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE \
CMD_LUT_SEQ_IDX_WRITEENABLE //!< 3 Write Enable sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \
4 //!< 4 Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5 //!< 5 Erase Sector sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8 //!< 8 Erase Block sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM \
CMD_LUT_SEQ_IDX_WRITE //!< 9 Program sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11 //!< 11 Chip Erase sequence in lookupTable id stored in config block
#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13 //!< 13 Read SFDP sequence in lookupTable id stored in config block
#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \
14 //!< 14 Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \
15 //!< 15 Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config blobk
/*
* Serial NOR configuration block
*/
typedef struct _flexspi_nor_config
{
flexspi_mem_config_t memConfig; //!< Common memory configuration info via FlexSPI
uint32_t pageSize; //!< Page size of Serial NOR
uint32_t sectorSize; //!< Sector size of Serial NOR
uint8_t ipcmdSerialClkFreq; //!< Clock frequency for IP command
uint8_t isUniformBlockSize; //!< Sector/Block size is the same
uint8_t reserved0[2]; //!< Reserved for future use
uint8_t serialNorType; //!< Serial NOR Flash type: 0/1/2/3
uint8_t needExitNoCmdMode; //!< Need to exit NoCmd mode before other IP command
uint8_t halfClkForNonReadCmd; //!< Half the Serial Clock for non-read command: true/false
uint8_t needRestoreNoCmdMode; //!< Need to Restore NoCmd mode after IP command execution
uint32_t blockSize; //!< Block size
uint32_t reserve2[11]; //!< Reserved for future use
} flexspi_nor_config_t;
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __cplusplus
}
#endif
#endif /* __EVKMIMXRT1020_FLEXSPI_NOR_CONFIG__ */

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<?xml version="1.0" encoding= "UTF-8" ?>
<configuration name="MIMXRT1020-EVK" xsi:schemaLocation="http://mcuxpresso.nxp.com/XSD/mex_configuration_13 http://mcuxpresso.nxp.com/XSD/mex_configuration_13.xsd" uuid="a558cc6e-82c2-41f9-9f55-0348efc7896f" version="13" xmlns="http://mcuxpresso.nxp.com/XSD/mex_configuration_13" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<common>
<processor>MIMXRT1021xxxxx</processor>
<package>MIMXRT1021DAG5A</package>
<board>MIMXRT1020-EVK</board>
<board_revision>A3</board_revision>
<mcu_data>ksdk2_0</mcu_data>
<cores selected="core0">
<core name="Cortex-M7F" id="core0" description="M7 core"/>
</cores>
<description></description>
</common>
<preferences>
<validate_boot_init_only>false</validate_boot_init_only>
<generate_extended_information>false</generate_extended_information>
<generate_code_modified_registers_only>false</generate_code_modified_registers_only>
<update_include_paths>true</update_include_paths>
<generate_registers_defines>false</generate_registers_defines>
</preferences>
<tools>
<pins name="Pins" version="13.1" enabled="true" update_project_code="true">
<generated_project_files>
<file path="board/pin_mux.c" update_enabled="true"/>
<file path="board/pin_mux.h" update_enabled="true"/>
</generated_project_files>
<pins_profile>
<processor_version>13.0.2</processor_version>
<pin_labels>
<pin_label pin_num="52" pin_signal="WAKEUP" label="USER_BUTTON" identifier="USER_BUTTON"/>
<pin_label pin_num="106" pin_signal="GPIO_AD_B0_05" label="JTAG_nTRST/J16[3]/USER_LED/J17[5]" identifier="USER_LED"/>
</pin_labels>
<external_user_signals>
<properties/>
</external_user_signals>
<power_domains>
<power_domain name="NVCC_GPIO" value="3.3"/>
</power_domains>
</pins_profile>
<functions_list>
<function name="BOARD_InitPins">
<description>Configures pin routing and optionally pin electrical features.</description>
<options>
<callFromInitBoot>true</callFromInitBoot>
<coreID>core0</coreID>
<enableClock>true</enableClock>
</options>
<dependencies>
<dependency resourceType="Peripheral" resourceId="GPIO5" description="Peripheral GPIO5 is not initialized" problem_level="1" source="Pins:BOARD_InitPins">
<feature name="initialized" evaluation="equal">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitPins">
<feature name="enabled" evaluation="equal" configuration="core0">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitPins">
<feature name="enabled" evaluation="equal" configuration="core0">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.igpio" description="Pins initialization requires the IGPIO Driver in the project." problem_level="2" source="Pins:BOARD_InitPins">
<feature name="enabled" evaluation="equal" configuration="core0">
<data>true</data>
</feature>
</dependency>
</dependencies>
<pins>
<pin peripheral="GPIO5" signal="gpio_io, 00" pin_num="52" pin_signal="WAKEUP">
<pin_features>
<pin_feature name="direction" value="INPUT"/>
</pin_features>
</pin>
<pin peripheral="GPIO1" signal="gpio_io, 05" pin_num="106" pin_signal="GPIO_AD_B0_05">
<pin_features>
<pin_feature name="direction" value="OUTPUT"/>
<pin_feature name="pull_keeper_select" value="Keeper"/>
</pin_features>
</pin>
</pins>
</function>
<function name="BOARD_InitDEBUG_UARTPins">
<description>Configures pin routing and optionally pin electrical features.</description>
<options>
<callFromInitBoot>true</callFromInitBoot>
<coreID>core0</coreID>
<enableClock>true</enableClock>
</options>
<dependencies>
<dependency resourceType="Peripheral" resourceId="LPUART1" description="Peripheral LPUART1 is not initialized" problem_level="1" source="Pins:BOARD_InitDEBUG_UARTPins">
<feature name="initialized" evaluation="equal">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitDEBUG_UARTPins">
<feature name="enabled" evaluation="equal" configuration="core0">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitDEBUG_UARTPins">
<feature name="enabled" evaluation="equal" configuration="core0">
<data>true</data>
</feature>
</dependency>
</dependencies>
<pins>
<pin peripheral="LPUART1" signal="RX" pin_num="101" pin_signal="GPIO_AD_B0_07"/>
<pin peripheral="LPUART1" signal="TX" pin_num="105" pin_signal="GPIO_AD_B0_06"/>
</pins>
</function>
<function name="BOARD_InitSDRAMPins">
<description>Configures pin routing and optionally pin electrical features.</description>
<options>
<coreID>core0</coreID>
<enableClock>true</enableClock>
</options>
<dependencies>
<dependency resourceType="Peripheral" resourceId="SEMC" description="Peripheral SEMC is not initialized" problem_level="1" source="Pins:BOARD_InitSDRAMPins">
<feature name="initialized" evaluation="equal">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitSDRAMPins">
<feature name="enabled" evaluation="equal" configuration="core0">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitSDRAMPins">
<feature name="enabled" evaluation="equal" configuration="core0">
<data>true</data>
</feature>
</dependency>
</dependencies>
<pins>
<pin peripheral="SEMC" signal="ADDR, 00" pin_num="142" pin_signal="GPIO_EMC_16"/>
<pin peripheral="SEMC" signal="ADDR, 01" pin_num="141" pin_signal="GPIO_EMC_17"/>
<pin peripheral="SEMC" signal="ADDR, 02" pin_num="140" pin_signal="GPIO_EMC_18"/>
<pin peripheral="SEMC" signal="ADDR, 03" pin_num="139" pin_signal="GPIO_EMC_19"/>
<pin peripheral="SEMC" signal="ADDR, 04" pin_num="138" pin_signal="GPIO_EMC_20"/>
<pin peripheral="SEMC" signal="ADDR, 06" pin_num="136" pin_signal="GPIO_EMC_22"/>
<pin peripheral="SEMC" signal="ADDR, 05" pin_num="137" pin_signal="GPIO_EMC_21"/>
<pin peripheral="SEMC" signal="ADDR, 07" pin_num="133" pin_signal="GPIO_EMC_23"/>
<pin peripheral="SEMC" signal="ADDR, 08" pin_num="132" pin_signal="GPIO_EMC_24"/>
<pin peripheral="SEMC" signal="ADDR, 09" pin_num="131" pin_signal="GPIO_EMC_25"/>
<pin peripheral="SEMC" signal="ADDR, 10" pin_num="143" pin_signal="GPIO_EMC_15"/>
<pin peripheral="SEMC" signal="ADDR, 11" pin_num="130" pin_signal="GPIO_EMC_26"/>
<pin peripheral="SEMC" signal="ADDR, 12" pin_num="129" pin_signal="GPIO_EMC_27"/>
<pin peripheral="SEMC" signal="BA, 0" pin_num="2" pin_signal="GPIO_EMC_13"/>
<pin peripheral="SEMC" signal="BA, 1" pin_num="1" pin_signal="GPIO_EMC_14"/>
<pin peripheral="SEMC" signal="semc_cas" pin_num="7" pin_signal="GPIO_EMC_10"/>
<pin peripheral="SEMC" signal="semc_cke" pin_num="127" pin_signal="GPIO_EMC_29"/>
<pin peripheral="SEMC" signal="semc_clk" pin_num="126" pin_signal="GPIO_EMC_30"/>
<pin peripheral="SEMC" signal="CS, 0" pin_num="3" pin_signal="GPIO_EMC_12"/>
<pin peripheral="SEMC" signal="semc_we" pin_num="8" pin_signal="GPIO_EMC_09"/>
<pin peripheral="SEMC" signal="semc_ras" pin_num="4" pin_signal="GPIO_EMC_11"/>
<pin peripheral="SEMC" signal="semc_dqs" pin_num="128" pin_signal="GPIO_EMC_28"/>
<pin peripheral="SEMC" signal="DM, 1" pin_num="125" pin_signal="GPIO_EMC_31"/>
<pin peripheral="SEMC" signal="DM, 0" pin_num="9" pin_signal="GPIO_EMC_08"/>
<pin peripheral="SEMC" signal="DATA, 15" pin_num="117" pin_signal="GPIO_EMC_39"/>
<pin peripheral="SEMC" signal="DATA, 14" pin_num="118" pin_signal="GPIO_EMC_38"/>
<pin peripheral="SEMC" signal="DATA, 13" pin_num="119" pin_signal="GPIO_EMC_37"/>
<pin peripheral="SEMC" signal="DATA, 12" pin_num="120" pin_signal="GPIO_EMC_36"/>
<pin peripheral="SEMC" signal="DATA, 10" pin_num="122" pin_signal="GPIO_EMC_34"/>
<pin peripheral="SEMC" signal="DATA, 11" pin_num="121" pin_signal="GPIO_EMC_35"/>
<pin peripheral="SEMC" signal="DATA, 09" pin_num="123" pin_signal="GPIO_EMC_33"/>
<pin peripheral="SEMC" signal="DATA, 08" pin_num="124" pin_signal="GPIO_EMC_32"/>
<pin peripheral="SEMC" signal="DATA, 07" pin_num="10" pin_signal="GPIO_EMC_07"/>
<pin peripheral="SEMC" signal="DATA, 06" pin_num="12" pin_signal="GPIO_EMC_06"/>
<pin peripheral="SEMC" signal="DATA, 05" pin_num="13" pin_signal="GPIO_EMC_05"/>
<pin peripheral="SEMC" signal="DATA, 04" pin_num="14" pin_signal="GPIO_EMC_04"/>
<pin peripheral="SEMC" signal="DATA, 03" pin_num="15" pin_signal="GPIO_EMC_03"/>
<pin peripheral="SEMC" signal="DATA, 02" pin_num="16" pin_signal="GPIO_EMC_02"/>
<pin peripheral="SEMC" signal="DATA, 01" pin_num="17" pin_signal="GPIO_EMC_01"/>
<pin peripheral="SEMC" signal="DATA, 00" pin_num="18" pin_signal="GPIO_EMC_00"/>
</pins>
</function>
<function name="BOARD_InitCANPins">
<description>Configures pin routing and optionally pin electrical features.</description>
<options>
<coreID>core0</coreID>
<enableClock>true</enableClock>
</options>
<dependencies>
<dependency resourceType="Peripheral" resourceId="CAN1" description="Peripheral CAN1 is not initialized" problem_level="1" source="Pins:BOARD_InitCANPins">
<feature name="initialized" evaluation="equal">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitCANPins">
<feature name="enabled" evaluation="equal" configuration="core0">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitCANPins">
<feature name="enabled" evaluation="equal" configuration="core0">
<data>true</data>
</feature>
</dependency>
</dependencies>
<pins>
<pin peripheral="CAN1" signal="RX" pin_num="32" pin_signal="GPIO_SD_B1_01"/>
<pin peripheral="CAN1" signal="TX" pin_num="33" pin_signal="GPIO_SD_B1_00"/>
</pins>
</function>
<function name="BOARD_InitENETPins">
<description>Configures pin routing and optionally pin electrical features.</description>
<options>
<coreID>core0</coreID>
<enableClock>true</enableClock>
</options>
<dependencies>
<dependency resourceType="Peripheral" resourceId="ENET" description="Peripheral ENET is not initialized" problem_level="1" source="Pins:BOARD_InitENETPins">
<feature name="initialized" evaluation="equal">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitENETPins">
<feature name="enabled" evaluation="equal" configuration="core0">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitENETPins">
<feature name="enabled" evaluation="equal" configuration="core0">
<data>true</data>
</feature>
</dependency>
</dependencies>
<pins>
<pin peripheral="ENET" signal="enet_rx_en" pin_num="97" pin_signal="GPIO_AD_B0_11"/>
<pin peripheral="GPIO1" signal="gpio_io, 22" pin_num="84" pin_signal="GPIO_AD_B1_06"/>
<pin peripheral="GPIO1" signal="gpio_io, 04" pin_num="107" pin_signal="GPIO_AD_B0_04"/>
<pin peripheral="ENET" signal="enet_tx_clk" pin_num="100" pin_signal="GPIO_AD_B0_08"/>
<pin peripheral="ENET" signal="enet_tx_en" pin_num="95" pin_signal="GPIO_AD_B0_13"/>
<pin peripheral="ENET" signal="enet_tx_data, 1" pin_num="93" pin_signal="GPIO_AD_B0_15"/>
<pin peripheral="ENET" signal="enet_tx_data, 0" pin_num="94" pin_signal="GPIO_AD_B0_14"/>
<pin peripheral="ENET" signal="enet_rx_er" pin_num="96" pin_signal="GPIO_AD_B0_12"/>
<pin peripheral="ENET" signal="enet_rx_data, 1" pin_num="99" pin_signal="GPIO_AD_B0_09"/>
<pin peripheral="ENET" signal="enet_rx_data, 0" pin_num="98" pin_signal="GPIO_AD_B0_10"/>
<pin peripheral="ENET" signal="enet_mdio" pin_num="116" pin_signal="GPIO_EMC_40"/>
<pin peripheral="ENET" signal="enet_mdc" pin_num="115" pin_signal="GPIO_EMC_41"/>
</pins>
</function>
<function name="BOARD_InitUSDHCPins">
<description>Configures pin routing and optionally pin electrical features.</description>
<options>
<coreID>core0</coreID>
<enableClock>true</enableClock>
</options>
<dependencies>
<dependency resourceType="Peripheral" resourceId="USDHC1" description="Peripheral USDHC1 is not initialized" problem_level="1" source="Pins:BOARD_InitUSDHCPins">
<feature name="initialized" evaluation="equal">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitUSDHCPins">
<feature name="enabled" evaluation="equal" configuration="core0">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitUSDHCPins">
<feature name="enabled" evaluation="equal" configuration="core0">
<data>true</data>
</feature>
</dependency>
</dependencies>
<pins>
<pin peripheral="USDHC1" signal="usdhc_clk" pin_num="45" pin_signal="GPIO_SD_B0_03"/>
<pin peripheral="USDHC1" signal="usdhc_cmd" pin_num="46" pin_signal="GPIO_SD_B0_02"/>
<pin peripheral="USDHC1" signal="usdhc_data, 0" pin_num="43" pin_signal="GPIO_SD_B0_04"/>
<pin peripheral="USDHC1" signal="usdhc_data, 1" pin_num="42" pin_signal="GPIO_SD_B0_05"/>
<pin peripheral="USDHC1" signal="usdhc_data, 2" pin_num="48" pin_signal="GPIO_SD_B0_00"/>
<pin peripheral="USDHC1" signal="usdhc_data, 3" pin_num="47" pin_signal="GPIO_SD_B0_01"/>
<pin peripheral="GPIO3" signal="gpio_io, 19" pin_num="41" pin_signal="GPIO_SD_B0_06"/>
</pins>
</function>
<function name="BOARD_InitQSPIPins">
<description>Configures pin routing and optionally pin electrical features.</description>
<options>
<coreID>core0</coreID>
<enableClock>true</enableClock>
</options>
<dependencies>
<dependency resourceType="Peripheral" resourceId="FLEXSPI" description="Peripheral FLEXSPI is not initialized" problem_level="1" source="Pins:BOARD_InitQSPIPins">
<feature name="initialized" evaluation="equal">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitQSPIPins">
<feature name="enabled" evaluation="equal" configuration="core0">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitQSPIPins">
<feature name="enabled" evaluation="equal" configuration="core0">
<data>true</data>
</feature>
</dependency>
</dependencies>
<pins>
<pin peripheral="FLEXSPI" signal="FLEXSPI_A_SCLK" pin_num="24" pin_signal="GPIO_SD_B1_07"/>
<pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA0" pin_num="23" pin_signal="GPIO_SD_B1_08"/>
<pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA1" pin_num="21" pin_signal="GPIO_SD_B1_10"/>
<pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA2" pin_num="22" pin_signal="GPIO_SD_B1_09"/>
<pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA3" pin_num="25" pin_signal="GPIO_SD_B1_06"/>
<pin peripheral="FLEXSPI" signal="FLEXSPI_A_SS0_B" pin_num="19" pin_signal="GPIO_SD_B1_11"/>
</pins>
</function>
</functions_list>
</pins>
<clocks name="Clocks" version="11.0" enabled="true" update_project_code="true">
<generated_project_files>
<file path="board/clock_config.c" update_enabled="true"/>
<file path="board/clock_config.h" update_enabled="true"/>
</generated_project_files>
<clocks_profile>
<processor_version>13.0.2</processor_version>
</clocks_profile>
<clock_configurations>
<clock_configuration name="BOARD_BootClockRUN" id_prefix="" prefix_user_defined="false">
<description></description>
<options/>
<dependencies>
<dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtali" description="&apos;RTC_XTALI&apos; (Pins tool id: XTALOSC24M.rtc_xtali, Clocks tool id: XTALOSC24M.RTC_XTALI) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
<feature name="routed" evaluation="">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtali" description="&apos;RTC_XTALI&apos; (Pins tool id: XTALOSC24M.rtc_xtali, Clocks tool id: XTALOSC24M.RTC_XTALI) needs to have &apos;INPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
<feature name="direction" evaluation="">
<data>INPUT</data>
</feature>
</dependency>
<dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtalo" description="&apos;RTC_XTALO&apos; (Pins tool id: XTALOSC24M.rtc_xtalo, Clocks tool id: XTALOSC24M.RTC_XTALO) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
<feature name="routed" evaluation="">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtalo" description="&apos;RTC_XTALO&apos; (Pins tool id: XTALOSC24M.rtc_xtalo, Clocks tool id: XTALOSC24M.RTC_XTALO) needs to have &apos;OUTPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
<feature name="direction" evaluation="">
<data>OUTPUT</data>
</feature>
</dependency>
<dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtali" description="&apos;XTALI&apos; (Pins tool id: XTALOSC24M.xtali, Clocks tool id: XTALOSC24M.XTALI) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
<feature name="routed" evaluation="">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtali" description="&apos;XTALI&apos; (Pins tool id: XTALOSC24M.xtali, Clocks tool id: XTALOSC24M.XTALI) needs to have &apos;INPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
<feature name="direction" evaluation="">
<data>INPUT</data>
</feature>
</dependency>
<dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtalo" description="&apos;XTALO&apos; (Pins tool id: XTALOSC24M.xtalo, Clocks tool id: XTALOSC24M.XTALO) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
<feature name="routed" evaluation="">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtalo" description="&apos;XTALO&apos; (Pins tool id: XTALOSC24M.xtalo, Clocks tool id: XTALOSC24M.XTALO) needs to have &apos;OUTPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
<feature name="direction" evaluation="">
<data>OUTPUT</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN">
<feature name="enabled" evaluation="equal" configuration="core0">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Clocks initialization requires the IOMUXC Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN">
<feature name="enabled" evaluation="equal" configuration="core0">
<data>true</data>
</feature>
</dependency>
</dependencies>
<clock_sources>
<clock_source id="XTALOSC24M.RTC_OSC.outFreq" value="32.768 kHz" locked="false" enabled="true"/>
</clock_sources>
<clock_outputs>
<clock_output id="AHB_CLK_ROOT.outFreq" value="500 MHz" locked="false" accuracy=""/>
<clock_output id="CAN_CLK_ROOT.outFreq" value="40 MHz" locked="false" accuracy=""/>
<clock_output id="CKIL_SYNC_CLK_ROOT.outFreq" value="32.768 kHz" locked="false" accuracy=""/>
<clock_output id="CLK_1M.outFreq" value="1 MHz" locked="false" accuracy=""/>
<clock_output id="CLK_24M.outFreq" value="24 MHz" locked="false" accuracy=""/>
<clock_output id="ENET_500M_REF_CLK.outFreq" value="500 MHz" locked="false" accuracy=""/>
<clock_output id="FLEXIO1_CLK_ROOT.outFreq" value="30 MHz" locked="false" accuracy=""/>
<clock_output id="FLEXSPI_CLK_ROOT.outFreq" value="132 MHz" locked="false" accuracy=""/>
<clock_output id="GPT1_ipg_clk_highfreq.outFreq" value="62.5 MHz" locked="false" accuracy=""/>
<clock_output id="GPT2_ipg_clk_highfreq.outFreq" value="62.5 MHz" locked="false" accuracy=""/>
<clock_output id="IPG_CLK_ROOT.outFreq" value="125 MHz" locked="false" accuracy=""/>
<clock_output id="LPI2C_CLK_ROOT.outFreq" value="60 MHz" locked="false" accuracy=""/>
<clock_output id="LPSPI_CLK_ROOT.outFreq" value="105.6 MHz" locked="false" accuracy=""/>
<clock_output id="MQS_MCLK.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
<clock_output id="PERCLK_CLK_ROOT.outFreq" value="62.5 MHz" locked="false" accuracy=""/>
<clock_output id="SAI1_CLK_ROOT.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
<clock_output id="SAI1_MCLK1.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
<clock_output id="SAI1_MCLK2.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
<clock_output id="SAI1_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/>
<clock_output id="SAI2_CLK_ROOT.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
<clock_output id="SAI2_MCLK1.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
<clock_output id="SAI2_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/>
<clock_output id="SAI3_CLK_ROOT.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
<clock_output id="SAI3_MCLK1.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
<clock_output id="SAI3_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/>
<clock_output id="SEMC_CLK_ROOT.outFreq" value="62.5 MHz" locked="false" accuracy=""/>
<clock_output id="SPDIF0_CLK_ROOT.outFreq" value="30 MHz" locked="false" accuracy=""/>
<clock_output id="TRACE_CLK_ROOT.outFreq" value="132 MHz" locked="false" accuracy=""/>
<clock_output id="UART_CLK_ROOT.outFreq" value="80 MHz" locked="false" accuracy=""/>
<clock_output id="USBPHY1_CLK.outFreq" value="480 MHz" locked="false" accuracy=""/>
<clock_output id="USDHC1_CLK_ROOT.outFreq" value="176 MHz" locked="false" accuracy=""/>
<clock_output id="USDHC2_CLK_ROOT.outFreq" value="176 MHz" locked="false" accuracy=""/>
</clock_outputs>
<clock_settings>
<setting id="CCM.AHB_PODF.scale" value="1" locked="true"/>
<setting id="CCM.ARM_PODF.scale" value="1" locked="true"/>
<setting id="CCM.FLEXSPI_PODF.scale" value="4" locked="true"/>
<setting id="CCM.FLEXSPI_SEL.sel" value="CCM_ANALOG.PLL2_PFD2_CLK" locked="false"/>
<setting id="CCM.IPG_PODF.scale" value="4" locked="false"/>
<setting id="CCM.LPSPI_PODF.scale" value="5" locked="true"/>
<setting id="CCM.PERCLK_PODF.scale" value="2" locked="true"/>
<setting id="CCM.PRE_PERIPH_CLK_SEL.sel" value="CCM.ARM_PODF" locked="false"/>
<setting id="CCM.SEMC_PODF.scale" value="8" locked="false"/>
<setting id="CCM.TRACE_CLK_SEL.sel" value="CCM_ANALOG.PLL2_MAIN_CLK" locked="false"/>
<setting id="CCM.TRACE_PODF.scale" value="4" locked="true"/>
<setting id="CCM.USDHC1_PODF.scale" value="3" locked="true"/>
<setting id="CCM.USDHC2_PODF.scale" value="3" locked="true"/>
<setting id="CCM_ANALOG.PLL2.denom" value="1" locked="true"/>
<setting id="CCM_ANALOG.PLL2.num" value="0" locked="true"/>
<setting id="CCM_ANALOG.PLL2_BYPASS.sel" value="CCM_ANALOG.PLL2_OUT_CLK" locked="false"/>
<setting id="CCM_ANALOG.PLL2_PFD0_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD0" locked="false"/>
<setting id="CCM_ANALOG.PLL2_PFD1_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD1" locked="false"/>
<setting id="CCM_ANALOG.PLL2_PFD2_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD2" locked="false"/>
<setting id="CCM_ANALOG.PLL2_PFD2_DIV.scale" value="18" locked="true"/>
<setting id="CCM_ANALOG.PLL2_PFD2_MUL.scale" value="18" locked="true"/>
<setting id="CCM_ANALOG.PLL2_PFD3_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD3" locked="false"/>
<setting id="CCM_ANALOG.PLL2_PFD3_DIV.scale" value="18" locked="true"/>
<setting id="CCM_ANALOG.PLL2_PFD3_MUL.scale" value="18" locked="true"/>
<setting id="CCM_ANALOG.PLL3_BYPASS.sel" value="CCM_ANALOG.PLL3" locked="false"/>
<setting id="CCM_ANALOG.PLL3_PFD0_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD0" locked="false"/>
<setting id="CCM_ANALOG.PLL3_PFD0_DIV.scale" value="22" locked="true"/>
<setting id="CCM_ANALOG.PLL3_PFD0_MUL.scale" value="18" locked="true"/>
<setting id="CCM_ANALOG.PLL3_PFD1_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD1" locked="false"/>
<setting id="CCM_ANALOG.PLL3_PFD2_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD2" locked="false"/>
<setting id="CCM_ANALOG.PLL3_PFD3_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD3" locked="false"/>
<setting id="CCM_ANALOG.PLL3_PFD3_DIV.scale" value="18" locked="true"/>
<setting id="CCM_ANALOG.PLL3_PFD3_MUL.scale" value="18" locked="true"/>
<setting id="CCM_ANALOG.PLL4.denom" value="50" locked="false"/>
<setting id="CCM_ANALOG.PLL4.div" value="47" locked="false"/>
<setting id="CCM_ANALOG.PLL6_BYPASS.sel" value="CCM_ANALOG.PLL6" locked="false"/>
<setting id="CCM_ANALOG_PLL_ENET_ENABLE_CFG" value="Disabled" locked="false"/>
<setting id="CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_CFG" value="Disabled" locked="false"/>
<setting id="CCM_ANALOG_PLL_USB1_EN_USB_CLKS_CFG" value="Enabled" locked="false"/>
<setting id="CCM_ANALOG_PLL_USB1_EN_USB_CLKS_OUT_CFG" value="Enabled" locked="false"/>
<setting id="CCM_ANALOG_PLL_USB1_POWER_CFG" value="Yes" locked="false"/>
</clock_settings>
<called_from_default_init>true</called_from_default_init>
</clock_configuration>
</clock_configurations>
</clocks>
<dcdx name="DCDx" version="3.0" enabled="true" update_project_code="true">
<generated_project_files>
<file path="board/dcd.c" update_enabled="true"/>
<file path="board/dcd.h" update_enabled="true"/>
</generated_project_files>
<dcdx_profile>
<processor_version>13.0.2</processor_version>
<output_format>c_array</output_format>
</dcdx_profile>
<dcdx_configurations>
<dcdx_configuration name="Device_configuration">
<description></description>
<options/>
<command_groups/>
</dcdx_configuration>
</dcdx_configurations>
</dcdx>
<periphs name="Peripherals" version="12.0" enabled="true" update_project_code="true">
<generated_project_files>
<file path="board/peripherals.c" update_enabled="true"/>
<file path="board/peripherals.h" update_enabled="true"/>
</generated_project_files>
<peripherals_profile>
<processor_version>13.0.2</processor_version>
</peripherals_profile>
<functional_groups>
<functional_group name="BOARD_InitPeripherals" uuid="6d394465-bc9b-47f2-9a1f-3ca61f76d27b" called_from_default_init="true" id_prefix="" core="core0">
<description></description>
<options/>
<dependencies/>
<instances>
<instance name="CAN" uuid="d0b30ebd-b05e-42b2-8e94-40b1625c2dba" type="flexcan" type_id="flexcan_10d80efac19b25dcd240244aae88dca0" mode="interrupts" peripheral="CAN1" enabled="false" comment="" custom_name_enabled="true" editing_lock="false">
<config_set name="interruptsCfg">
<setting name="messageBufferIrqs" value="0"/>
<setting name="messageBufferIrqs2" value="0"/>
<set name="interruptsEnable">
<selected/>
</set>
<setting name="enable_irq" value="false"/>
<struct name="interrupt_shared">
<setting name="IRQn" value="CAN1_IRQn"/>
<setting name="enable_interrrupt" value="enabled"/>
<setting name="enable_priority" value="false"/>
<setting name="priority" value="0"/>
<setting name="enable_custom_name" value="false"/>
</struct>
</config_set>
<config_set name="fsl_flexcan" quick_selection="default">
<struct name="can_config">
<setting name="clockSource" value="kFLEXCAN_ClkSrcOsc"/>
<setting name="clockSourceFreq" value="ClocksTool_DefaultInit"/>
<setting name="wakeupSrc" value="kFLEXCAN_WakeupSrcUnfiltered"/>
<setting name="baudRate" value="1000000"/>
<setting name="maxMbNum" value="16"/>
<setting name="enableLoopBack" value="false"/>
<setting name="enableTimerSync" value="true"/>
<setting name="enableSelfWakeup" value="false"/>
<setting name="enableIndividMask" value="false"/>
<struct name="timingConfig">
<setting name="propSeg" value="2"/>
<setting name="phaseSeg1" value="4"/>
<setting name="phaseSeg2" value="3"/>
<setting name="rJumpwidth" value="2"/>
<struct name="bitTime"/>
</struct>
</struct>
<setting name="enableRxFIFO" value="false"/>
<struct name="rxFIFO">
<setting name="idFilterTable" value=""/>
<setting name="idFilterNum" value="num0"/>
<setting name="idFilterType" value="kFLEXCAN_RxFifoFilterTypeA"/>
<setting name="priority" value="kFLEXCAN_RxFifoPrioLow"/>
</struct>
<array name="channels">
<struct name="0">
<setting name="mbID" value="0"/>
<setting name="mbType" value="mbRx"/>
<struct name="rxMb">
<setting name="id" value="0"/>
<setting name="format" value="kFLEXCAN_FrameFormatStandard"/>
<setting name="type" value="kFLEXCAN_FrameTypeData"/>
</struct>
</struct>
<struct name="1">
<setting name="mbID" value="1"/>
<setting name="mbType" value="mbTx"/>
<struct name="rxMb">
<setting name="id" value="0"/>
<setting name="format" value="kFLEXCAN_FrameFormatStandard"/>
<setting name="type" value="kFLEXCAN_FrameTypeData"/>
</struct>
</struct>
</array>
</config_set>
</instance>
<instance name="DEBUG_UART" uuid="27a94726-61ef-42ac-b517-d1eda3853dfe" type="lpuart" type_id="lpuart_bf01db7d964092f3cf860852cba17f7e" mode="polling" peripheral="LPUART1" enabled="false" comment="" custom_name_enabled="true" editing_lock="false">
<config_set name="lpuartConfig_t">
<struct name="lpuartConfig">
<setting name="clockSource" value="LpuartClock"/>
<setting name="lpuartSrcClkFreq" value="BOARD_BootClockRUN"/>
<setting name="baudRate_Bps" value="115200"/>
<setting name="parityMode" value="kLPUART_ParityDisabled"/>
<setting name="dataBitsCount" value="kLPUART_EightDataBits"/>
<setting name="isMsb" value="false"/>
<setting name="stopBitCount" value="kLPUART_OneStopBit"/>
<setting name="enableMatchAddress1" value="false"/>
<setting name="matchAddress1" value="0"/>
<setting name="enableMatchAddress2" value="false"/>
<setting name="matchAddress2" value="0"/>
<setting name="txFifoWatermark" value="0"/>
<setting name="rxFifoWatermark" value="1"/>
<setting name="enableRxRTS" value="false"/>
<setting name="enableTxCTS" value="false"/>
<setting name="txCtsSource" value="kLPUART_CtsSourcePin"/>
<setting name="txCtsConfig" value="kLPUART_CtsSampleAtStart"/>
<setting name="rxIdleType" value="kLPUART_IdleTypeStartBit"/>
<setting name="rxIdleConfig" value="kLPUART_IdleCharacter1"/>
<setting name="enableTx" value="true"/>
<setting name="enableRx" value="true"/>
</struct>
</config_set>
</instance>
<instance name="NVIC" uuid="e2a4cccd-cb23-4714-8c90-022fcf6146e8" type="nvic" type_id="nvic_57b5eef3774cc60acaede6f5b8bddc67" mode="general" peripheral="NVIC" enabled="true" comment="" custom_name_enabled="false" editing_lock="false">
<config_set name="nvic">
<array name="interrupt_table"/>
<array name="interrupts"/>
</config_set>
</instance>
</instances>
</functional_group>
</functional_groups>
<components>
<component name="system" uuid="bd191d83-2cb2-40ed-a718-47b39d772006" type_id="system">
<config_set_global name="global_system_definitions">
<setting name="user_definitions" value=""/>
<setting name="user_includes" value=""/>
</config_set_global>
</component>
<component name="msg" uuid="d097438f-179b-43e0-b37c-aee31212cebd" type_id="msg">
<config_set_global name="global_messages"/>
</component>
<component name="gpio_adapter_common" uuid="d84400f7-fd84-4466-908a-04abca190ef6" type_id="gpio_adapter_common_57579b9ac814fe26bf95df0a384c36b6">
<config_set_global name="global_gpio_adapter_common" quick_selection="default"/>
</component>
<component name="generic_uart" uuid="4f0123a9-0338-4076-b275-b49951642704" type_id="generic_uart_8cae00565451cf2346eb1b8c624e73a6">
<config_set_global name="global_uart"/>
</component>
<component name="generic_can" uuid="18150193-6d2b-469f-88e5-4908669bf3e5" type_id="generic_can_1bfdd78b1af214566c1f23cf6a582d80">
<config_set_global name="global_can"/>
</component>
<component name="uart_cmsis_common" uuid="602159e8-d65b-45d3-b63b-cd33be549134" type_id="uart_cmsis_common_9cb8e302497aa696fdbb5a4fd622c2a8">
<config_set_global name="global_USART_CMSIS_common" quick_selection="default"/>
</component>
<component name="generic_enet" uuid="eb963b89-5367-4d86-8885-82b4b8cff735" type_id="generic_enet_74db5c914f0ddbe47d86af40cb77a619">
<config_set_global name="global_enet"/>
</component>
</components>
</periphs>
<tee name="TEE" version="4.0" enabled="false" update_project_code="true">
<generated_project_files/>
<tee_profile>
<processor_version>0.0.0</processor_version>
</tee_profile>
</tee>
<common name="common" version="1.0" enabled="true" update_project_code="true">
<core name="core0" role="primary" project_name="Project"/>
</common>
</tools>
</configuration>

16
managed_components/espressif__tinyusb/hw/bsp/imxrt/boards/mimxrt1024_evk/board.cmake Normal file
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set(MCU_VARIANT MIMXRT1024)
set(JLINK_DEVICE MIMXRT1024xxx5A)
set(PYOCD_TARGET mimxrt1024)
set(NXPLINK_DEVICE MIMXRT1024xxxxx:MIMXRT1024-EVK)
function(update_board TARGET)
target_sources(${TARGET} PUBLIC
${CMAKE_CURRENT_FUNCTION_LIST_DIR}/evkmimxrt1024_flexspi_nor_config.c
)
target_compile_definitions(${TARGET} PUBLIC
CPU_MIMXRT1024DAG5A
CFG_EXAMPLE_VIDEO_READONLY
#-Wno-error=array-bounds
)
endfunction()

56
managed_components/espressif__tinyusb/hw/bsp/imxrt/boards/mimxrt1024_evk/board.h Normal file
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/*
* The MIT License (MIT)
*
* Copyright (c) 2019, Ha Thach (tinyusb.org)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* This file is part of the TinyUSB stack.
*/
/* metadata:
name: i.MX RT1024 Evaluation Kit
url: https://www.nxp.com/design/design-center/development-boards-and-designs/i-mx-evaluation-and-development-boards/i-mx-rt1024-evaluation-kit:MIMXRT1024-EVK
*/
#ifndef BOARD_MIMXRT1024_EVK_H_
#define BOARD_MIMXRT1024_EVK_H_
// required since iMXRT MCUX-SDK include this file for board size
// RT1020-EVK #define BOARD_FLASH_SIZE (0x800000U)
#define BOARD_FLASH_SIZE (0x400000U) // builtin flash of RT1024
// LED: IOMUXC_GPIO_AD_B1_08_GPIO1_IO24
#define LED_PORT BOARD_INITPINS_USER_LED_GPIO
#define LED_PIN BOARD_INITPINS_USER_LED_PIN
#define LED_STATE_ON 1
// SW8 button: IOMUXC_SNVS_WAKEUP_GPIO5_IO00
#define BUTTON_PORT BOARD_INITPINS_USER_BUTTON_GPIO
#define BUTTON_PIN BOARD_INITPINS_USER_BUTTON_PIN
#define BUTTON_STATE_ACTIVE 0
// UART: IOMUXC_GPIO_AD_B0_07_LPUART1_RX, IOMUXC_GPIO_AD_B0_06_LPUART1_TX
#define UART_PORT LPUART1
#define UART_CLK_ROOT BOARD_BOOTCLOCKRUN_UART_CLK_ROOT
static inline void BOARD_ConfigMPU(void) {
}
#endif

14
managed_components/espressif__tinyusb/hw/bsp/imxrt/boards/mimxrt1024_evk/board.mk Normal file
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CFLAGS += -DCPU_MIMXRT1024DAG5A
MCU_VARIANT = MIMXRT1024
# warnings caused by mcu driver
CFLAGS += -Wno-error=array-bounds
# For flash-jlink target
JLINK_DEVICE = MIMXRT1024xxx5A
# For flash-pyocd target
PYOCD_TARGET = mimxrt1024
# flash using pyocd
flash: flash-pyocd

421
managed_components/espressif__tinyusb/hw/bsp/imxrt/boards/mimxrt1024_evk/board/clock_config.c Normal file
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/*
* How to setup clock using clock driver functions:
*
* 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock.
*
* 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock.
*
* 3. Call CLOCK_SetMux() to configure corresponding clock source for target clock out.
*
* 4. Call CLOCK_SetDiv() to configure corresponding clock divider for target clock out.
*
* 5. Call CLOCK_SetXtalFreq() to set XTAL frequency based on board settings.
*
*/
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!GlobalInfo
product: Clocks v11.0
processor: MIMXRT1024xxxxx
package_id: MIMXRT1024DAG5A
mcu_data: ksdk2_0
processor_version: 13.0.2
board: MIMXRT1024-EVK
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
#include "clock_config.h"
#include "fsl_iomuxc.h"
/*******************************************************************************
* Definitions
******************************************************************************/
/*******************************************************************************
* Variables
******************************************************************************/
/*******************************************************************************
************************ BOARD_InitBootClocks function ************************
******************************************************************************/
void BOARD_InitBootClocks(void)
{
BOARD_BootClockRUN();
}
/*******************************************************************************
********************** Configuration BOARD_BootClockRUN ***********************
******************************************************************************/
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!Configuration
name: BOARD_BootClockRUN
called_from_default_init: true
outputs:
- {id: AHB_CLK_ROOT.outFreq, value: 500 MHz}
- {id: CAN_CLK_ROOT.outFreq, value: 40 MHz}
- {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz}
- {id: CLK_1M.outFreq, value: 1 MHz}
- {id: CLK_24M.outFreq, value: 24 MHz}
- {id: ENET_500M_REF_CLK.outFreq, value: 500 MHz}
- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz}
- {id: FLEXSPI_CLK_ROOT.outFreq, value: 132 MHz}
- {id: GPT1_ipg_clk_highfreq.outFreq, value: 62.5 MHz}
- {id: GPT2_ipg_clk_highfreq.outFreq, value: 62.5 MHz}
- {id: IPG_CLK_ROOT.outFreq, value: 125 MHz}
- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz}
- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz}
- {id: MQS_MCLK.outFreq, value: 1080/17 MHz}
- {id: PERCLK_CLK_ROOT.outFreq, value: 62.5 MHz}
- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz}
- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz}
- {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz}
- {id: SAI1_MCLK3.outFreq, value: 30 MHz}
- {id: SAI2_CLK_ROOT.outFreq, value: 1080/17 MHz}
- {id: SAI2_MCLK1.outFreq, value: 1080/17 MHz}
- {id: SAI2_MCLK3.outFreq, value: 30 MHz}
- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz}
- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz}
- {id: SAI3_MCLK3.outFreq, value: 30 MHz}
- {id: SEMC_CLK_ROOT.outFreq, value: 62.5 MHz}
- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz}
- {id: TRACE_CLK_ROOT.outFreq, value: 132 MHz}
- {id: UART_CLK_ROOT.outFreq, value: 80 MHz}
- {id: USBPHY1_CLK.outFreq, value: 480 MHz}
- {id: USDHC1_CLK_ROOT.outFreq, value: 176 MHz}
- {id: USDHC2_CLK_ROOT.outFreq, value: 176 MHz}
settings:
- {id: CCM.AHB_PODF.scale, value: '1', locked: true}
- {id: CCM.ARM_PODF.scale, value: '1', locked: true}
- {id: CCM.FLEXSPI_PODF.scale, value: '4', locked: true}
- {id: CCM.FLEXSPI_SEL.sel, value: CCM_ANALOG.PLL2_PFD2_CLK}
- {id: CCM.IPG_PODF.scale, value: '4'}
- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true}
- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true}
- {id: CCM.PRE_PERIPH_CLK_SEL.sel, value: CCM.ARM_PODF}
- {id: CCM.SEMC_PODF.scale, value: '8'}
- {id: CCM.TRACE_CLK_SEL.sel, value: CCM_ANALOG.PLL2_MAIN_CLK}
- {id: CCM.TRACE_PODF.scale, value: '4', locked: true}
- {id: CCM.USDHC1_PODF.scale, value: '3', locked: true}
- {id: CCM.USDHC2_PODF.scale, value: '3', locked: true}
- {id: CCM_ANALOG.PLL2.denom, value: '1', locked: true}
- {id: CCM_ANALOG.PLL2.num, value: '0', locked: true}
- {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK}
- {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0}
- {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1}
- {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2}
- {id: CCM_ANALOG.PLL2_PFD2_DIV.scale, value: '18', locked: true}
- {id: CCM_ANALOG.PLL2_PFD2_MUL.scale, value: '18', locked: true}
- {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3}
- {id: CCM_ANALOG.PLL2_PFD3_DIV.scale, value: '18', locked: true}
- {id: CCM_ANALOG.PLL2_PFD3_MUL.scale, value: '18', locked: true}
- {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3}
- {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0}
- {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '22', locked: true}
- {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true}
- {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1}
- {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2}
- {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3}
- {id: CCM_ANALOG.PLL3_PFD3_DIV.scale, value: '18', locked: true}
- {id: CCM_ANALOG.PLL3_PFD3_MUL.scale, value: '18', locked: true}
- {id: CCM_ANALOG.PLL4.denom, value: '50'}
- {id: CCM_ANALOG.PLL4.div, value: '47'}
- {id: CCM_ANALOG.PLL6_BYPASS.sel, value: CCM_ANALOG.PLL6}
- {id: CCM_ANALOG_PLL_ENET_ENABLE_CFG, value: Disabled}
- {id: CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_CFG, value: Disabled}
- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_CFG, value: Enabled}
- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_OUT_CFG, value: Enabled}
- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'}
sources:
- {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/*******************************************************************************
* Variables for BOARD_BootClockRUN configuration
******************************************************************************/
const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN =
{
.loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */
.numerator = 0, /* 30 bit numerator of fractional loop divider */
.denominator = 1, /* 30 bit denominator of fractional loop divider */
.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
};
const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN =
{
.loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */
.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
};
const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN =
{
.enableClkOutput = false, /* Disable the PLL providing the ENET 125MHz reference clock */
.enableClkOutput500M = true, /* Enable the PLL providing the ENET 500MHz reference clock */
.enableClkOutput25M = false, /* Disable the PLL providing the ENET 25MHz reference clock */
.loopDivider = 1, /* Set frequency of ethernet reference clock to 50 MHz */
.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
};
/*******************************************************************************
* Code for BOARD_BootClockRUN configuration
******************************************************************************/
void BOARD_BootClockRUN(void)
{
/* Init RTC OSC clock frequency. */
CLOCK_SetRtcXtalFreq(32768U);
/* Enable 1MHz clock output. */
XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK;
/* Use free 1MHz clock output. */
XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK;
/* Set XTAL 24MHz clock frequency. */
CLOCK_SetXtalFreq(24000000U);
/* Enable XTAL 24MHz clock source. */
CLOCK_InitExternalClk(0);
/* Enable internal RC. */
CLOCK_InitRcOsc24M();
/* Switch clock source to external OSC. */
CLOCK_SwitchOsc(kCLOCK_XtalOsc);
/* Set Oscillator ready counter value. */
CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127);
/* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */
CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */
CLOCK_SetMux(kCLOCK_PeriphMux, 1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */
/* Setting the VDD_SOC to 1.25V. It is necessary to config AHB to 500Mhz. */
DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x12);
/* Waiting for DCDC_STS_DC_OK bit is asserted */
while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0))
{
}
/* Set AHB_PODF. */
CLOCK_SetDiv(kCLOCK_AhbDiv, 0);
/* Disable IPG clock gate. */
CLOCK_DisableClock(kCLOCK_Adc1);
CLOCK_DisableClock(kCLOCK_Adc2);
CLOCK_DisableClock(kCLOCK_Xbar1);
CLOCK_DisableClock(kCLOCK_Xbar2);
/* Set IPG_PODF. */
CLOCK_SetDiv(kCLOCK_IpgDiv, 3);
/* Set ARM_PODF. */
CLOCK_SetDiv(kCLOCK_ArmDiv, 0);
/* Set PERIPH_CLK2_PODF. */
CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0);
/* Disable PERCLK clock gate. */
CLOCK_DisableClock(kCLOCK_Gpt1);
CLOCK_DisableClock(kCLOCK_Gpt1S);
CLOCK_DisableClock(kCLOCK_Gpt2);
CLOCK_DisableClock(kCLOCK_Gpt2S);
CLOCK_DisableClock(kCLOCK_Pit);
/* Set PERCLK_PODF. */
CLOCK_SetDiv(kCLOCK_PerclkDiv, 1);
/* Disable USDHC1 clock gate. */
CLOCK_DisableClock(kCLOCK_Usdhc1);
/* Set USDHC1_PODF. */
CLOCK_SetDiv(kCLOCK_Usdhc1Div, 2);
/* Set Usdhc1 clock source. */
CLOCK_SetMux(kCLOCK_Usdhc1Mux, 0);
/* Disable USDHC2 clock gate. */
CLOCK_DisableClock(kCLOCK_Usdhc2);
/* Set USDHC2_PODF. */
CLOCK_SetDiv(kCLOCK_Usdhc2Div, 2);
/* Set Usdhc2 clock source. */
CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0);
/* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
* With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
* Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
#ifndef SKIP_SYSCLK_INIT
/* Disable Semc clock gate. */
CLOCK_DisableClock(kCLOCK_Semc);
/* Set SEMC_PODF. */
CLOCK_SetDiv(kCLOCK_SemcDiv, 7);
/* Set Semc alt clock source. */
CLOCK_SetMux(kCLOCK_SemcAltMux, 0);
/* Set Semc clock source. */
CLOCK_SetMux(kCLOCK_SemcMux, 0);
#endif
/* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
* With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
* Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
/* Disable Flexspi clock gate. */
CLOCK_DisableClock(kCLOCK_FlexSpi);
/* Set FLEXSPI_PODF. */
CLOCK_SetDiv(kCLOCK_FlexspiDiv, 3);
/* Set Flexspi clock source. */
CLOCK_SetMux(kCLOCK_FlexspiMux, 2);
#endif
/* Disable LPSPI clock gate. */
CLOCK_DisableClock(kCLOCK_Lpspi1);
CLOCK_DisableClock(kCLOCK_Lpspi2);
CLOCK_DisableClock(kCLOCK_Lpspi3);
CLOCK_DisableClock(kCLOCK_Lpspi4);
/* Set LPSPI_PODF. */
CLOCK_SetDiv(kCLOCK_LpspiDiv, 4);
/* Set Lpspi clock source. */
CLOCK_SetMux(kCLOCK_LpspiMux, 2);
/* Disable TRACE clock gate. */
CLOCK_DisableClock(kCLOCK_Trace);
/* Set TRACE_PODF. */
CLOCK_SetDiv(kCLOCK_TraceDiv, 3);
/* Set Trace clock source. */
CLOCK_SetMux(kCLOCK_TraceMux, 0);
/* Disable SAI1 clock gate. */
CLOCK_DisableClock(kCLOCK_Sai1);
/* Set SAI1_CLK_PRED. */
CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3);
/* Set SAI1_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_Sai1Div, 1);
/* Set Sai1 clock source. */
CLOCK_SetMux(kCLOCK_Sai1Mux, 0);
/* Disable SAI2 clock gate. */
CLOCK_DisableClock(kCLOCK_Sai2);
/* Set SAI2_CLK_PRED. */
CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3);
/* Set SAI2_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_Sai2Div, 1);
/* Set Sai2 clock source. */
CLOCK_SetMux(kCLOCK_Sai2Mux, 0);
/* Disable SAI3 clock gate. */
CLOCK_DisableClock(kCLOCK_Sai3);
/* Set SAI3_CLK_PRED. */
CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3);
/* Set SAI3_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_Sai3Div, 1);
/* Set Sai3 clock source. */
CLOCK_SetMux(kCLOCK_Sai3Mux, 0);
/* Disable Lpi2c clock gate. */
CLOCK_DisableClock(kCLOCK_Lpi2c1);
CLOCK_DisableClock(kCLOCK_Lpi2c2);
CLOCK_DisableClock(kCLOCK_Lpi2c3);
/* Set LPI2C_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0);
/* Set Lpi2c clock source. */
CLOCK_SetMux(kCLOCK_Lpi2cMux, 0);
/* Disable CAN clock gate. */
CLOCK_DisableClock(kCLOCK_Can1);
CLOCK_DisableClock(kCLOCK_Can2);
CLOCK_DisableClock(kCLOCK_Can1S);
CLOCK_DisableClock(kCLOCK_Can2S);
/* Set CAN_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_CanDiv, 1);
/* Set Can clock source. */
CLOCK_SetMux(kCLOCK_CanMux, 2);
/* Disable UART clock gate. */
CLOCK_DisableClock(kCLOCK_Lpuart1);
CLOCK_DisableClock(kCLOCK_Lpuart2);
CLOCK_DisableClock(kCLOCK_Lpuart3);
CLOCK_DisableClock(kCLOCK_Lpuart4);
CLOCK_DisableClock(kCLOCK_Lpuart5);
CLOCK_DisableClock(kCLOCK_Lpuart6);
CLOCK_DisableClock(kCLOCK_Lpuart7);
CLOCK_DisableClock(kCLOCK_Lpuart8);
/* Set UART_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_UartDiv, 0);
/* Set Uart clock source. */
CLOCK_SetMux(kCLOCK_UartMux, 0);
/* Disable SPDIF clock gate. */
CLOCK_DisableClock(kCLOCK_Spdif);
/* Set SPDIF0_CLK_PRED. */
CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1);
/* Set SPDIF0_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_Spdif0Div, 7);
/* Set Spdif clock source. */
CLOCK_SetMux(kCLOCK_SpdifMux, 3);
/* Disable Flexio1 clock gate. */
CLOCK_DisableClock(kCLOCK_Flexio1);
/* Set FLEXIO1_CLK_PRED. */
CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1);
/* Set FLEXIO1_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_Flexio1Div, 7);
/* Set Flexio1 clock source. */
CLOCK_SetMux(kCLOCK_Flexio1Mux, 3);
/* Set Pll3 sw clock source. */
CLOCK_SetMux(kCLOCK_Pll3SwMux, 0);
/* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
* With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
* Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
#ifndef SKIP_SYSCLK_INIT
#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1)
#warning "SKIP_SYSCLK_INIT should be defined to keep system pll (selected to be SEMC source clock in SDK projects) unchanged."
#endif
/* Init System PLL. */
CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN);
/* Init System pfd0. */
CLOCK_InitSysPfd(kCLOCK_Pfd0, 27);
/* Init System pfd1. */
CLOCK_InitSysPfd(kCLOCK_Pfd1, 16);
/* Init System pfd2. */
CLOCK_InitSysPfd(kCLOCK_Pfd2, 18);
/* Init System pfd3. */
CLOCK_InitSysPfd(kCLOCK_Pfd3, 18);
#endif
/* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
* With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
* Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
/* Init Usb1 PLL. */
CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN);
/* Init Usb1 pfd0. */
CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 22);
/* Init Usb1 pfd1. */
CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16);
/* Init Usb1 pfd2. */
CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17);
/* Init Usb1 pfd3. */
CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 18);
#endif
/* DeInit Audio PLL. */
CLOCK_DeinitAudioPll();
/* Bypass Audio PLL. */
CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1);
/* Set divider for Audio PLL. */
CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK;
CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK;
/* Enable Audio PLL output. */
CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK;
/* Init Enet PLL. */
CLOCK_InitEnetPll(&enetPllConfig_BOARD_BootClockRUN);
/* Set preperiph clock source. */
CLOCK_SetMux(kCLOCK_PrePeriphMux, 3);
/* Set periph clock source. */
CLOCK_SetMux(kCLOCK_PeriphMux, 0);
/* Set periph clock2 clock source. */
CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
/* Set per clock source. */
CLOCK_SetMux(kCLOCK_PerclkMux, 0);
/* Set clock out1 divider. */
CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0);
/* Set clock out1 source. */
CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1);
/* Set clock out2 divider. */
CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0);
/* Set clock out2 source. */
CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(3);
/* Set clock out1 drives clock out1. */
CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK;
/* Disable clock out1. */
CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK;
/* Disable clock out2. */
CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK;
/* Set SAI1 MCLK1 clock source. */
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0);
/* Set SAI1 MCLK2 clock source. */
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0);
/* Set SAI1 MCLK3 clock source. */
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0);
/* Set SAI2 MCLK3 clock source. */
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0);
/* Set SAI3 MCLK3 clock source. */
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
/* Set MQS configuration. */
IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0);
/* Set ENET Ref clock source. */
#if defined(IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK)
IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK;
#elif defined(IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK)
/* Backward compatibility for original bitfield name */
IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK;
#else
#error "Neither IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK nor IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK is defined."
#endif /* defined(IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK) */
/* Set GPT1 High frequency reference clock source. */
IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK;
/* Set GPT2 High frequency reference clock source. */
IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK;
/* Set SystemCoreClock variable. */
SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
}

108
managed_components/espressif__tinyusb/hw/bsp/imxrt/boards/mimxrt1024_evk/board/clock_config.h Normal file
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#ifndef _CLOCK_CONFIG_H_
#define _CLOCK_CONFIG_H_
#include "fsl_common.h"
/*******************************************************************************
* Definitions
******************************************************************************/
#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */
#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */
/*******************************************************************************
************************ BOARD_InitBootClocks function ************************
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/
/*!
* @brief This function executes default configuration of clocks.
*
*/
void BOARD_InitBootClocks(void);
#if defined(__cplusplus)
}
#endif /* __cplusplus*/
/*******************************************************************************
********************** Configuration BOARD_BootClockRUN ***********************
******************************************************************************/
/*******************************************************************************
* Definitions for BOARD_BootClockRUN configuration
******************************************************************************/
#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 500000000U /*!< Core clock frequency: 500000000Hz */
/* Clock outputs (values are in Hz): */
#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT 500000000UL
#define BOARD_BOOTCLOCKRUN_CAN_CLK_ROOT 40000000UL
#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL
#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL
#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL
#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL
#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL
#define BOARD_BOOTCLOCKRUN_ENET_125M_CLK 0UL
#define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK 0UL
#define BOARD_BOOTCLOCKRUN_ENET_500M_REF_CLK 500000000UL
#define BOARD_BOOTCLOCKRUN_ENET_REF_CLK 0UL
#define BOARD_BOOTCLOCKRUN_ENET_TX_CLK 0UL
#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL
#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 132000000UL
#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 62500000UL
#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 62500000UL
#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 125000000UL
#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL
#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL
#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL
#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 62500000UL
#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL
#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 63529411UL
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 63529411UL
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 30000000UL
#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL
#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 62500000UL
#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL
#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL
#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 132000000UL
#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL
#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK 480000000UL
#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 176000000UL
#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 176000000UL
/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration.
*/
extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN;
/*! @brief Sys PLL for BOARD_BootClockRUN configuration.
*/
extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN;
/*! @brief Enet PLL set for BOARD_BootClockRUN configuration.
*/
extern const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN;
/*******************************************************************************
* API for BOARD_BootClockRUN configuration
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/
/*!
* @brief This function executes configuration of clocks.
*
*/
void BOARD_BootClockRUN(void);
#if defined(__cplusplus)
}
#endif /* __cplusplus*/
#endif /* _CLOCK_CONFIG_H_ */

490
managed_components/espressif__tinyusb/hw/bsp/imxrt/boards/mimxrt1024_evk/board/pin_mux.c Normal file
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/***********************************************************************************************************************
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
**********************************************************************************************************************/
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!GlobalInfo
product: Pins v13.1
processor: MIMXRT1024xxxxx
package_id: MIMXRT1024DAG5A
mcu_data: ksdk2_0
processor_version: 13.0.2
board: MIMXRT1024-EVK
pin_labels:
- {pin_num: '52', pin_signal: WAKEUP, label: USER_BUTTON, identifier: USER_BUTTON}
- {pin_num: '82', pin_signal: GPIO_AD_B1_08, label: 'UART_TX/USER_LED/J17[4]', identifier: USER_LED}
power_domains: {NVCC_GPIO: '3.3'}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
#include "fsl_common.h"
#include "fsl_iomuxc.h"
#include "fsl_gpio.h"
#include "pin_mux.h"
/* FUNCTION ************************************************************************************************************
*
* Function Name : BOARD_InitBootPins
* Description : Calls initialization functions.
*
* END ****************************************************************************************************************/
void BOARD_InitBootPins(void) {
BOARD_InitPins();
BOARD_InitDEBUG_UARTPins();
/* GPIO_AD_B1_00~GPIO_AD_B1_05 can only be configured as flexspi function. Note that it can't be modified here */
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_00_FLEXSPI_A_DATA03,1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_01_FLEXSPI_A_SCLK,1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_02_FLEXSPI_A_DATA00,1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_03_FLEXSPI_A_DATA02,1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_04_FLEXSPI_A_DATA01,1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_05_FLEXSPI_A_SS0_B,1U);
}
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
BOARD_InitPins:
- options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'}
- pin_list:
- {pin_num: '52', peripheral: GPIO5, signal: 'gpio_io, 00', pin_signal: WAKEUP, direction: INPUT}
- {pin_num: '82', peripheral: GPIO1, signal: 'gpio_io, 24', pin_signal: GPIO_AD_B1_08, direction: OUTPUT}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
/* FUNCTION ************************************************************************************************************
*
* Function Name : BOARD_InitPins
* Description : Configures pin routing and optionally pin electrical features.
*
* END ****************************************************************************************************************/
void BOARD_InitPins(void) {
CLOCK_EnableClock(kCLOCK_Iomuxc); /* iomuxc clock (iomuxc_clk_enable): 0x03U */
CLOCK_EnableClock(kCLOCK_IomuxcSnvs); /* iomuxc_snvs clock (iomuxc_snvs_clk_enable): 0x03U */
/* GPIO configuration of USER_LED on GPIO_AD_B1_08 (pin 82) */
gpio_pin_config_t USER_LED_config = {
.direction = kGPIO_DigitalOutput,
.outputLogic = 0U,
.interruptMode = kGPIO_NoIntmode
};
/* Initialize GPIO functionality on GPIO_AD_B1_08 (pin 82) */
GPIO_PinInit(GPIO1, 24U, &USER_LED_config);
/* GPIO configuration of USER_BUTTON on WAKEUP (pin 52) */
gpio_pin_config_t USER_BUTTON_config = {
.direction = kGPIO_DigitalInput,
.outputLogic = 0U,
.interruptMode = kGPIO_NoIntmode
};
/* Initialize GPIO functionality on WAKEUP (pin 52) */
GPIO_PinInit(GPIO5, 0U, &USER_BUTTON_config);
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_B1_08_GPIO1_IO24, /* GPIO_AD_B1_08 is configured as GPIO1_IO24 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_SNVS_WAKEUP_GPIO5_IO00, /* WAKEUP is configured as GPIO5_IO00 */
0U); /* Software Input On Field: Input Path is determined by functionality */
}
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
BOARD_InitDEBUG_UARTPins:
- options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'}
- pin_list:
- {pin_num: '101', peripheral: LPUART1, signal: RX, pin_signal: GPIO_AD_B0_07}
- {pin_num: '105', peripheral: LPUART1, signal: TX, pin_signal: GPIO_AD_B0_06}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
/* FUNCTION ************************************************************************************************************
*
* Function Name : BOARD_InitDEBUG_UARTPins
* Description : Configures pin routing and optionally pin electrical features.
*
* END ****************************************************************************************************************/
void BOARD_InitDEBUG_UARTPins(void) {
CLOCK_EnableClock(kCLOCK_Iomuxc); /* iomuxc clock (iomuxc_clk_enable): 0x03U */
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_B0_06_LPUART1_TX, /* GPIO_AD_B0_06 is configured as LPUART1_TX */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_B0_07_LPUART1_RX, /* GPIO_AD_B0_07 is configured as LPUART1_RX */
0U); /* Software Input On Field: Input Path is determined by functionality */
}
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
BOARD_InitSDRAMPins:
- options: {coreID: core0, enableClock: 'true'}
- pin_list:
- {pin_num: '142', peripheral: SEMC, signal: 'ADDR, 00', pin_signal: GPIO_EMC_16}
- {pin_num: '141', peripheral: SEMC, signal: 'ADDR, 01', pin_signal: GPIO_EMC_17}
- {pin_num: '140', peripheral: SEMC, signal: 'ADDR, 02', pin_signal: GPIO_EMC_18}
- {pin_num: '139', peripheral: SEMC, signal: 'ADDR, 03', pin_signal: GPIO_EMC_19}
- {pin_num: '138', peripheral: SEMC, signal: 'ADDR, 04', pin_signal: GPIO_EMC_20}
- {pin_num: '136', peripheral: SEMC, signal: 'ADDR, 06', pin_signal: GPIO_EMC_22}
- {pin_num: '137', peripheral: SEMC, signal: 'ADDR, 05', pin_signal: GPIO_EMC_21}
- {pin_num: '133', peripheral: SEMC, signal: 'ADDR, 07', pin_signal: GPIO_EMC_23}
- {pin_num: '132', peripheral: SEMC, signal: 'ADDR, 08', pin_signal: GPIO_EMC_24}
- {pin_num: '131', peripheral: SEMC, signal: 'ADDR, 09', pin_signal: GPIO_EMC_25}
- {pin_num: '143', peripheral: SEMC, signal: 'ADDR, 10', pin_signal: GPIO_EMC_15}
- {pin_num: '130', peripheral: SEMC, signal: 'ADDR, 11', pin_signal: GPIO_EMC_26}
- {pin_num: '129', peripheral: SEMC, signal: 'ADDR, 12', pin_signal: GPIO_EMC_27}
- {pin_num: '2', peripheral: SEMC, signal: 'BA, 0', pin_signal: GPIO_EMC_13}
- {pin_num: '1', peripheral: SEMC, signal: 'BA, 1', pin_signal: GPIO_EMC_14}
- {pin_num: '7', peripheral: SEMC, signal: semc_cas, pin_signal: GPIO_EMC_10}
- {pin_num: '127', peripheral: SEMC, signal: semc_cke, pin_signal: GPIO_EMC_29}
- {pin_num: '126', peripheral: SEMC, signal: semc_clk, pin_signal: GPIO_EMC_30}
- {pin_num: '3', peripheral: SEMC, signal: 'CS, 0', pin_signal: GPIO_EMC_12}
- {pin_num: '8', peripheral: SEMC, signal: semc_we, pin_signal: GPIO_EMC_09}
- {pin_num: '4', peripheral: SEMC, signal: semc_ras, pin_signal: GPIO_EMC_11}
- {pin_num: '128', peripheral: SEMC, signal: semc_dqs, pin_signal: GPIO_EMC_28}
- {pin_num: '125', peripheral: SEMC, signal: 'DM, 1', pin_signal: GPIO_EMC_31}
- {pin_num: '9', peripheral: SEMC, signal: 'DM, 0', pin_signal: GPIO_EMC_08}
- {pin_num: '117', peripheral: SEMC, signal: 'DATA, 15', pin_signal: GPIO_EMC_39}
- {pin_num: '118', peripheral: SEMC, signal: 'DATA, 14', pin_signal: GPIO_EMC_38}
- {pin_num: '119', peripheral: SEMC, signal: 'DATA, 13', pin_signal: GPIO_EMC_37}
- {pin_num: '120', peripheral: SEMC, signal: 'DATA, 12', pin_signal: GPIO_EMC_36}
- {pin_num: '122', peripheral: SEMC, signal: 'DATA, 10', pin_signal: GPIO_EMC_34}
- {pin_num: '121', peripheral: SEMC, signal: 'DATA, 11', pin_signal: GPIO_EMC_35}
- {pin_num: '123', peripheral: SEMC, signal: 'DATA, 09', pin_signal: GPIO_EMC_33}
- {pin_num: '124', peripheral: SEMC, signal: 'DATA, 08', pin_signal: GPIO_EMC_32}
- {pin_num: '10', peripheral: SEMC, signal: 'DATA, 07', pin_signal: GPIO_EMC_07}
- {pin_num: '12', peripheral: SEMC, signal: 'DATA, 06', pin_signal: GPIO_EMC_06}
- {pin_num: '13', peripheral: SEMC, signal: 'DATA, 05', pin_signal: GPIO_EMC_05}
- {pin_num: '14', peripheral: SEMC, signal: 'DATA, 04', pin_signal: GPIO_EMC_04}
- {pin_num: '15', peripheral: SEMC, signal: 'DATA, 03', pin_signal: GPIO_EMC_03}
- {pin_num: '16', peripheral: SEMC, signal: 'DATA, 02', pin_signal: GPIO_EMC_02}
- {pin_num: '17', peripheral: SEMC, signal: 'DATA, 01', pin_signal: GPIO_EMC_01}
- {pin_num: '18', peripheral: SEMC, signal: 'DATA, 00', pin_signal: GPIO_EMC_00}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
/* FUNCTION ************************************************************************************************************
*
* Function Name : BOARD_InitSDRAMPins
* Description : Configures pin routing and optionally pin electrical features.
*
* END ****************************************************************************************************************/
void BOARD_InitSDRAMPins(void) {
CLOCK_EnableClock(kCLOCK_Iomuxc); /* iomuxc clock (iomuxc_clk_enable): 0x03U */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_00_SEMC_DATA00, /* GPIO_EMC_00 is configured as SEMC_DATA00 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_01_SEMC_DATA01, /* GPIO_EMC_01 is configured as SEMC_DATA01 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_02_SEMC_DATA02, /* GPIO_EMC_02 is configured as SEMC_DATA02 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_03_SEMC_DATA03, /* GPIO_EMC_03 is configured as SEMC_DATA03 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_04_SEMC_DATA04, /* GPIO_EMC_04 is configured as SEMC_DATA04 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_05_SEMC_DATA05, /* GPIO_EMC_05 is configured as SEMC_DATA05 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_06_SEMC_DATA06, /* GPIO_EMC_06 is configured as SEMC_DATA06 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_07_SEMC_DATA07, /* GPIO_EMC_07 is configured as SEMC_DATA07 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_08_SEMC_DM00, /* GPIO_EMC_08 is configured as SEMC_DM00 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_09_SEMC_WE, /* GPIO_EMC_09 is configured as SEMC_WE */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_10_SEMC_CAS, /* GPIO_EMC_10 is configured as SEMC_CAS */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_11_SEMC_RAS, /* GPIO_EMC_11 is configured as SEMC_RAS */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_12_SEMC_CS0, /* GPIO_EMC_12 is configured as SEMC_CS0 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_13_SEMC_BA0, /* GPIO_EMC_13 is configured as SEMC_BA0 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_14_SEMC_BA1, /* GPIO_EMC_14 is configured as SEMC_BA1 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_15_SEMC_ADDR10, /* GPIO_EMC_15 is configured as SEMC_ADDR10 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_16_SEMC_ADDR00, /* GPIO_EMC_16 is configured as SEMC_ADDR00 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_17_SEMC_ADDR01, /* GPIO_EMC_17 is configured as SEMC_ADDR01 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_18_SEMC_ADDR02, /* GPIO_EMC_18 is configured as SEMC_ADDR02 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_19_SEMC_ADDR03, /* GPIO_EMC_19 is configured as SEMC_ADDR03 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_20_SEMC_ADDR04, /* GPIO_EMC_20 is configured as SEMC_ADDR04 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_21_SEMC_ADDR05, /* GPIO_EMC_21 is configured as SEMC_ADDR05 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_22_SEMC_ADDR06, /* GPIO_EMC_22 is configured as SEMC_ADDR06 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_23_SEMC_ADDR07, /* GPIO_EMC_23 is configured as SEMC_ADDR07 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_24_SEMC_ADDR08, /* GPIO_EMC_24 is configured as SEMC_ADDR08 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_25_SEMC_ADDR09, /* GPIO_EMC_25 is configured as SEMC_ADDR09 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_26_SEMC_ADDR11, /* GPIO_EMC_26 is configured as SEMC_ADDR11 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_27_SEMC_ADDR12, /* GPIO_EMC_27 is configured as SEMC_ADDR12 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_28_SEMC_DQS, /* GPIO_EMC_28 is configured as SEMC_DQS */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_29_SEMC_CKE, /* GPIO_EMC_29 is configured as SEMC_CKE */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_30_SEMC_CLK, /* GPIO_EMC_30 is configured as SEMC_CLK */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_31_SEMC_DM01, /* GPIO_EMC_31 is configured as SEMC_DM01 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_32_SEMC_DATA08, /* GPIO_EMC_32 is configured as SEMC_DATA08 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_33_SEMC_DATA09, /* GPIO_EMC_33 is configured as SEMC_DATA09 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_34_SEMC_DATA10, /* GPIO_EMC_34 is configured as SEMC_DATA10 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_35_SEMC_DATA11, /* GPIO_EMC_35 is configured as SEMC_DATA11 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_36_SEMC_DATA12, /* GPIO_EMC_36 is configured as SEMC_DATA12 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_37_SEMC_DATA13, /* GPIO_EMC_37 is configured as SEMC_DATA13 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_38_SEMC_DATA14, /* GPIO_EMC_38 is configured as SEMC_DATA14 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_39_SEMC_DATA15, /* GPIO_EMC_39 is configured as SEMC_DATA15 */
0U); /* Software Input On Field: Input Path is determined by functionality */
}
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
BOARD_InitCANPins:
- options: {coreID: core0, enableClock: 'true'}
- pin_list:
- {pin_num: '32', peripheral: CAN1, signal: RX, pin_signal: GPIO_SD_B1_01}
- {pin_num: '33', peripheral: CAN1, signal: TX, pin_signal: GPIO_SD_B1_00}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
/* FUNCTION ************************************************************************************************************
*
* Function Name : BOARD_InitCANPins
* Description : Configures pin routing and optionally pin electrical features.
*
* END ****************************************************************************************************************/
void BOARD_InitCANPins(void) {
CLOCK_EnableClock(kCLOCK_Iomuxc); /* iomuxc clock (iomuxc_clk_enable): 0x03U */
IOMUXC_SetPinMux(
IOMUXC_GPIO_SD_B1_00_FLEXCAN1_TX, /* GPIO_SD_B1_00 is configured as FLEXCAN1_TX */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_SD_B1_01_FLEXCAN1_RX, /* GPIO_SD_B1_01 is configured as FLEXCAN1_RX */
0U); /* Software Input On Field: Input Path is determined by functionality */
}
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
BOARD_InitENETPins:
- options: {coreID: core0, enableClock: 'true'}
- pin_list:
- {pin_num: '97', peripheral: ENET, signal: enet_rx_en, pin_signal: GPIO_AD_B0_11}
- {pin_num: '84', peripheral: GPIO1, signal: 'gpio_io, 22', pin_signal: GPIO_AD_B1_06}
- {pin_num: '107', peripheral: GPIO1, signal: 'gpio_io, 04', pin_signal: GPIO_AD_B0_04}
- {pin_num: '100', peripheral: ENET, signal: enet_tx_clk, pin_signal: GPIO_AD_B0_08}
- {pin_num: '95', peripheral: ENET, signal: enet_tx_en, pin_signal: GPIO_AD_B0_13}
- {pin_num: '93', peripheral: ENET, signal: 'enet_tx_data, 1', pin_signal: GPIO_AD_B0_15}
- {pin_num: '94', peripheral: ENET, signal: 'enet_tx_data, 0', pin_signal: GPIO_AD_B0_14}
- {pin_num: '96', peripheral: ENET, signal: enet_rx_er, pin_signal: GPIO_AD_B0_12}
- {pin_num: '99', peripheral: ENET, signal: 'enet_rx_data, 1', pin_signal: GPIO_AD_B0_09}
- {pin_num: '98', peripheral: ENET, signal: 'enet_rx_data, 0', pin_signal: GPIO_AD_B0_10}
- {pin_num: '116', peripheral: ENET, signal: enet_mdio, pin_signal: GPIO_EMC_40}
- {pin_num: '115', peripheral: ENET, signal: enet_mdc, pin_signal: GPIO_EMC_41}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
/* FUNCTION ************************************************************************************************************
*
* Function Name : BOARD_InitENETPins
* Description : Configures pin routing and optionally pin electrical features.
*
* END ****************************************************************************************************************/
void BOARD_InitENETPins(void) {
CLOCK_EnableClock(kCLOCK_Iomuxc); /* iomuxc clock (iomuxc_clk_enable): 0x03U */
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_B0_04_GPIO1_IO04, /* GPIO_AD_B0_04 is configured as GPIO1_IO04 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_B0_08_ENET_TX_CLK, /* GPIO_AD_B0_08 is configured as ENET_TX_CLK */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_B0_09_ENET_RDATA01, /* GPIO_AD_B0_09 is configured as ENET_RDATA01 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_B0_10_ENET_RDATA00, /* GPIO_AD_B0_10 is configured as ENET_RDATA00 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_B0_11_ENET_RX_EN, /* GPIO_AD_B0_11 is configured as ENET_RX_EN */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_B0_12_ENET_RX_ER, /* GPIO_AD_B0_12 is configured as ENET_RX_ER */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_B0_13_ENET_TX_EN, /* GPIO_AD_B0_13 is configured as ENET_TX_EN */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_B0_14_ENET_TDATA00, /* GPIO_AD_B0_14 is configured as ENET_TDATA00 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_B0_15_ENET_TDATA01, /* GPIO_AD_B0_15 is configured as ENET_TDATA01 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_B1_06_GPIO1_IO22, /* GPIO_AD_B1_06 is configured as GPIO1_IO22 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_40_ENET_MDIO, /* GPIO_EMC_40 is configured as ENET_MDIO */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_41_ENET_MDC, /* GPIO_EMC_41 is configured as ENET_MDC */
0U); /* Software Input On Field: Input Path is determined by functionality */
}
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
BOARD_InitUSDHCPins:
- options: {coreID: core0, enableClock: 'true'}
- pin_list:
- {pin_num: '45', peripheral: USDHC1, signal: usdhc_clk, pin_signal: GPIO_SD_B0_03}
- {pin_num: '46', peripheral: USDHC1, signal: usdhc_cmd, pin_signal: GPIO_SD_B0_02}
- {pin_num: '43', peripheral: USDHC1, signal: 'usdhc_data, 0', pin_signal: GPIO_SD_B0_04}
- {pin_num: '42', peripheral: USDHC1, signal: 'usdhc_data, 1', pin_signal: GPIO_SD_B0_05}
- {pin_num: '48', peripheral: USDHC1, signal: 'usdhc_data, 2', pin_signal: GPIO_SD_B0_00}
- {pin_num: '47', peripheral: USDHC1, signal: 'usdhc_data, 3', pin_signal: GPIO_SD_B0_01}
- {pin_num: '41', peripheral: GPIO3, signal: 'gpio_io, 19', pin_signal: GPIO_SD_B0_06}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
/* FUNCTION ************************************************************************************************************
*
* Function Name : BOARD_InitUSDHCPins
* Description : Configures pin routing and optionally pin electrical features.
*
* END ****************************************************************************************************************/
void BOARD_InitUSDHCPins(void) {
CLOCK_EnableClock(kCLOCK_Iomuxc); /* iomuxc clock (iomuxc_clk_enable): 0x03U */
IOMUXC_SetPinMux(
IOMUXC_GPIO_SD_B0_00_USDHC1_DATA2, /* GPIO_SD_B0_00 is configured as USDHC1_DATA2 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_SD_B0_01_USDHC1_DATA3, /* GPIO_SD_B0_01 is configured as USDHC1_DATA3 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_SD_B0_02_USDHC1_CMD, /* GPIO_SD_B0_02 is configured as USDHC1_CMD */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_SD_B0_03_USDHC1_CLK, /* GPIO_SD_B0_03 is configured as USDHC1_CLK */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_SD_B0_04_USDHC1_DATA0, /* GPIO_SD_B0_04 is configured as USDHC1_DATA0 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_SD_B0_05_USDHC1_DATA1, /* GPIO_SD_B0_05 is configured as USDHC1_DATA1 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_SD_B0_06_GPIO3_IO19, /* GPIO_SD_B0_06 is configured as GPIO3_IO19 */
0U); /* Software Input On Field: Input Path is determined by functionality */
}
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
BOARD_InitQSPIPins:
- options: {coreID: core0, enableClock: 'true'}
- pin_list:
- {pin_num: '24', peripheral: FLEXSPI, signal: FLEXSPI_A_SCLK, pin_signal: GPIO_SD_B1_07}
- {pin_num: '23', peripheral: FLEXSPI, signal: FLEXSPI_A_DATA0, pin_signal: GPIO_SD_B1_08}
- {pin_num: '21', peripheral: FLEXSPI, signal: FLEXSPI_A_DATA1, pin_signal: GPIO_SD_B1_10}
- {pin_num: '22', peripheral: FLEXSPI, signal: FLEXSPI_A_DATA2, pin_signal: GPIO_SD_B1_09}
- {pin_num: '25', peripheral: FLEXSPI, signal: FLEXSPI_A_DATA3, pin_signal: GPIO_SD_B1_06}
- {pin_num: '19', peripheral: FLEXSPI, signal: FLEXSPI_A_SS0_B, pin_signal: GPIO_SD_B1_11}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
/* FUNCTION ************************************************************************************************************
*
* Function Name : BOARD_InitQSPIPins
* Description : Configures pin routing and optionally pin electrical features.
*
* END ****************************************************************************************************************/
void BOARD_InitQSPIPins(void) {
CLOCK_EnableClock(kCLOCK_Iomuxc); /* iomuxc clock (iomuxc_clk_enable): 0x03U */
IOMUXC_SetPinMux(
IOMUXC_GPIO_SD_B1_06_FLEXSPI_A_DATA03, /* GPIO_SD_B1_06 is configured as FLEXSPI_A_DATA03 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_SD_B1_07_FLEXSPI_A_SCLK, /* GPIO_SD_B1_07 is configured as FLEXSPI_A_SCLK */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_SD_B1_08_FLEXSPI_A_DATA00, /* GPIO_SD_B1_08 is configured as FLEXSPI_A_DATA00 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_SD_B1_09_FLEXSPI_A_DATA02, /* GPIO_SD_B1_09 is configured as FLEXSPI_A_DATA02 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_SD_B1_10_FLEXSPI_A_DATA01, /* GPIO_SD_B1_10 is configured as FLEXSPI_A_DATA01 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_SD_B1_11_FLEXSPI_A_SS0_B, /* GPIO_SD_B1_11 is configured as FLEXSPI_A_SS0_B */
0U); /* Software Input On Field: Input Path is determined by functionality */
}
/***********************************************************************************************************************
* EOF
**********************************************************************************************************************/

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/***********************************************************************************************************************
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
**********************************************************************************************************************/
#ifndef _PIN_MUX_H_
#define _PIN_MUX_H_
/***********************************************************************************************************************
* Definitions
**********************************************************************************************************************/
/* Define the flexspi macro. Note that it can't be modified here */
#define IOMUXC_GPIO_AD_B1_00_FLEXSPI_A_DATA03 0x401F80FCU, 0x1U, 0x401F8374U, 0x1U, 0x401F8270U
#define IOMUXC_GPIO_AD_B1_01_FLEXSPI_A_SCLK 0x401F8100U, 0x1U, 0x401F8378U, 0x1U, 0x401F8274U
#define IOMUXC_GPIO_AD_B1_02_FLEXSPI_A_DATA00 0x401F8104U, 0x1U, 0x401F8368U, 0x1U, 0x401F8278U
#define IOMUXC_GPIO_AD_B1_03_FLEXSPI_A_DATA02 0x401F8108U, 0x1U, 0x401F8370U, 0x1U, 0x401F827CU
#define IOMUXC_GPIO_AD_B1_04_FLEXSPI_A_DATA01 0x401F810CU, 0x1U, 0x401F836CU, 0x1U, 0x401F8280U
#define IOMUXC_GPIO_AD_B1_05_FLEXSPI_A_SS0_B 0x401F8110U, 0x1U, 0, 0, 0x401F8284U
/*! @brief Direction type */
typedef enum _pin_mux_direction
{
kPIN_MUX_DirectionInput = 0U, /* Input direction */
kPIN_MUX_DirectionOutput = 1U, /* Output direction */
kPIN_MUX_DirectionInputOrOutput = 2U /* Input or output direction */
} pin_mux_direction_t;
/*!
* @addtogroup pin_mux
* @{
*/
/***********************************************************************************************************************
* API
**********************************************************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif
/*!
* @brief Calls initialization functions.
*
*/
void BOARD_InitBootPins(void);
/* WAKEUP (number 52), USER_BUTTON */
#define BOARD_INITPINS_USER_BUTTON_GPIO GPIO5 /*!< GPIO device name: GPIO5 */
#define BOARD_INITPINS_USER_BUTTON_PORT GPIO5 /*!< PORT device name: GPIO5 */
#define BOARD_INITPINS_USER_BUTTON_PIN 0U /*!< GPIO5 pin index: 0 */
/* GPIO_AD_B1_08 (number 82), UART_TX/USER_LED/J17[4] */
#define BOARD_INITPINS_USER_LED_GPIO GPIO1 /*!< GPIO device name: GPIO1 */
#define BOARD_INITPINS_USER_LED_PORT GPIO1 /*!< PORT device name: GPIO1 */
#define BOARD_INITPINS_USER_LED_PIN 24U /*!< GPIO1 pin index: 24 */
/*!
* @brief Configures pin routing and optionally pin electrical features.
*
*/
void BOARD_InitPins(void);
/* GPIO_AD_B0_07 (number 101), UART1_RXD/J17[8] */
#define BOARD_INITDEBUG_UARTPINS_UART1_RXD_PERIPHERAL LPUART1 /*!< Device name: LPUART1 */
#define BOARD_INITDEBUG_UARTPINS_UART1_RXD_SIGNAL RX /*!< LPUART1 signal: RX */
/* GPIO_AD_B0_06 (number 105), UART1_TXD/J17[12] */
#define BOARD_INITDEBUG_UARTPINS_UART1_TXD_PERIPHERAL LPUART1 /*!< Device name: LPUART1 */
#define BOARD_INITDEBUG_UARTPINS_UART1_TXD_SIGNAL TX /*!< LPUART1 signal: TX */
/*!
* @brief Configures pin routing and optionally pin electrical features.
*
*/
void BOARD_InitDEBUG_UARTPins(void);
/* GPIO_EMC_16 (number 142), SEMC_A0/U14[23]/BOOT_MODE[0] */
#define BOARD_INITSDRAMPINS_SEMC_A0_PERIPHERAL SEMC /*!< Device name: SEMC */
#define BOARD_INITSDRAMPINS_SEMC_A0_SIGNAL ADDR /*!< SEMC signal: ADDR */
#define BOARD_INITSDRAMPINS_SEMC_A0_CHANNEL 0U /*!< SEMC ADDR channel: 00 */
/* GPIO_EMC_17 (number 141), SEMC_A1/U14[24]/BOOT_MODE[1] */
#define BOARD_INITSDRAMPINS_SEMC_A1_PERIPHERAL SEMC /*!< Device name: SEMC */
#define BOARD_INITSDRAMPINS_SEMC_A1_SIGNAL ADDR /*!< SEMC signal: ADDR */
#define BOARD_INITSDRAMPINS_SEMC_A1_CHANNEL 1U /*!< SEMC ADDR channel: 01 */
/* GPIO_EMC_18 (number 140), SEMC_A2/U14[25]/BT_CFG[0] */
#define BOARD_INITSDRAMPINS_SEMC_A2_PERIPHERAL SEMC /*!< Device name: SEMC */
#define BOARD_INITSDRAMPINS_SEMC_A2_SIGNAL ADDR /*!< SEMC signal: ADDR */
#define BOARD_INITSDRAMPINS_SEMC_A2_CHANNEL 2U /*!< SEMC ADDR channel: 02 */
/* GPIO_EMC_19 (number 139), SEMC_A3/U14[26]/BT_CFG[1] */
#define BOARD_INITSDRAMPINS_SEMC_A3_PERIPHERAL SEMC /*!< Device name: SEMC */
#define BOARD_INITSDRAMPINS_SEMC_A3_SIGNAL ADDR /*!< SEMC signal: ADDR */
#define BOARD_INITSDRAMPINS_SEMC_A3_CHANNEL 3U /*!< SEMC ADDR channel: 03 */
/* GPIO_EMC_20 (number 138), SEMC_A4/U14[29]/BT_CFG[2] */
#define BOARD_INITSDRAMPINS_SEMC_A4_PERIPHERAL SEMC /*!< Device name: SEMC */
#define BOARD_INITSDRAMPINS_SEMC_A4_SIGNAL ADDR /*!< SEMC signal: ADDR */
#define BOARD_INITSDRAMPINS_SEMC_A4_CHANNEL 4U /*!< SEMC ADDR channel: 04 */
/* GPIO_EMC_22 (number 136), SEMC_A6/U14[31]/BT_CFG[4] */
#define BOARD_INITSDRAMPINS_SEMC_A6_PERIPHERAL SEMC /*!< Device name: SEMC */
#define BOARD_INITSDRAMPINS_SEMC_A6_SIGNAL ADDR /*!< SEMC signal: ADDR */
#define BOARD_INITSDRAMPINS_SEMC_A6_CHANNEL 6U /*!< SEMC ADDR channel: 06 */
/* GPIO_EMC_21 (number 137), SEMC_A5/U14[30]/BT_CFG[3] */
#define BOARD_INITSDRAMPINS_SEMC_A5_PERIPHERAL SEMC /*!< Device name: SEMC */
#define BOARD_INITSDRAMPINS_SEMC_A5_SIGNAL ADDR /*!< SEMC signal: ADDR */
#define BOARD_INITSDRAMPINS_SEMC_A5_CHANNEL 5U /*!< SEMC ADDR channel: 05 */
/* GPIO_EMC_23 (number 133), SEMC_A7/U14[32]/BT_CFG[5] */
#define BOARD_INITSDRAMPINS_SEMC_A7_PERIPHERAL SEMC /*!< Device name: SEMC */
#define BOARD_INITSDRAMPINS_SEMC_A7_SIGNAL ADDR /*!< SEMC signal: ADDR */
#define BOARD_INITSDRAMPINS_SEMC_A7_CHANNEL 7U /*!< SEMC ADDR channel: 07 */
/* GPIO_EMC_24 (number 132), SEMC_A8/U14[33]/BT_CFG[6] */
#define BOARD_INITSDRAMPINS_SEMC_A8_PERIPHERAL SEMC /*!< Device name: SEMC */
#define BOARD_INITSDRAMPINS_SEMC_A8_SIGNAL ADDR /*!< SEMC signal: ADDR */
#define BOARD_INITSDRAMPINS_SEMC_A8_CHANNEL 8U /*!< SEMC ADDR channel: 08 */
/* GPIO_EMC_25 (number 131), SEMC_A9/U14[34]/BT_CFG[7] */
#define BOARD_INITSDRAMPINS_SEMC_A9_PERIPHERAL SEMC /*!< Device name: SEMC */
#define BOARD_INITSDRAMPINS_SEMC_A9_SIGNAL ADDR /*!< SEMC signal: ADDR */
#define BOARD_INITSDRAMPINS_SEMC_A9_CHANNEL 9U /*!< SEMC ADDR channel: 09 */
/* GPIO_EMC_15 (number 143), SEMC_A10/U14[22] */
#define BOARD_INITSDRAMPINS_SEMC_A10_PERIPHERAL SEMC /*!< Device name: SEMC */
#define BOARD_INITSDRAMPINS_SEMC_A10_SIGNAL ADDR /*!< SEMC signal: ADDR */
#define BOARD_INITSDRAMPINS_SEMC_A10_CHANNEL 10U /*!< SEMC ADDR channel: 10 */
/* GPIO_EMC_26 (number 130), SEMC_A11/U14[35]/BT_CFG[8] */
#define BOARD_INITSDRAMPINS_SEMC_A11_PERIPHERAL SEMC /*!< Device name: SEMC */
#define BOARD_INITSDRAMPINS_SEMC_A11_SIGNAL ADDR /*!< SEMC signal: ADDR */
#define BOARD_INITSDRAMPINS_SEMC_A11_CHANNEL 11U /*!< SEMC ADDR channel: 11 */
/* GPIO_EMC_27 (number 129), SEMC_A12/U14[36]/BT_CFG[9] */
#define BOARD_INITSDRAMPINS_SEMC_A12_PERIPHERAL SEMC /*!< Device name: SEMC */
#define BOARD_INITSDRAMPINS_SEMC_A12_SIGNAL ADDR /*!< SEMC signal: ADDR */
#define BOARD_INITSDRAMPINS_SEMC_A12_CHANNEL 12U /*!< SEMC ADDR channel: 12 */
/* GPIO_EMC_13 (number 2), SEMC_BA0/U14[20] */
#define BOARD_INITSDRAMPINS_SEMC_BA0_PERIPHERAL SEMC /*!< Device name: SEMC */
#define BOARD_INITSDRAMPINS_SEMC_BA0_SIGNAL BA /*!< SEMC signal: BA */
#define BOARD_INITSDRAMPINS_SEMC_BA0_CHANNEL 0U /*!< SEMC BA channel: 0 */
/* GPIO_EMC_14 (number 1), SEMC_BA1/U14[21] */
#define BOARD_INITSDRAMPINS_SEMC_BA1_PERIPHERAL SEMC /*!< Device name: SEMC */
#define BOARD_INITSDRAMPINS_SEMC_BA1_SIGNAL BA /*!< SEMC signal: BA */
#define BOARD_INITSDRAMPINS_SEMC_BA1_CHANNEL 1U /*!< SEMC BA channel: 1 */
/* GPIO_EMC_10 (number 7), SEMC_CAS/U14[17] */
#define BOARD_INITSDRAMPINS_SEMC_CAS_PERIPHERAL SEMC /*!< Device name: SEMC */
#define BOARD_INITSDRAMPINS_SEMC_CAS_SIGNAL semc_cas /*!< SEMC signal: semc_cas */
/* GPIO_EMC_29 (number 127), SEMC_CKE/U14[37] */
#define BOARD_INITSDRAMPINS_SEMC_CKE_PERIPHERAL SEMC /*!< Device name: SEMC */
#define BOARD_INITSDRAMPINS_SEMC_CKE_SIGNAL semc_cke /*!< SEMC signal: semc_cke */
/* GPIO_EMC_30 (number 126), SEMC_CLK/U14[38] */
#define BOARD_INITSDRAMPINS_SEMC_CLK_PERIPHERAL SEMC /*!< Device name: SEMC */
#define BOARD_INITSDRAMPINS_SEMC_CLK_SIGNAL semc_clk /*!< SEMC signal: semc_clk */
/* GPIO_EMC_12 (number 3), SEMC_CS0/U14[19] */
#define BOARD_INITSDRAMPINS_SEMC_CS0_PERIPHERAL SEMC /*!< Device name: SEMC */
#define BOARD_INITSDRAMPINS_SEMC_CS0_SIGNAL CS /*!< SEMC signal: CS */
#define BOARD_INITSDRAMPINS_SEMC_CS0_CHANNEL 0U /*!< SEMC CS channel: 0 */
/* GPIO_EMC_09 (number 8), SEMC_WE/U14[16] */
#define BOARD_INITSDRAMPINS_SEMC_WE_PERIPHERAL SEMC /*!< Device name: SEMC */
#define BOARD_INITSDRAMPINS_SEMC_WE_SIGNAL semc_we /*!< SEMC signal: semc_we */
/* GPIO_EMC_11 (number 4), SEMC_RAS/U14[18] */
#define BOARD_INITSDRAMPINS_SEMC_RAS_PERIPHERAL SEMC /*!< Device name: SEMC */
#define BOARD_INITSDRAMPINS_SEMC_RAS_SIGNAL semc_ras /*!< SEMC signal: semc_ras */
/* GPIO_EMC_28 (number 128), SAI3_MCLK */
#define BOARD_INITSDRAMPINS_SEMC_DQS_PERIPHERAL SEMC /*!< Device name: SEMC */
#define BOARD_INITSDRAMPINS_SEMC_DQS_SIGNAL semc_dqs /*!< SEMC signal: semc_dqs */
/* GPIO_EMC_31 (number 125), SEMC_DM1/U14[39] */
#define BOARD_INITSDRAMPINS_SEMC_DM1_PERIPHERAL SEMC /*!< Device name: SEMC */
#define BOARD_INITSDRAMPINS_SEMC_DM1_SIGNAL DM /*!< SEMC signal: DM */
#define BOARD_INITSDRAMPINS_SEMC_DM1_CHANNEL 1U /*!< SEMC DM channel: 1 */
/* GPIO_EMC_08 (number 9), SEMC_DM0/U14[15] */
#define BOARD_INITSDRAMPINS_SEMC_DM0_PERIPHERAL SEMC /*!< Device name: SEMC */
#define BOARD_INITSDRAMPINS_SEMC_DM0_SIGNAL DM /*!< SEMC signal: DM */
#define BOARD_INITSDRAMPINS_SEMC_DM0_CHANNEL 0U /*!< SEMC DM channel: 0 */
/* GPIO_EMC_39 (number 117), SEMC_D15/U14[53] */
#define BOARD_INITSDRAMPINS_SEMC_D15_PERIPHERAL SEMC /*!< Device name: SEMC */
#define BOARD_INITSDRAMPINS_SEMC_D15_SIGNAL DATA /*!< SEMC signal: DATA */
#define BOARD_INITSDRAMPINS_SEMC_D15_CHANNEL 15U /*!< SEMC DATA channel: 15 */
/* GPIO_EMC_38 (number 118), SEMC_D14/U14[51] */
#define BOARD_INITSDRAMPINS_SEMC_D14_PERIPHERAL SEMC /*!< Device name: SEMC */
#define BOARD_INITSDRAMPINS_SEMC_D14_SIGNAL DATA /*!< SEMC signal: DATA */
#define BOARD_INITSDRAMPINS_SEMC_D14_CHANNEL 14U /*!< SEMC DATA channel: 14 */
/* GPIO_EMC_37 (number 119), SEMC_D13/U14[50] */
#define BOARD_INITSDRAMPINS_SEMC_D13_PERIPHERAL SEMC /*!< Device name: SEMC */
#define BOARD_INITSDRAMPINS_SEMC_D13_SIGNAL DATA /*!< SEMC signal: DATA */
#define BOARD_INITSDRAMPINS_SEMC_D13_CHANNEL 13U /*!< SEMC DATA channel: 13 */
/* GPIO_EMC_36 (number 120), SEMC_D12/U14[48] */
#define BOARD_INITSDRAMPINS_SEMC_D12_PERIPHERAL SEMC /*!< Device name: SEMC */
#define BOARD_INITSDRAMPINS_SEMC_D12_SIGNAL DATA /*!< SEMC signal: DATA */
#define BOARD_INITSDRAMPINS_SEMC_D12_CHANNEL 12U /*!< SEMC DATA channel: 12 */
/* GPIO_EMC_34 (number 122), SEMC_D10/U14[45] */
#define BOARD_INITSDRAMPINS_SEMC_D10_PERIPHERAL SEMC /*!< Device name: SEMC */
#define BOARD_INITSDRAMPINS_SEMC_D10_SIGNAL DATA /*!< SEMC signal: DATA */
#define BOARD_INITSDRAMPINS_SEMC_D10_CHANNEL 10U /*!< SEMC DATA channel: 10 */
/* GPIO_EMC_35 (number 121), SEMC_D11/U14[47] */
#define BOARD_INITSDRAMPINS_SEMC_D11_PERIPHERAL SEMC /*!< Device name: SEMC */
#define BOARD_INITSDRAMPINS_SEMC_D11_SIGNAL DATA /*!< SEMC signal: DATA */
#define BOARD_INITSDRAMPINS_SEMC_D11_CHANNEL 11U /*!< SEMC DATA channel: 11 */
/* GPIO_EMC_33 (number 123), SEMC_D9/U14[44] */
#define BOARD_INITSDRAMPINS_SEMC_D9_PERIPHERAL SEMC /*!< Device name: SEMC */
#define BOARD_INITSDRAMPINS_SEMC_D9_SIGNAL DATA /*!< SEMC signal: DATA */
#define BOARD_INITSDRAMPINS_SEMC_D9_CHANNEL 9U /*!< SEMC DATA channel: 09 */
/* GPIO_EMC_32 (number 124), SEMC_D8/U14[42] */
#define BOARD_INITSDRAMPINS_SEMC_D8_PERIPHERAL SEMC /*!< Device name: SEMC */
#define BOARD_INITSDRAMPINS_SEMC_D8_SIGNAL DATA /*!< SEMC signal: DATA */
#define BOARD_INITSDRAMPINS_SEMC_D8_CHANNEL 8U /*!< SEMC DATA channel: 08 */
/* GPIO_EMC_07 (number 10), SEMC_D7/U14[13] */
#define BOARD_INITSDRAMPINS_SEMC_D7_PERIPHERAL SEMC /*!< Device name: SEMC */
#define BOARD_INITSDRAMPINS_SEMC_D7_SIGNAL DATA /*!< SEMC signal: DATA */
#define BOARD_INITSDRAMPINS_SEMC_D7_CHANNEL 7U /*!< SEMC DATA channel: 07 */
/* GPIO_EMC_06 (number 12), SEMC_D6/U14[11] */
#define BOARD_INITSDRAMPINS_SEMC_D6_PERIPHERAL SEMC /*!< Device name: SEMC */
#define BOARD_INITSDRAMPINS_SEMC_D6_SIGNAL DATA /*!< SEMC signal: DATA */
#define BOARD_INITSDRAMPINS_SEMC_D6_CHANNEL 6U /*!< SEMC DATA channel: 06 */
/* GPIO_EMC_05 (number 13), SEMC_D5/U14[10] */
#define BOARD_INITSDRAMPINS_SEMC_D5_PERIPHERAL SEMC /*!< Device name: SEMC */
#define BOARD_INITSDRAMPINS_SEMC_D5_SIGNAL DATA /*!< SEMC signal: DATA */
#define BOARD_INITSDRAMPINS_SEMC_D5_CHANNEL 5U /*!< SEMC DATA channel: 05 */
/* GPIO_EMC_04 (number 14), SEMC_D4/U14[8] */
#define BOARD_INITSDRAMPINS_SEMC_D4_PERIPHERAL SEMC /*!< Device name: SEMC */
#define BOARD_INITSDRAMPINS_SEMC_D4_SIGNAL DATA /*!< SEMC signal: DATA */
#define BOARD_INITSDRAMPINS_SEMC_D4_CHANNEL 4U /*!< SEMC DATA channel: 04 */
/* GPIO_EMC_03 (number 15), SEMC_D3/U14[7] */
#define BOARD_INITSDRAMPINS_SEMC_D3_PERIPHERAL SEMC /*!< Device name: SEMC */
#define BOARD_INITSDRAMPINS_SEMC_D3_SIGNAL DATA /*!< SEMC signal: DATA */
#define BOARD_INITSDRAMPINS_SEMC_D3_CHANNEL 3U /*!< SEMC DATA channel: 03 */
/* GPIO_EMC_02 (number 16), SEMC_D2/U14[5] */
#define BOARD_INITSDRAMPINS_SEMC_D2_PERIPHERAL SEMC /*!< Device name: SEMC */
#define BOARD_INITSDRAMPINS_SEMC_D2_SIGNAL DATA /*!< SEMC signal: DATA */
#define BOARD_INITSDRAMPINS_SEMC_D2_CHANNEL 2U /*!< SEMC DATA channel: 02 */
/* GPIO_EMC_01 (number 17), SEMC_D1/U14[4] */
#define BOARD_INITSDRAMPINS_SEMC_D1_PERIPHERAL SEMC /*!< Device name: SEMC */
#define BOARD_INITSDRAMPINS_SEMC_D1_SIGNAL DATA /*!< SEMC signal: DATA */
#define BOARD_INITSDRAMPINS_SEMC_D1_CHANNEL 1U /*!< SEMC DATA channel: 01 */
/* GPIO_EMC_00 (number 18), SEMC_D0/U14[2] */
#define BOARD_INITSDRAMPINS_SEMC_D0_PERIPHERAL SEMC /*!< Device name: SEMC */
#define BOARD_INITSDRAMPINS_SEMC_D0_SIGNAL DATA /*!< SEMC signal: DATA */
#define BOARD_INITSDRAMPINS_SEMC_D0_CHANNEL 0U /*!< SEMC DATA channel: 00 */
/*!
* @brief Configures pin routing and optionally pin electrical features.
*
*/
void BOARD_InitSDRAMPins(void);
/* GPIO_SD_B1_01 (number 32), CAN1_RX/U9[4] */
#define BOARD_INITCANPINS_CAN1_RX_PERIPHERAL CAN1 /*!< Device name: CAN1 */
#define BOARD_INITCANPINS_CAN1_RX_SIGNAL RX /*!< CAN1 signal: RX */
/* GPIO_SD_B1_00 (number 33), CAN1_TX/U9[1] */
#define BOARD_INITCANPINS_CAN1_TX_PERIPHERAL CAN1 /*!< Device name: CAN1 */
#define BOARD_INITCANPINS_CAN1_TX_SIGNAL TX /*!< CAN1 signal: TX */
/*!
* @brief Configures pin routing and optionally pin electrical features.
*
*/
void BOARD_InitCANPins(void);
/* GPIO_AD_B0_11 (number 97), ENET_CRS_DV/U11[18]/J19[6] */
#define BOARD_INITENETPINS_ENET_CRS_DV_PERIPHERAL ENET /*!< Device name: ENET */
#define BOARD_INITENETPINS_ENET_CRS_DV_SIGNAL enet_rx_en /*!< ENET signal: enet_rx_en */
/* GPIO_AD_B1_06 (number 84), ENET_INT/U11[21]/J17[16] */
#define BOARD_INITENETPINS_ENET_INT_GPIO GPIO1 /*!< GPIO device name: GPIO1 */
#define BOARD_INITENETPINS_ENET_INT_PORT GPIO1 /*!< PORT device name: GPIO1 */
#define BOARD_INITENETPINS_ENET_INT_PIN 22U /*!< GPIO1 pin index: 22 */
/* GPIO_AD_B0_04 (number 107), JTAG_TDO/ENET_RST/U11[32] */
#define BOARD_INITENETPINS_ENET_RST_GPIO GPIO1 /*!< GPIO device name: GPIO1 */
#define BOARD_INITENETPINS_ENET_RST_PORT GPIO1 /*!< PORT device name: GPIO1 */
#define BOARD_INITENETPINS_ENET_RST_PIN 4U /*!< GPIO1 pin index: 4 */
/* GPIO_AD_B0_08 (number 100), ENET_TX_REF_CLK/U11[9] */
#define BOARD_INITENETPINS_ENET_TX_CLK_PERIPHERAL ENET /*!< Device name: ENET */
#define BOARD_INITENETPINS_ENET_TX_CLK_SIGNAL enet_tx_clk /*!< ENET signal: enet_tx_clk */
/* GPIO_AD_B0_13 (number 95), ENET_TXEN/U11[23]/J19[10] */
#define BOARD_INITENETPINS_ENET_TXEN_PERIPHERAL ENET /*!< Device name: ENET */
#define BOARD_INITENETPINS_ENET_TXEN_SIGNAL enet_tx_en /*!< ENET signal: enet_tx_en */
/* GPIO_AD_B0_15 (number 93), ENET_TXD1/U11[25]/J19[4] */
#define BOARD_INITENETPINS_ENET_TXD1_PERIPHERAL ENET /*!< Device name: ENET */
#define BOARD_INITENETPINS_ENET_TXD1_SIGNAL enet_tx_data /*!< ENET signal: enet_tx_data */
#define BOARD_INITENETPINS_ENET_TXD1_CHANNEL 1U /*!< ENET enet_tx_data channel: 1 */
/* GPIO_AD_B0_14 (number 94), ENET_TXD0/U11[24]/J17[14] */
#define BOARD_INITENETPINS_ENET_TXD0_PERIPHERAL ENET /*!< Device name: ENET */
#define BOARD_INITENETPINS_ENET_TXD0_SIGNAL enet_tx_data /*!< ENET signal: enet_tx_data */
#define BOARD_INITENETPINS_ENET_TXD0_CHANNEL 0U /*!< ENET enet_tx_data channel: 0 */
/* GPIO_AD_B0_12 (number 96), ENET_RXER/U11[20]/J19[8] */
#define BOARD_INITENETPINS_ENET_RXER_PERIPHERAL ENET /*!< Device name: ENET */
#define BOARD_INITENETPINS_ENET_RXER_SIGNAL enet_rx_er /*!< ENET signal: enet_rx_er */
/* GPIO_AD_B0_09 (number 99), ENET_RXD1/U11[15]/J17[6] */
#define BOARD_INITENETPINS_ENET_RXD1_PERIPHERAL ENET /*!< Device name: ENET */
#define BOARD_INITENETPINS_ENET_RXD1_SIGNAL enet_rx_data /*!< ENET signal: enet_rx_data */
#define BOARD_INITENETPINS_ENET_RXD1_CHANNEL 1U /*!< ENET enet_rx_data channel: 1 */
/* GPIO_AD_B0_10 (number 98), ENET_RXD0/U11[16]/J19[12] */
#define BOARD_INITENETPINS_ENET_RXD0_PERIPHERAL ENET /*!< Device name: ENET */
#define BOARD_INITENETPINS_ENET_RXD0_SIGNAL enet_rx_data /*!< ENET signal: enet_rx_data */
#define BOARD_INITENETPINS_ENET_RXD0_CHANNEL 0U /*!< ENET enet_rx_data channel: 0 */
/* GPIO_EMC_40 (number 116), ENET_MDIO/U11[11] */
#define BOARD_INITENETPINS_ENET_MDIO_PERIPHERAL ENET /*!< Device name: ENET */
#define BOARD_INITENETPINS_ENET_MDIO_SIGNAL enet_mdio /*!< ENET signal: enet_mdio */
/* GPIO_EMC_41 (number 115), ENET_MDC/U11[12] */
#define BOARD_INITENETPINS_ENET_MDC_PERIPHERAL ENET /*!< Device name: ENET */
#define BOARD_INITENETPINS_ENET_MDC_SIGNAL enet_mdc /*!< ENET signal: enet_mdc */
/*!
* @brief Configures pin routing and optionally pin electrical features.
*
*/
void BOARD_InitENETPins(void);
/* GPIO_SD_B0_03 (number 45), SD1_CLK/J15[5] */
#define BOARD_INITUSDHCPINS_SD1_CLK_PERIPHERAL USDHC1 /*!< Device name: USDHC1 */
#define BOARD_INITUSDHCPINS_SD1_CLK_SIGNAL usdhc_clk /*!< USDHC1 signal: usdhc_clk */
/* GPIO_SD_B0_02 (number 46), SD1_CMD/J15[3] */
#define BOARD_INITUSDHCPINS_SD1_CMD_PERIPHERAL USDHC1 /*!< Device name: USDHC1 */
#define BOARD_INITUSDHCPINS_SD1_CMD_SIGNAL usdhc_cmd /*!< USDHC1 signal: usdhc_cmd */
/* GPIO_SD_B0_04 (number 43), SD1_D0/J15[7] */
#define BOARD_INITUSDHCPINS_SD1_D0_PERIPHERAL USDHC1 /*!< Device name: USDHC1 */
#define BOARD_INITUSDHCPINS_SD1_D0_SIGNAL usdhc_data /*!< USDHC1 signal: usdhc_data */
#define BOARD_INITUSDHCPINS_SD1_D0_CHANNEL 0U /*!< USDHC1 usdhc_data channel: 0 */
/* GPIO_SD_B0_05 (number 42), SD1_D1/J15[8] */
#define BOARD_INITUSDHCPINS_SD1_D1_PERIPHERAL USDHC1 /*!< Device name: USDHC1 */
#define BOARD_INITUSDHCPINS_SD1_D1_SIGNAL usdhc_data /*!< USDHC1 signal: usdhc_data */
#define BOARD_INITUSDHCPINS_SD1_D1_CHANNEL 1U /*!< USDHC1 usdhc_data channel: 1 */
/* GPIO_SD_B0_00 (number 48), SD1_D2/J15[1] */
#define BOARD_INITUSDHCPINS_SD1_D2_PERIPHERAL USDHC1 /*!< Device name: USDHC1 */
#define BOARD_INITUSDHCPINS_SD1_D2_SIGNAL usdhc_data /*!< USDHC1 signal: usdhc_data */
#define BOARD_INITUSDHCPINS_SD1_D2_CHANNEL 2U /*!< USDHC1 usdhc_data channel: 2 */
/* GPIO_SD_B0_01 (number 47), SD1_D3/J15[2] */
#define BOARD_INITUSDHCPINS_SD1_D3_PERIPHERAL USDHC1 /*!< Device name: USDHC1 */
#define BOARD_INITUSDHCPINS_SD1_D3_SIGNAL usdhc_data /*!< USDHC1 signal: usdhc_data */
#define BOARD_INITUSDHCPINS_SD1_D3_CHANNEL 3U /*!< USDHC1 usdhc_data channel: 3 */
/* GPIO_SD_B0_06 (number 41), SD_CD_SW/J15[9] */
#define BOARD_INITUSDHCPINS_SD_CD_SW_GPIO GPIO3 /*!< GPIO device name: GPIO3 */
#define BOARD_INITUSDHCPINS_SD_CD_SW_PORT GPIO3 /*!< PORT device name: GPIO3 */
#define BOARD_INITUSDHCPINS_SD_CD_SW_PIN 19U /*!< GPIO3 pin index: 19 */
/*!
* @brief Configures pin routing and optionally pin electrical features.
*
*/
void BOARD_InitUSDHCPins(void);
/* GPIO_SD_B1_07 (number 24), SAI3_TX_SYNC */
#define BOARD_INITQSPIPINS_FlexSPI_CLK_PERIPHERAL FLEXSPI /*!< Device name: FLEXSPI */
#define BOARD_INITQSPIPINS_FlexSPI_CLK_SIGNAL FLEXSPI_A_SCLK /*!< FLEXSPI signal: FLEXSPI_A_SCLK */
/* GPIO_SD_B1_08 (number 23), SAI3_TXD */
#define BOARD_INITQSPIPINS_FlexSPI_D0_A_PERIPHERAL FLEXSPI /*!< Device name: FLEXSPI */
#define BOARD_INITQSPIPINS_FlexSPI_D0_A_SIGNAL FLEXSPI_A_DATA0 /*!< FLEXSPI signal: FLEXSPI_A_DATA0 */
/* GPIO_SD_B1_10 (number 21), SD_PWREN */
#define BOARD_INITQSPIPINS_FlexSPI_D1_A_PERIPHERAL FLEXSPI /*!< Device name: FLEXSPI */
#define BOARD_INITQSPIPINS_FlexSPI_D1_A_SIGNAL FLEXSPI_A_DATA1 /*!< FLEXSPI signal: FLEXSPI_A_DATA1 */
/* GPIO_SD_B1_09 (number 22), AUD_INT */
#define BOARD_INITQSPIPINS_FlexSPI_D2_A_PERIPHERAL FLEXSPI /*!< Device name: FLEXSPI */
#define BOARD_INITQSPIPINS_FlexSPI_D2_A_SIGNAL FLEXSPI_A_DATA2 /*!< FLEXSPI signal: FLEXSPI_A_DATA2 */
/* GPIO_SD_B1_06 (number 25), SAI3_TX_BCLK */
#define BOARD_INITQSPIPINS_FlexSPI_D3_A_PERIPHERAL FLEXSPI /*!< Device name: FLEXSPI */
#define BOARD_INITQSPIPINS_FlexSPI_D3_A_SIGNAL FLEXSPI_A_DATA3 /*!< FLEXSPI signal: FLEXSPI_A_DATA3 */
/* GPIO_SD_B1_11 (number 19), SAI3_RXD */
#define BOARD_INITQSPIPINS_FlexSPI_SS0_PERIPHERAL FLEXSPI /*!< Device name: FLEXSPI */
#define BOARD_INITQSPIPINS_FlexSPI_SS0_SIGNAL FLEXSPI_A_SS0_B /*!< FLEXSPI signal: FLEXSPI_A_SS0_B */
/*!
* @brief Configures pin routing and optionally pin electrical features.
*
*/
void BOARD_InitQSPIPins(void);
#if defined(__cplusplus)
}
#endif
/*!
* @}
*/
#endif /* _PIN_MUX_H_ */
/***********************************************************************************************************************
* EOF
**********************************************************************************************************************/

48
managed_components/espressif__tinyusb/hw/bsp/imxrt/boards/mimxrt1024_evk/evkmimxrt1024_flexspi_nor_config.c Normal file
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/*
* Copyright 2020 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "evkmimxrt1024_flexspi_nor_config.h"
/* Component ID definition, used by tools. */
#ifndef FSL_COMPONENT_ID
#define FSL_COMPONENT_ID "platform.drivers.xip_board"
#endif
/*******************************************************************************
* Code
******************************************************************************/
#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
__attribute__((section(".boot_hdr.conf"), used))
#elif defined(__ICCARM__)
#pragma location = ".boot_hdr.conf"
#endif
const flexspi_nor_config_t qspiflash_config = {
.memConfig =
{
.tag = FLEXSPI_CFG_BLK_TAG,
.version = FLEXSPI_CFG_BLK_VERSION,
.readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackInternally,
.csHoldTime = 3u,
.csSetupTime = 3u,
.sflashPadType = kSerialFlash_4Pads,
.serialClkFreq = kFlexSpiSerialClk_60MHz,
.sflashA1Size = 4u * 1024u * 1024u,
.lookupTable =
{
// Read LUTs
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18),
FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04),
},
},
.pageSize = 256u,
.sectorSize = 4u * 1024u,
.blockSize = 64u * 1024u,
.isUniformBlockSize = false,
};
#endif /* XIP_BOOT_HEADER_ENABLE */

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/*
* Copyright 2020 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __EVKMIMXRT1024_FLEXSPI_NOR_CONFIG__
#define __EVKMIMXRT1024_FLEXSPI_NOR_CONFIG__
#include <stdint.h>
#include <stdbool.h>
#include "fsl_common.h"
/*! @name Driver version */
/*@{*/
/*! @brief XIP_BOARD driver version 2.0.1. */
#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
/*@}*/
/* FLEXSPI memory config block related definitions */
#define FLEXSPI_CFG_BLK_TAG (0x42464346UL) // ascii "FCFB" Big Endian
#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0
#define FLEXSPI_CFG_BLK_SIZE (512)
/* FLEXSPI Feature related definitions */
#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1
/* Lookup table related definitions */
#define CMD_INDEX_READ 0
#define CMD_INDEX_READSTATUS 1
#define CMD_INDEX_WRITEENABLE 2
#define CMD_INDEX_WRITE 4
#define CMD_LUT_SEQ_IDX_READ 0
#define CMD_LUT_SEQ_IDX_READSTATUS 1
#define CMD_LUT_SEQ_IDX_WRITEENABLE 3
#define CMD_LUT_SEQ_IDX_WRITE 9
#define CMD_SDR 0x01
#define CMD_DDR 0x21
#define RADDR_SDR 0x02
#define RADDR_DDR 0x22
#define CADDR_SDR 0x03
#define CADDR_DDR 0x23
#define MODE1_SDR 0x04
#define MODE1_DDR 0x24
#define MODE2_SDR 0x05
#define MODE2_DDR 0x25
#define MODE4_SDR 0x06
#define MODE4_DDR 0x26
#define MODE8_SDR 0x07
#define MODE8_DDR 0x27
#define WRITE_SDR 0x08
#define WRITE_DDR 0x28
#define READ_SDR 0x09
#define READ_DDR 0x29
#define LEARN_SDR 0x0A
#define LEARN_DDR 0x2A
#define DATSZ_SDR 0x0B
#define DATSZ_DDR 0x2B
#define DUMMY_SDR 0x0C
#define DUMMY_DDR 0x2C
#define DUMMY_RWDS_SDR 0x0D
#define DUMMY_RWDS_DDR 0x2D
#define JMP_ON_CS 0x1F
#define STOP 0
#define FLEXSPI_1PAD 0
#define FLEXSPI_2PAD 1
#define FLEXSPI_4PAD 2
#define FLEXSPI_8PAD 3
#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \
(FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \
FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))
//!@brief Definitions for FlexSPI Serial Clock Frequency
typedef enum _FlexSpiSerialClockFreq
{
kFlexSpiSerialClk_30MHz = 1,
kFlexSpiSerialClk_50MHz = 2,
kFlexSpiSerialClk_60MHz = 3,
kFlexSpiSerialClk_75MHz = 4,
kFlexSpiSerialClk_80MHz = 5,
kFlexSpiSerialClk_100MHz = 6,
kFlexSpiSerialClk_133MHz = 7,
} flexspi_serial_clk_freq_t;
//!@brief FlexSPI clock configuration type
enum
{
kFlexSpiClk_SDR, //!< Clock configure for SDR mode
kFlexSpiClk_DDR, //!< Clock configurat for DDR mode
};
//!@brief FlexSPI Read Sample Clock Source definition
typedef enum _FlashReadSampleClkSource
{
kFlexSPIReadSampleClk_LoopbackInternally = 0,
kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1,
kFlexSPIReadSampleClk_LoopbackFromSckPad = 2,
kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3,
} flexspi_read_sample_clk_t;
//!@brief Misc feature bit definitions
enum
{
kFlexSpiMiscOffset_DiffClkEnable = 0, //!< Bit for Differential clock enable
kFlexSpiMiscOffset_Ck2Enable = 1, //!< Bit for CK2 enable
kFlexSpiMiscOffset_ParallelEnable = 2, //!< Bit for Parallel mode enable
kFlexSpiMiscOffset_WordAddressableEnable = 3, //!< Bit for Word Addressable enable
kFlexSpiMiscOffset_SafeConfigFreqEnable = 4, //!< Bit for Safe Configuration Frequency enable
kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, //!< Bit for Pad setting override enable
kFlexSpiMiscOffset_DdrModeEnable = 6, //!< Bit for DDR clock confiuration indication.
};
//!@brief Flash Type Definition
enum
{
kFlexSpiDeviceType_SerialNOR = 1, //!< Flash devices are Serial NOR
kFlexSpiDeviceType_SerialNAND = 2, //!< Flash devices are Serial NAND
kFlexSpiDeviceType_SerialRAM = 3, //!< Flash devices are Serial RAM/HyperFLASH
kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND
kFlexSpiDeviceType_MCP_NOR_RAM = 0x13, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial RAMs
};
//!@brief Flash Pad Definitions
enum
{
kSerialFlash_1Pad = 1,
kSerialFlash_2Pads = 2,
kSerialFlash_4Pads = 4,
kSerialFlash_8Pads = 8,
};
//!@brief FlexSPI LUT Sequence structure
typedef struct _lut_sequence
{
uint8_t seqNum; //!< Sequence Number, valid number: 1-16
uint8_t seqId; //!< Sequence Index, valid number: 0-15
uint16_t reserved;
} flexspi_lut_seq_t;
//!@brief Flash Configuration Command Type
enum
{
kDeviceConfigCmdType_Generic, //!< Generic command, for example: configure dummy cycles, drive strength, etc
kDeviceConfigCmdType_QuadEnable, //!< Quad Enable command
kDeviceConfigCmdType_Spi2Xpi, //!< Switch from SPI to DPI/QPI/OPI mode
kDeviceConfigCmdType_Xpi2Spi, //!< Switch from DPI/QPI/OPI to SPI mode
kDeviceConfigCmdType_Spi2NoCmd, //!< Switch to 0-4-4/0-8-8 mode
kDeviceConfigCmdType_Reset, //!< Reset device command
};
//!@brief FlexSPI Memory Configuration Block
typedef struct _FlexSPIConfig
{
uint32_t tag; //!< [0x000-0x003] Tag, fixed value 0x42464346UL
uint32_t version; //!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix
uint32_t reserved0; //!< [0x008-0x00b] Reserved for future use
uint8_t readSampleClkSrc; //!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3
uint8_t csHoldTime; //!< [0x00d-0x00d] CS hold time, default value: 3
uint8_t csSetupTime; //!< [0x00e-0x00e] CS setup time, default value: 3
uint8_t columnAddressWidth; //!< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For
//! Serial NAND, need to refer to datasheet
uint8_t deviceModeCfgEnable; //!< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable
uint8_t deviceModeType; //!< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch,
//! Generic configuration, etc.
uint16_t waitTimeCfgCommands; //!< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for
//! DPI/QPI/OPI switch or reset command
flexspi_lut_seq_t deviceModeSeq; //!< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt
//! sequence number, [31:16] Reserved
uint32_t deviceModeArg; //!< [0x018-0x01b] Argument/Parameter for device configuration
uint8_t configCmdEnable; //!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable
uint8_t configModeType[3]; //!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe
flexspi_lut_seq_t
configCmdSeqs[3]; //!< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq
uint32_t reserved1; //!< [0x02c-0x02f] Reserved for future use
uint32_t configCmdArgs[3]; //!< [0x030-0x03b] Arguments/Parameters for device Configuration commands
uint32_t reserved2; //!< [0x03c-0x03f] Reserved for future use
uint32_t controllerMiscOption; //!< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more
//! details
uint8_t deviceType; //!< [0x044-0x044] Device Type: See Flash Type Definition for more details
uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal
uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequency, device specific definitions, See System Boot
//! Chapter for more details
uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot
//! be done using 1 LUT sequence, currently, only applicable to HyperFLASH
uint32_t reserved3[2]; //!< [0x048-0x04f] Reserved for future use
uint32_t sflashA1Size; //!< [0x050-0x053] Size of Flash connected to A1
uint32_t sflashA2Size; //!< [0x054-0x057] Size of Flash connected to A2
uint32_t sflashB1Size; //!< [0x058-0x05b] Size of Flash connected to B1
uint32_t sflashB2Size; //!< [0x05c-0x05f] Size of Flash connected to B2
uint32_t csPadSettingOverride; //!< [0x060-0x063] CS pad setting override value
uint32_t sclkPadSettingOverride; //!< [0x064-0x067] SCK pad setting override value
uint32_t dataPadSettingOverride; //!< [0x068-0x06b] data pad setting override value
uint32_t dqsPadSettingOverride; //!< [0x06c-0x06f] DQS pad setting override value
uint32_t timeoutInMs; //!< [0x070-0x073] Timeout threshold for read status command
uint32_t commandInterval; //!< [0x074-0x077] CS deselect interval between two commands
uint16_t dataValidTime[2]; //!< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns
uint16_t busyOffset; //!< [0x07c-0x07d] Busy offset, valid value: 0-31
uint16_t busyBitPolarity; //!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 -
//! busy flag is 0 when flash device is busy
uint32_t lookupTable[64]; //!< [0x080-0x17f] Lookup table holds Flash command sequences
flexspi_lut_seq_t lutCustomSeq[12]; //!< [0x180-0x1af] Customizable LUT Sequences
uint32_t reserved4[4]; //!< [0x1b0-0x1bf] Reserved for future use
} flexspi_mem_config_t;
/* */
#define NOR_CMD_INDEX_READ CMD_INDEX_READ //!< 0
#define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS //!< 1
#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE //!< 2
#define NOR_CMD_INDEX_ERASESECTOR 3 //!< 3
#define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE //!< 4
#define NOR_CMD_INDEX_CHIPERASE 5 //!< 5
#define NOR_CMD_INDEX_DUMMY 6 //!< 6
#define NOR_CMD_INDEX_ERASEBLOCK 7 //!< 7
#define NOR_CMD_LUT_SEQ_IDX_READ CMD_LUT_SEQ_IDX_READ //!< 0 READ LUT sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_READSTATUS \
CMD_LUT_SEQ_IDX_READSTATUS //!< 1 Read Status LUT sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \
2 //!< 2 Read status DPI/QPI/OPI sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE \
CMD_LUT_SEQ_IDX_WRITEENABLE //!< 3 Write Enable sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \
4 //!< 4 Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5 //!< 5 Erase Sector sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8 //!< 8 Erase Block sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM \
CMD_LUT_SEQ_IDX_WRITE //!< 9 Program sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11 //!< 11 Chip Erase sequence in lookupTable id stored in config block
#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13 //!< 13 Read SFDP sequence in lookupTable id stored in config block
#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \
14 //!< 14 Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \
15 //!< 15 Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config blobk
/*
* Serial NOR configuration block
*/
typedef struct _flexspi_nor_config
{
flexspi_mem_config_t memConfig; //!< Common memory configuration info via FlexSPI
uint32_t pageSize; //!< Page size of Serial NOR
uint32_t sectorSize; //!< Sector size of Serial NOR
uint8_t ipcmdSerialClkFreq; //!< Clock frequency for IP command
uint8_t isUniformBlockSize; //!< Sector/Block size is the same
uint8_t reserved0[2]; //!< Reserved for future use
uint8_t serialNorType; //!< Serial NOR Flash type: 0/1/2/3
uint8_t needExitNoCmdMode; //!< Need to exit NoCmd mode before other IP command
uint8_t halfClkForNonReadCmd; //!< Half the Serial Clock for non-read command: true/false
uint8_t needRestoreNoCmdMode; //!< Need to Restore NoCmd mode after IP command execution
uint32_t blockSize; //!< Block size
uint32_t reserve2[11]; //!< Reserved for future use
} flexspi_nor_config_t;
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __cplusplus
}
#endif
#endif /* __EVKMIMXRT1024_FLEXSPI_NOR_CONFIG__ */

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<?xml version="1.0" encoding= "UTF-8" ?>
<configuration name="MIMXRT1024-EVK" xsi:schemaLocation="http://mcuxpresso.nxp.com/XSD/mex_configuration_13 http://mcuxpresso.nxp.com/XSD/mex_configuration_13.xsd" uuid="a558cc6e-82c2-41f9-9f55-0348efc7896f" version="13" xmlns="http://mcuxpresso.nxp.com/XSD/mex_configuration_13" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<common>
<processor>MIMXRT1024xxxxx</processor>
<package>MIMXRT1024DAG5A</package>
<board>MIMXRT1024-EVK</board>
<board_revision>B1</board_revision>
<mcu_data>ksdk2_0</mcu_data>
<cores selected="core0">
<core name="Cortex-M7F" id="core0" description="M7 core"/>
</cores>
<description></description>
</common>
<preferences>
<validate_boot_init_only>false</validate_boot_init_only>
<generate_extended_information>false</generate_extended_information>
<generate_code_modified_registers_only>false</generate_code_modified_registers_only>
<update_include_paths>true</update_include_paths>
<generate_registers_defines>false</generate_registers_defines>
</preferences>
<tools>
<pins name="Pins" version="13.1" enabled="true" update_project_code="true">
<generated_project_files>
<file path="board/pin_mux.c" update_enabled="true"/>
<file path="board/pin_mux.h" update_enabled="true"/>
</generated_project_files>
<pins_profile>
<processor_version>13.0.2</processor_version>
<pin_labels>
<pin_label pin_num="52" pin_signal="WAKEUP" label="USER_BUTTON" identifier="USER_BUTTON"/>
<pin_label pin_num="82" pin_signal="GPIO_AD_B1_08" label="UART_TX/USER_LED/J17[4]" identifier="USER_LED"/>
</pin_labels>
<power_domains>
<power_domain name="NVCC_GPIO" value="3.3"/>
</power_domains>
</pins_profile>
<functions_list>
<function name="BOARD_InitPins">
<description>Configures pin routing and optionally pin electrical features.</description>
<options>
<callFromInitBoot>true</callFromInitBoot>
<coreID>core0</coreID>
<enableClock>true</enableClock>
</options>
<dependencies>
<dependency resourceType="Peripheral" resourceId="GPIO5" description="Peripheral GPIO5 is not initialized" problem_level="1" source="Pins:BOARD_InitPins">
<feature name="initialized" evaluation="equal">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitPins">
<feature name="enabled" evaluation="equal" configuration="core0">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitPins">
<feature name="enabled" evaluation="equal" configuration="core0">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.igpio" description="Pins initialization requires the IGPIO Driver in the project." problem_level="2" source="Pins:BOARD_InitPins">
<feature name="enabled" evaluation="equal" configuration="core0">
<data>true</data>
</feature>
</dependency>
</dependencies>
<pins>
<pin peripheral="GPIO5" signal="gpio_io, 00" pin_num="52" pin_signal="WAKEUP">
<pin_features>
<pin_feature name="direction" value="INPUT"/>
</pin_features>
</pin>
<pin peripheral="GPIO1" signal="gpio_io, 24" pin_num="82" pin_signal="GPIO_AD_B1_08">
<pin_features>
<pin_feature name="direction" value="OUTPUT"/>
</pin_features>
</pin>
</pins>
</function>
<function name="BOARD_InitDEBUG_UARTPins">
<description>Configures pin routing and optionally pin electrical features.</description>
<options>
<callFromInitBoot>true</callFromInitBoot>
<coreID>core0</coreID>
<enableClock>true</enableClock>
</options>
<dependencies>
<dependency resourceType="Peripheral" resourceId="LPUART1" description="Peripheral LPUART1 is not initialized" problem_level="1" source="Pins:BOARD_InitDEBUG_UARTPins">
<feature name="initialized" evaluation="equal">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitDEBUG_UARTPins">
<feature name="enabled" evaluation="equal" configuration="core0">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitDEBUG_UARTPins">
<feature name="enabled" evaluation="equal" configuration="core0">
<data>true</data>
</feature>
</dependency>
</dependencies>
<pins>
<pin peripheral="LPUART1" signal="RX" pin_num="101" pin_signal="GPIO_AD_B0_07"/>
<pin peripheral="LPUART1" signal="TX" pin_num="105" pin_signal="GPIO_AD_B0_06"/>
</pins>
</function>
<function name="BOARD_InitSDRAMPins">
<description>Configures pin routing and optionally pin electrical features.</description>
<options>
<coreID>core0</coreID>
<enableClock>true</enableClock>
</options>
<dependencies>
<dependency resourceType="Peripheral" resourceId="SEMC" description="Peripheral SEMC is not initialized" problem_level="1" source="Pins:BOARD_InitSDRAMPins">
<feature name="initialized" evaluation="equal">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitSDRAMPins">
<feature name="enabled" evaluation="equal" configuration="core0">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitSDRAMPins">
<feature name="enabled" evaluation="equal" configuration="core0">
<data>true</data>
</feature>
</dependency>
</dependencies>
<pins>
<pin peripheral="SEMC" signal="ADDR, 00" pin_num="142" pin_signal="GPIO_EMC_16"/>
<pin peripheral="SEMC" signal="ADDR, 01" pin_num="141" pin_signal="GPIO_EMC_17"/>
<pin peripheral="SEMC" signal="ADDR, 02" pin_num="140" pin_signal="GPIO_EMC_18"/>
<pin peripheral="SEMC" signal="ADDR, 03" pin_num="139" pin_signal="GPIO_EMC_19"/>
<pin peripheral="SEMC" signal="ADDR, 04" pin_num="138" pin_signal="GPIO_EMC_20"/>
<pin peripheral="SEMC" signal="ADDR, 06" pin_num="136" pin_signal="GPIO_EMC_22"/>
<pin peripheral="SEMC" signal="ADDR, 05" pin_num="137" pin_signal="GPIO_EMC_21"/>
<pin peripheral="SEMC" signal="ADDR, 07" pin_num="133" pin_signal="GPIO_EMC_23"/>
<pin peripheral="SEMC" signal="ADDR, 08" pin_num="132" pin_signal="GPIO_EMC_24"/>
<pin peripheral="SEMC" signal="ADDR, 09" pin_num="131" pin_signal="GPIO_EMC_25"/>
<pin peripheral="SEMC" signal="ADDR, 10" pin_num="143" pin_signal="GPIO_EMC_15"/>
<pin peripheral="SEMC" signal="ADDR, 11" pin_num="130" pin_signal="GPIO_EMC_26"/>
<pin peripheral="SEMC" signal="ADDR, 12" pin_num="129" pin_signal="GPIO_EMC_27"/>
<pin peripheral="SEMC" signal="BA, 0" pin_num="2" pin_signal="GPIO_EMC_13"/>
<pin peripheral="SEMC" signal="BA, 1" pin_num="1" pin_signal="GPIO_EMC_14"/>
<pin peripheral="SEMC" signal="semc_cas" pin_num="7" pin_signal="GPIO_EMC_10"/>
<pin peripheral="SEMC" signal="semc_cke" pin_num="127" pin_signal="GPIO_EMC_29"/>
<pin peripheral="SEMC" signal="semc_clk" pin_num="126" pin_signal="GPIO_EMC_30"/>
<pin peripheral="SEMC" signal="CS, 0" pin_num="3" pin_signal="GPIO_EMC_12"/>
<pin peripheral="SEMC" signal="semc_we" pin_num="8" pin_signal="GPIO_EMC_09"/>
<pin peripheral="SEMC" signal="semc_ras" pin_num="4" pin_signal="GPIO_EMC_11"/>
<pin peripheral="SEMC" signal="semc_dqs" pin_num="128" pin_signal="GPIO_EMC_28"/>
<pin peripheral="SEMC" signal="DM, 1" pin_num="125" pin_signal="GPIO_EMC_31"/>
<pin peripheral="SEMC" signal="DM, 0" pin_num="9" pin_signal="GPIO_EMC_08"/>
<pin peripheral="SEMC" signal="DATA, 15" pin_num="117" pin_signal="GPIO_EMC_39"/>
<pin peripheral="SEMC" signal="DATA, 14" pin_num="118" pin_signal="GPIO_EMC_38"/>
<pin peripheral="SEMC" signal="DATA, 13" pin_num="119" pin_signal="GPIO_EMC_37"/>
<pin peripheral="SEMC" signal="DATA, 12" pin_num="120" pin_signal="GPIO_EMC_36"/>
<pin peripheral="SEMC" signal="DATA, 10" pin_num="122" pin_signal="GPIO_EMC_34"/>
<pin peripheral="SEMC" signal="DATA, 11" pin_num="121" pin_signal="GPIO_EMC_35"/>
<pin peripheral="SEMC" signal="DATA, 09" pin_num="123" pin_signal="GPIO_EMC_33"/>
<pin peripheral="SEMC" signal="DATA, 08" pin_num="124" pin_signal="GPIO_EMC_32"/>
<pin peripheral="SEMC" signal="DATA, 07" pin_num="10" pin_signal="GPIO_EMC_07"/>
<pin peripheral="SEMC" signal="DATA, 06" pin_num="12" pin_signal="GPIO_EMC_06"/>
<pin peripheral="SEMC" signal="DATA, 05" pin_num="13" pin_signal="GPIO_EMC_05"/>
<pin peripheral="SEMC" signal="DATA, 04" pin_num="14" pin_signal="GPIO_EMC_04"/>
<pin peripheral="SEMC" signal="DATA, 03" pin_num="15" pin_signal="GPIO_EMC_03"/>
<pin peripheral="SEMC" signal="DATA, 02" pin_num="16" pin_signal="GPIO_EMC_02"/>
<pin peripheral="SEMC" signal="DATA, 01" pin_num="17" pin_signal="GPIO_EMC_01"/>
<pin peripheral="SEMC" signal="DATA, 00" pin_num="18" pin_signal="GPIO_EMC_00"/>
</pins>
</function>
<function name="BOARD_InitCANPins">
<description>Configures pin routing and optionally pin electrical features.</description>
<options>
<coreID>core0</coreID>
<enableClock>true</enableClock>
</options>
<dependencies>
<dependency resourceType="Peripheral" resourceId="CAN1" description="Peripheral CAN1 is not initialized" problem_level="1" source="Pins:BOARD_InitCANPins">
<feature name="initialized" evaluation="equal">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitCANPins">
<feature name="enabled" evaluation="equal" configuration="core0">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitCANPins">
<feature name="enabled" evaluation="equal" configuration="core0">
<data>true</data>
</feature>
</dependency>
</dependencies>
<pins>
<pin peripheral="CAN1" signal="RX" pin_num="32" pin_signal="GPIO_SD_B1_01"/>
<pin peripheral="CAN1" signal="TX" pin_num="33" pin_signal="GPIO_SD_B1_00"/>
</pins>
</function>
<function name="BOARD_InitENETPins">
<description>Configures pin routing and optionally pin electrical features.</description>
<options>
<coreID>core0</coreID>
<enableClock>true</enableClock>
</options>
<dependencies>
<dependency resourceType="Peripheral" resourceId="ENET" description="Peripheral ENET is not initialized" problem_level="1" source="Pins:BOARD_InitENETPins">
<feature name="initialized" evaluation="equal">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitENETPins">
<feature name="enabled" evaluation="equal" configuration="core0">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitENETPins">
<feature name="enabled" evaluation="equal" configuration="core0">
<data>true</data>
</feature>
</dependency>
</dependencies>
<pins>
<pin peripheral="ENET" signal="enet_rx_en" pin_num="97" pin_signal="GPIO_AD_B0_11"/>
<pin peripheral="GPIO1" signal="gpio_io, 22" pin_num="84" pin_signal="GPIO_AD_B1_06"/>
<pin peripheral="GPIO1" signal="gpio_io, 04" pin_num="107" pin_signal="GPIO_AD_B0_04"/>
<pin peripheral="ENET" signal="enet_tx_clk" pin_num="100" pin_signal="GPIO_AD_B0_08"/>
<pin peripheral="ENET" signal="enet_tx_en" pin_num="95" pin_signal="GPIO_AD_B0_13"/>
<pin peripheral="ENET" signal="enet_tx_data, 1" pin_num="93" pin_signal="GPIO_AD_B0_15"/>
<pin peripheral="ENET" signal="enet_tx_data, 0" pin_num="94" pin_signal="GPIO_AD_B0_14"/>
<pin peripheral="ENET" signal="enet_rx_er" pin_num="96" pin_signal="GPIO_AD_B0_12"/>
<pin peripheral="ENET" signal="enet_rx_data, 1" pin_num="99" pin_signal="GPIO_AD_B0_09"/>
<pin peripheral="ENET" signal="enet_rx_data, 0" pin_num="98" pin_signal="GPIO_AD_B0_10"/>
<pin peripheral="ENET" signal="enet_mdio" pin_num="116" pin_signal="GPIO_EMC_40"/>
<pin peripheral="ENET" signal="enet_mdc" pin_num="115" pin_signal="GPIO_EMC_41"/>
</pins>
</function>
<function name="BOARD_InitUSDHCPins">
<description>Configures pin routing and optionally pin electrical features.</description>
<options>
<coreID>core0</coreID>
<enableClock>true</enableClock>
</options>
<dependencies>
<dependency resourceType="Peripheral" resourceId="USDHC1" description="Peripheral USDHC1 is not initialized" problem_level="1" source="Pins:BOARD_InitUSDHCPins">
<feature name="initialized" evaluation="equal">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitUSDHCPins">
<feature name="enabled" evaluation="equal" configuration="core0">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitUSDHCPins">
<feature name="enabled" evaluation="equal" configuration="core0">
<data>true</data>
</feature>
</dependency>
</dependencies>
<pins>
<pin peripheral="USDHC1" signal="usdhc_clk" pin_num="45" pin_signal="GPIO_SD_B0_03"/>
<pin peripheral="USDHC1" signal="usdhc_cmd" pin_num="46" pin_signal="GPIO_SD_B0_02"/>
<pin peripheral="USDHC1" signal="usdhc_data, 0" pin_num="43" pin_signal="GPIO_SD_B0_04"/>
<pin peripheral="USDHC1" signal="usdhc_data, 1" pin_num="42" pin_signal="GPIO_SD_B0_05"/>
<pin peripheral="USDHC1" signal="usdhc_data, 2" pin_num="48" pin_signal="GPIO_SD_B0_00"/>
<pin peripheral="USDHC1" signal="usdhc_data, 3" pin_num="47" pin_signal="GPIO_SD_B0_01"/>
<pin peripheral="GPIO3" signal="gpio_io, 19" pin_num="41" pin_signal="GPIO_SD_B0_06"/>
</pins>
</function>
<function name="BOARD_InitQSPIPins">
<description>Configures pin routing and optionally pin electrical features.</description>
<options>
<coreID>core0</coreID>
<enableClock>true</enableClock>
</options>
<dependencies>
<dependency resourceType="Peripheral" resourceId="FLEXSPI" description="Peripheral FLEXSPI is not initialized" problem_level="1" source="Pins:BOARD_InitQSPIPins">
<feature name="initialized" evaluation="equal">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitQSPIPins">
<feature name="enabled" evaluation="equal" configuration="core0">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitQSPIPins">
<feature name="enabled" evaluation="equal" configuration="core0">
<data>true</data>
</feature>
</dependency>
</dependencies>
<pins>
<pin peripheral="FLEXSPI" signal="FLEXSPI_A_SCLK" pin_num="24" pin_signal="GPIO_SD_B1_07"/>
<pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA0" pin_num="23" pin_signal="GPIO_SD_B1_08"/>
<pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA1" pin_num="21" pin_signal="GPIO_SD_B1_10"/>
<pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA2" pin_num="22" pin_signal="GPIO_SD_B1_09"/>
<pin peripheral="FLEXSPI" signal="FLEXSPI_A_DATA3" pin_num="25" pin_signal="GPIO_SD_B1_06"/>
<pin peripheral="FLEXSPI" signal="FLEXSPI_A_SS0_B" pin_num="19" pin_signal="GPIO_SD_B1_11"/>
</pins>
</function>
</functions_list>
</pins>
<clocks name="Clocks" version="11.0" enabled="true" update_project_code="true">
<generated_project_files>
<file path="board/clock_config.c" update_enabled="true"/>
<file path="board/clock_config.h" update_enabled="true"/>
</generated_project_files>
<clocks_profile>
<processor_version>13.0.2</processor_version>
</clocks_profile>
<clock_configurations>
<clock_configuration name="BOARD_BootClockRUN" id_prefix="" prefix_user_defined="false">
<description></description>
<options/>
<dependencies>
<dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtali" description="&apos;RTC_XTALI&apos; (Pins tool id: XTALOSC24M.rtc_xtali, Clocks tool id: XTALOSC24M.RTC_XTALI) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
<feature name="routed" evaluation="">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtali" description="&apos;RTC_XTALI&apos; (Pins tool id: XTALOSC24M.rtc_xtali, Clocks tool id: XTALOSC24M.RTC_XTALI) needs to have &apos;INPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
<feature name="direction" evaluation="">
<data>INPUT</data>
</feature>
</dependency>
<dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtalo" description="&apos;RTC_XTALO&apos; (Pins tool id: XTALOSC24M.rtc_xtalo, Clocks tool id: XTALOSC24M.RTC_XTALO) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
<feature name="routed" evaluation="">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtalo" description="&apos;RTC_XTALO&apos; (Pins tool id: XTALOSC24M.rtc_xtalo, Clocks tool id: XTALOSC24M.RTC_XTALO) needs to have &apos;OUTPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
<feature name="direction" evaluation="">
<data>OUTPUT</data>
</feature>
</dependency>
<dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtali" description="&apos;XTALI&apos; (Pins tool id: XTALOSC24M.xtali, Clocks tool id: XTALOSC24M.XTALI) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
<feature name="routed" evaluation="">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtali" description="&apos;XTALI&apos; (Pins tool id: XTALOSC24M.xtali, Clocks tool id: XTALOSC24M.XTALI) needs to have &apos;INPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
<feature name="direction" evaluation="">
<data>INPUT</data>
</feature>
</dependency>
<dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtalo" description="&apos;XTALO&apos; (Pins tool id: XTALOSC24M.xtalo, Clocks tool id: XTALOSC24M.XTALO) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
<feature name="routed" evaluation="">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtalo" description="&apos;XTALO&apos; (Pins tool id: XTALOSC24M.xtalo, Clocks tool id: XTALOSC24M.XTALO) needs to have &apos;OUTPUT&apos; direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
<feature name="direction" evaluation="">
<data>OUTPUT</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN">
<feature name="enabled" evaluation="equal" configuration="core0">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Clocks initialization requires the IOMUXC Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN">
<feature name="enabled" evaluation="equal" configuration="core0">
<data>true</data>
</feature>
</dependency>
</dependencies>
<clock_sources>
<clock_source id="XTALOSC24M.RTC_OSC.outFreq" value="32.768 kHz" locked="false" enabled="true"/>
</clock_sources>
<clock_outputs>
<clock_output id="AHB_CLK_ROOT.outFreq" value="500 MHz" locked="false" accuracy=""/>
<clock_output id="CAN_CLK_ROOT.outFreq" value="40 MHz" locked="false" accuracy=""/>
<clock_output id="CKIL_SYNC_CLK_ROOT.outFreq" value="32.768 kHz" locked="false" accuracy=""/>
<clock_output id="CLK_1M.outFreq" value="1 MHz" locked="false" accuracy=""/>
<clock_output id="CLK_24M.outFreq" value="24 MHz" locked="false" accuracy=""/>
<clock_output id="ENET_500M_REF_CLK.outFreq" value="500 MHz" locked="false" accuracy=""/>
<clock_output id="FLEXIO1_CLK_ROOT.outFreq" value="30 MHz" locked="false" accuracy=""/>
<clock_output id="FLEXSPI_CLK_ROOT.outFreq" value="132 MHz" locked="false" accuracy=""/>
<clock_output id="GPT1_ipg_clk_highfreq.outFreq" value="62.5 MHz" locked="false" accuracy=""/>
<clock_output id="GPT2_ipg_clk_highfreq.outFreq" value="62.5 MHz" locked="false" accuracy=""/>
<clock_output id="IPG_CLK_ROOT.outFreq" value="125 MHz" locked="false" accuracy=""/>
<clock_output id="LPI2C_CLK_ROOT.outFreq" value="60 MHz" locked="false" accuracy=""/>
<clock_output id="LPSPI_CLK_ROOT.outFreq" value="105.6 MHz" locked="false" accuracy=""/>
<clock_output id="MQS_MCLK.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
<clock_output id="PERCLK_CLK_ROOT.outFreq" value="62.5 MHz" locked="false" accuracy=""/>
<clock_output id="SAI1_CLK_ROOT.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
<clock_output id="SAI1_MCLK1.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
<clock_output id="SAI1_MCLK2.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
<clock_output id="SAI1_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/>
<clock_output id="SAI2_CLK_ROOT.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
<clock_output id="SAI2_MCLK1.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
<clock_output id="SAI2_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/>
<clock_output id="SAI3_CLK_ROOT.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
<clock_output id="SAI3_MCLK1.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
<clock_output id="SAI3_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/>
<clock_output id="SEMC_CLK_ROOT.outFreq" value="62.5 MHz" locked="false" accuracy=""/>
<clock_output id="SPDIF0_CLK_ROOT.outFreq" value="30 MHz" locked="false" accuracy=""/>
<clock_output id="TRACE_CLK_ROOT.outFreq" value="132 MHz" locked="false" accuracy=""/>
<clock_output id="UART_CLK_ROOT.outFreq" value="80 MHz" locked="false" accuracy=""/>
<clock_output id="USBPHY1_CLK.outFreq" value="480 MHz" locked="false" accuracy=""/>
<clock_output id="USDHC1_CLK_ROOT.outFreq" value="176 MHz" locked="false" accuracy=""/>
<clock_output id="USDHC2_CLK_ROOT.outFreq" value="176 MHz" locked="false" accuracy=""/>
</clock_outputs>
<clock_settings>
<setting id="CCM.AHB_PODF.scale" value="1" locked="true"/>
<setting id="CCM.ARM_PODF.scale" value="1" locked="true"/>
<setting id="CCM.FLEXSPI_PODF.scale" value="4" locked="true"/>
<setting id="CCM.FLEXSPI_SEL.sel" value="CCM_ANALOG.PLL2_PFD2_CLK" locked="false"/>
<setting id="CCM.IPG_PODF.scale" value="4" locked="false"/>
<setting id="CCM.LPSPI_PODF.scale" value="5" locked="true"/>
<setting id="CCM.PERCLK_PODF.scale" value="2" locked="true"/>
<setting id="CCM.PRE_PERIPH_CLK_SEL.sel" value="CCM.ARM_PODF" locked="false"/>
<setting id="CCM.SEMC_PODF.scale" value="8" locked="false"/>
<setting id="CCM.TRACE_CLK_SEL.sel" value="CCM_ANALOG.PLL2_MAIN_CLK" locked="false"/>
<setting id="CCM.TRACE_PODF.scale" value="4" locked="true"/>
<setting id="CCM.USDHC1_PODF.scale" value="3" locked="true"/>
<setting id="CCM.USDHC2_PODF.scale" value="3" locked="true"/>
<setting id="CCM_ANALOG.PLL2.denom" value="1" locked="true"/>
<setting id="CCM_ANALOG.PLL2.num" value="0" locked="true"/>
<setting id="CCM_ANALOG.PLL2_BYPASS.sel" value="CCM_ANALOG.PLL2_OUT_CLK" locked="false"/>
<setting id="CCM_ANALOG.PLL2_PFD0_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD0" locked="false"/>
<setting id="CCM_ANALOG.PLL2_PFD1_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD1" locked="false"/>
<setting id="CCM_ANALOG.PLL2_PFD2_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD2" locked="false"/>
<setting id="CCM_ANALOG.PLL2_PFD2_DIV.scale" value="18" locked="true"/>
<setting id="CCM_ANALOG.PLL2_PFD2_MUL.scale" value="18" locked="true"/>
<setting id="CCM_ANALOG.PLL2_PFD3_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD3" locked="false"/>
<setting id="CCM_ANALOG.PLL2_PFD3_DIV.scale" value="18" locked="true"/>
<setting id="CCM_ANALOG.PLL2_PFD3_MUL.scale" value="18" locked="true"/>
<setting id="CCM_ANALOG.PLL3_BYPASS.sel" value="CCM_ANALOG.PLL3" locked="false"/>
<setting id="CCM_ANALOG.PLL3_PFD0_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD0" locked="false"/>
<setting id="CCM_ANALOG.PLL3_PFD0_DIV.scale" value="22" locked="true"/>
<setting id="CCM_ANALOG.PLL3_PFD0_MUL.scale" value="18" locked="true"/>
<setting id="CCM_ANALOG.PLL3_PFD1_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD1" locked="false"/>
<setting id="CCM_ANALOG.PLL3_PFD2_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD2" locked="false"/>
<setting id="CCM_ANALOG.PLL3_PFD3_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD3" locked="false"/>
<setting id="CCM_ANALOG.PLL3_PFD3_DIV.scale" value="18" locked="true"/>
<setting id="CCM_ANALOG.PLL3_PFD3_MUL.scale" value="18" locked="true"/>
<setting id="CCM_ANALOG.PLL4.denom" value="50" locked="false"/>
<setting id="CCM_ANALOG.PLL4.div" value="47" locked="false"/>
<setting id="CCM_ANALOG.PLL6_BYPASS.sel" value="CCM_ANALOG.PLL6" locked="false"/>
<setting id="CCM_ANALOG_PLL_ENET_ENABLE_CFG" value="Disabled" locked="false"/>
<setting id="CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_CFG" value="Disabled" locked="false"/>
<setting id="CCM_ANALOG_PLL_USB1_EN_USB_CLKS_CFG" value="Enabled" locked="false"/>
<setting id="CCM_ANALOG_PLL_USB1_EN_USB_CLKS_OUT_CFG" value="Enabled" locked="false"/>
<setting id="CCM_ANALOG_PLL_USB1_POWER_CFG" value="Yes" locked="false"/>
</clock_settings>
<called_from_default_init>true</called_from_default_init>
</clock_configuration>
</clock_configurations>
</clocks>
<dcdx name="DCDx" version="3.0" enabled="false" update_project_code="true">
<generated_project_files/>
<dcdx_profile>
<processor_version>13.0.2</processor_version>
<output_format>c_array</output_format>
</dcdx_profile>
<dcdx_configurations>
<dcdx_configuration name="Device_configuration">
<description></description>
<options/>
<command_groups/>
</dcdx_configuration>
</dcdx_configurations>
</dcdx>
<periphs name="Peripherals" version="12.0" enabled="false" update_project_code="true">
<generated_project_files/>
<peripherals_profile>
<processor_version>13.0.2</processor_version>
</peripherals_profile>
<functional_groups>
<functional_group name="BOARD_InitPeripherals" uuid="6d394465-bc9b-47f2-9a1f-3ca61f76d27b" called_from_default_init="true" id_prefix="" core="core0">
<description></description>
<options/>
<dependencies/>
<instances>
<instance name="NVIC" uuid="096e7e36-6917-481a-a4c5-06822cfc2da4" type="nvic" type_id="nvic_57b5eef3774cc60acaede6f5b8bddc67" mode="general" peripheral="NVIC" enabled="true" comment="" custom_name_enabled="false" editing_lock="false">
<config_set name="nvic">
<array name="interrupt_table"/>
<array name="interrupts"/>
</config_set>
</instance>
</instances>
</functional_group>
</functional_groups>
<components>
<component name="system" uuid="5dc935cc-5865-4d50-bac9-89ad440a12ee" type_id="system_54b53072540eeeb8f8e9343e71f28176">
<config_set_global name="global_system_definitions">
<setting name="user_definitions" value=""/>
<setting name="user_includes" value=""/>
</config_set_global>
</component>
<component name="msg" uuid="c2fe99b8-bf9b-437f-9446-a35000b06679" type_id="msg_6e2baaf3b97dbeef01c0043275f9a0e7">
<config_set_global name="global_messages"/>
</component>
<component name="generic_uart" uuid="eca93ea1-cadf-4247-bfdc-08769ef8ed12" type_id="generic_uart_8cae00565451cf2346eb1b8c624e73a6">
<config_set_global name="global_uart"/>
</component>
<component name="generic_can" uuid="fdf82c69-a73f-4f32-9699-457260453bc6" type_id="generic_can_1bfdd78b1af214566c1f23cf6a582d80">
<config_set_global name="global_can"/>
</component>
<component name="gpio_adapter_common" uuid="af80d7a8-d163-4a6f-839d-0ce2b15abffd" type_id="gpio_adapter_common_57579b9ac814fe26bf95df0a384c36b6">
<config_set_global name="global_gpio_adapter_common" quick_selection="default"/>
</component>
<component name="uart_cmsis_common" uuid="dca6ee55-a78d-4884-99bd-4f821b552213" type_id="uart_cmsis_common_9cb8e302497aa696fdbb5a4fd622c2a8">
<config_set_global name="global_USART_CMSIS_common" quick_selection="default"/>
</component>
<component name="generic_enet" uuid="4c34638b-b184-4e9d-8a81-5f3a1287180a" type_id="generic_enet_74db5c914f0ddbe47d86af40cb77a619">
<config_set_global name="global_enet"/>
</component>
</components>
</periphs>
<tee name="TEE" version="4.0" enabled="false" update_project_code="true">
<generated_project_files/>
<tee_profile>
<processor_version>N/A</processor_version>
</tee_profile>
</tee>
<common name="common" version="1.0" enabled="true" update_project_code="true">
<core name="core0" role="primary" project_name="Project"/>
</common>
</tools>
</configuration>

16
managed_components/espressif__tinyusb/hw/bsp/imxrt/boards/mimxrt1050_evkb/board.cmake Normal file
View File

@@ -0,0 +1,16 @@
set(MCU_VARIANT MIMXRT1052)
set(JLINK_DEVICE MIMXRT1052xxxxB)
set(PYOCD_TARGET mimxrt1050)
set(NXPLINK_DEVICE MIMXRT1052xxxxB:EVK-MIMXRT1050)
function(update_board TARGET)
target_sources(${TARGET} PUBLIC
${CMAKE_CURRENT_FUNCTION_LIST_DIR}/evkbimxrt1050_flexspi_nor_config.c
)
target_compile_definitions(${TARGET} PUBLIC
CPU_MIMXRT1052DVL6B
BOARD_TUD_RHPORT=0
BOARD_TUH_RHPORT=1
)
endfunction()

55
managed_components/espressif__tinyusb/hw/bsp/imxrt/boards/mimxrt1050_evkb/board.h Normal file
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/*
* The MIT License (MIT)
*
* Copyright (c) 2019, Ha Thach (tinyusb.org)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* This file is part of the TinyUSB stack.
*/
/* metadata:
name: i.MX RT1050 Evaluation Kit revB
url: https://www.nxp.com/part/IMXRT1050-EVKB
*/
#ifndef BOARD_MIMXRT1050_EVKB_H_
#define BOARD_MIMXRT1050_EVKB_H_
// required since iMXRT MCUX-SDK include this file for board size
#define BOARD_FLASH_SIZE (0x4000000U)
// LED: IOMUXC_GPIO_AD_B0_09_GPIO1_IO09
#define LED_PORT BOARD_INITPINS_USER_LED_PERIPHERAL
#define LED_PIN BOARD_INITPINS_USER_LED_CHANNEL
#define LED_STATE_ON 0
// SW8 button: IOMUXC_SNVS_WAKEUP_GPIO5_IO00
#define BUTTON_PORT BOARD_INITPINS_USER_BUTTON_PERIPHERAL
#define BUTTON_PIN BOARD_INITPINS_USER_BUTTON_CHANNEL
#define BUTTON_STATE_ACTIVE 0
// UART: IOMUXC_GPIO_AD_B0_13_LPUART1_RXD, IOMUXC_GPIO_AD_B0_12_LPUART1_TXD
#define UART_PORT LPUART1
#define UART_CLK_ROOT BOARD_BOOTCLOCKRUN_UART_CLK_ROOT
static inline void BOARD_ConfigMPU(void) {
}
#endif

10
managed_components/espressif__tinyusb/hw/bsp/imxrt/boards/mimxrt1050_evkb/board.mk Normal file
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CFLAGS += -DCPU_MIMXRT1052DVL6B
MCU_VARIANT = MIMXRT1052
JLINK_DEVICE = MIMXRT1052xxxxB
# For flash-pyocd target
PYOCD_TARGET = mimxrt1050
# flash using pyocd
flash: flash-pyocd

495
managed_components/espressif__tinyusb/hw/bsp/imxrt/boards/mimxrt1050_evkb/board/clock_config.c Normal file
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/*
* How to setup clock using clock driver functions:
*
* 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock.
*
* 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock.
*
* 3. Call CLOCK_SetMux() to configure corresponding clock source for target clock out.
*
* 4. Call CLOCK_SetDiv() to configure corresponding clock divider for target clock out.
*
* 5. Call CLOCK_SetXtalFreq() to set XTAL frequency based on board settings.
*
*/
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!GlobalInfo
product: Clocks v11.0
processor: MIMXRT1052xxxxB
package_id: MIMXRT1052DVL6B
mcu_data: ksdk2_0
processor_version: 13.0.2
board: IMXRT1050-EVKB
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
#include "clock_config.h"
#include "fsl_iomuxc.h"
/*******************************************************************************
* Definitions
******************************************************************************/
/*******************************************************************************
* Variables
******************************************************************************/
/*******************************************************************************
************************ BOARD_InitBootClocks function ************************
******************************************************************************/
void BOARD_InitBootClocks(void)
{
BOARD_BootClockRUN();
}
/*******************************************************************************
********************** Configuration BOARD_BootClockRUN ***********************
******************************************************************************/
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!Configuration
name: BOARD_BootClockRUN
called_from_default_init: true
outputs:
- {id: AHB_CLK_ROOT.outFreq, value: 600 MHz}
- {id: CAN_CLK_ROOT.outFreq, value: 40 MHz}
- {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz}
- {id: CLK_1M.outFreq, value: 1 MHz}
- {id: CLK_24M.outFreq, value: 24 MHz}
- {id: CSI_CLK_ROOT.outFreq, value: 12 MHz}
- {id: ENET_125M_CLK.outFreq, value: 2.4 MHz}
- {id: ENET_25M_REF_CLK.outFreq, value: 1.2 MHz}
- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz}
- {id: FLEXIO2_CLK_ROOT.outFreq, value: 30 MHz}
- {id: FLEXSPI_CLK_ROOT.outFreq, value: 160 MHz}
- {id: GPT1_ipg_clk_highfreq.outFreq, value: 75 MHz}
- {id: GPT2_ipg_clk_highfreq.outFreq, value: 75 MHz}
- {id: IPG_CLK_ROOT.outFreq, value: 150 MHz}
- {id: LCDIF_CLK_ROOT.outFreq, value: 67.5 MHz}
- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz}
- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz}
- {id: LVDS1_CLK.outFreq, value: 1.2 GHz}
- {id: MQS_MCLK.outFreq, value: 1080/17 MHz}
- {id: PERCLK_CLK_ROOT.outFreq, value: 75 MHz}
- {id: PLL7_MAIN_CLK.outFreq, value: 480 MHz}
- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz}
- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz}
- {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz}
- {id: SAI1_MCLK3.outFreq, value: 30 MHz}
- {id: SAI2_CLK_ROOT.outFreq, value: 1080/17 MHz}
- {id: SAI2_MCLK1.outFreq, value: 1080/17 MHz}
- {id: SAI2_MCLK3.outFreq, value: 30 MHz}
- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz}
- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz}
- {id: SAI3_MCLK3.outFreq, value: 30 MHz}
- {id: SEMC_CLK_ROOT.outFreq, value: 75 MHz}
- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz}
- {id: TRACE_CLK_ROOT.outFreq, value: 132 MHz}
- {id: UART_CLK_ROOT.outFreq, value: 80 MHz}
- {id: USBPHY1_CLK.outFreq, value: 480 MHz}
- {id: USBPHY2_CLK.outFreq, value: 480 MHz}
- {id: USDHC1_CLK_ROOT.outFreq, value: 198 MHz}
- {id: USDHC2_CLK_ROOT.outFreq, value: 198 MHz}
settings:
- {id: CCM.AHB_PODF.scale, value: '1', locked: true}
- {id: CCM.ARM_PODF.scale, value: '2', locked: true}
- {id: CCM.FLEXSPI_PODF.scale, value: '3', locked: true}
- {id: CCM.FLEXSPI_SEL.sel, value: CCM.PLL3_SW_CLK_SEL}
- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true}
- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true}
- {id: CCM.SEMC_PODF.scale, value: '8'}
- {id: CCM.TRACE_CLK_SEL.sel, value: CCM_ANALOG.PLL2_MAIN_CLK}
- {id: CCM_ANALOG.PLL1_BYPASS.sel, value: CCM_ANALOG.PLL1}
- {id: CCM_ANALOG.PLL1_PREDIV.scale, value: '1', locked: true}
- {id: CCM_ANALOG.PLL1_VDIV.scale, value: '50', locked: true}
- {id: CCM_ANALOG.PLL2.denom, value: '1', locked: true}
- {id: CCM_ANALOG.PLL2.num, value: '0', locked: true}
- {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK}
- {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0}
- {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1}
- {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2}
- {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3}
- {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3}
- {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0}
- {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '33', locked: true}
- {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true}
- {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1}
- {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2}
- {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3}
- {id: CCM_ANALOG.PLL4.denom, value: '50'}
- {id: CCM_ANALOG.PLL4.div, value: '47'}
- {id: CCM_ANALOG.PLL5.denom, value: '1'}
- {id: CCM_ANALOG.PLL5.div, value: '40'}
- {id: CCM_ANALOG.PLL5.num, value: '0'}
- {id: CCM_ANALOG.PLL5_BYPASS.sel, value: CCM_ANALOG.PLL5_POST_DIV}
- {id: CCM_ANALOG.PLL5_POST_DIV.scale, value: '2'}
- {id: CCM_ANALOG.PLL7_BYPASS.sel, value: CCM_ANALOG.PLL7}
- {id: CCM_ANALOG.VIDEO_DIV.scale, value: '4'}
- {id: CCM_ANALOG_PLL_ENET_POWERDOWN_CFG, value: 'Yes'}
- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_CFG, value: Enabled}
- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_OUT_CFG, value: Enabled}
- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'}
- {id: CCM_ANALOG_PLL_USB2_EN_USB_CLKS_CFG, value: Enabled}
- {id: CCM_ANALOG_PLL_USB2_EN_USB_CLKS_OUT_CFG, value: Enabled}
- {id: CCM_ANALOG_PLL_USB2_POWER_CFG, value: 'Yes'}
- {id: CCM_ANALOG_PLL_VIDEO_POWERDOWN_CFG, value: 'No'}
sources:
- {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/*******************************************************************************
* Variables for BOARD_BootClockRUN configuration
******************************************************************************/
const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN =
{
.loopDivider = 100, /* PLL loop divider, Fout = Fin * 50 */
.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
};
const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN =
{
.loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */
.numerator = 0, /* 30 bit numerator of fractional loop divider */
.denominator = 1, /* 30 bit denominator of fractional loop divider */
.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
};
const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN =
{
.loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */
.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
};
const clock_usb_pll_config_t usb2PllConfig_BOARD_BootClockRUN =
{
.loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */
.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
};
const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN =
{
.loopDivider = 40, /* PLL loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
.postDivider = 8, /* Divider after PLL */
.numerator = 0, /* 30 bit numerator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
.denominator = 1, /* 30 bit denominator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
};
/*******************************************************************************
* Code for BOARD_BootClockRUN configuration
******************************************************************************/
void BOARD_BootClockRUN(void)
{
/* Init RTC OSC clock frequency. */
CLOCK_SetRtcXtalFreq(32768U);
/* Enable 1MHz clock output. */
XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK;
/* Use free 1MHz clock output. */
XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK;
/* Set XTAL 24MHz clock frequency. */
CLOCK_SetXtalFreq(24000000U);
/* Enable XTAL 24MHz clock source. */
CLOCK_InitExternalClk(0);
/* Enable internal RC. */
CLOCK_InitRcOsc24M();
/* Switch clock source to external OSC. */
CLOCK_SwitchOsc(kCLOCK_XtalOsc);
/* Set Oscillator ready counter value. */
CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127);
/* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */
CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */
CLOCK_SetMux(kCLOCK_PeriphMux, 1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */
/* Setting the VDD_SOC to 1.275V. It is necessary to config AHB to 600Mhz. */
DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x13);
/* Waiting for DCDC_STS_DC_OK bit is asserted */
while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0))
{
}
/* Set AHB_PODF. */
CLOCK_SetDiv(kCLOCK_AhbDiv, 0);
/* Disable IPG clock gate. */
CLOCK_DisableClock(kCLOCK_Adc1);
CLOCK_DisableClock(kCLOCK_Adc2);
CLOCK_DisableClock(kCLOCK_Xbar1);
CLOCK_DisableClock(kCLOCK_Xbar2);
CLOCK_DisableClock(kCLOCK_Xbar3);
/* Set IPG_PODF. */
CLOCK_SetDiv(kCLOCK_IpgDiv, 3);
/* Set ARM_PODF. */
CLOCK_SetDiv(kCLOCK_ArmDiv, 1);
/* Set PERIPH_CLK2_PODF. */
CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0);
/* Disable PERCLK clock gate. */
CLOCK_DisableClock(kCLOCK_Gpt1);
CLOCK_DisableClock(kCLOCK_Gpt1S);
CLOCK_DisableClock(kCLOCK_Gpt2);
CLOCK_DisableClock(kCLOCK_Gpt2S);
CLOCK_DisableClock(kCLOCK_Pit);
/* Set PERCLK_PODF. */
CLOCK_SetDiv(kCLOCK_PerclkDiv, 1);
/* Disable USDHC1 clock gate. */
CLOCK_DisableClock(kCLOCK_Usdhc1);
/* Set USDHC1_PODF. */
CLOCK_SetDiv(kCLOCK_Usdhc1Div, 1);
/* Set Usdhc1 clock source. */
CLOCK_SetMux(kCLOCK_Usdhc1Mux, 0);
/* Disable USDHC2 clock gate. */
CLOCK_DisableClock(kCLOCK_Usdhc2);
/* Set USDHC2_PODF. */
CLOCK_SetDiv(kCLOCK_Usdhc2Div, 1);
/* Set Usdhc2 clock source. */
CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0);
/* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
* With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
* Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
#ifndef SKIP_SYSCLK_INIT
/* Disable Semc clock gate. */
CLOCK_DisableClock(kCLOCK_Semc);
/* Set SEMC_PODF. */
CLOCK_SetDiv(kCLOCK_SemcDiv, 7);
/* Set Semc alt clock source. */
CLOCK_SetMux(kCLOCK_SemcAltMux, 0);
/* Set Semc clock source. */
CLOCK_SetMux(kCLOCK_SemcMux, 0);
#endif
/* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
* With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
* Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
/* Disable Flexspi clock gate. */
CLOCK_DisableClock(kCLOCK_FlexSpi);
/* Set FLEXSPI_PODF. */
CLOCK_SetDiv(kCLOCK_FlexspiDiv, 2);
/* Set Flexspi clock source. */
CLOCK_SetMux(kCLOCK_FlexspiMux, 1);
#endif
/* Disable CSI clock gate. */
CLOCK_DisableClock(kCLOCK_Csi);
/* Set CSI_PODF. */
CLOCK_SetDiv(kCLOCK_CsiDiv, 1);
/* Set Csi clock source. */
CLOCK_SetMux(kCLOCK_CsiMux, 0);
/* Disable LPSPI clock gate. */
CLOCK_DisableClock(kCLOCK_Lpspi1);
CLOCK_DisableClock(kCLOCK_Lpspi2);
CLOCK_DisableClock(kCLOCK_Lpspi3);
CLOCK_DisableClock(kCLOCK_Lpspi4);
/* Set LPSPI_PODF. */
CLOCK_SetDiv(kCLOCK_LpspiDiv, 4);
/* Set Lpspi clock source. */
CLOCK_SetMux(kCLOCK_LpspiMux, 2);
/* Disable TRACE clock gate. */
CLOCK_DisableClock(kCLOCK_Trace);
/* Set TRACE_PODF. */
CLOCK_SetDiv(kCLOCK_TraceDiv, 3);
/* Set Trace clock source. */
CLOCK_SetMux(kCLOCK_TraceMux, 0);
/* Disable SAI1 clock gate. */
CLOCK_DisableClock(kCLOCK_Sai1);
/* Set SAI1_CLK_PRED. */
CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3);
/* Set SAI1_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_Sai1Div, 1);
/* Set Sai1 clock source. */
CLOCK_SetMux(kCLOCK_Sai1Mux, 0);
/* Disable SAI2 clock gate. */
CLOCK_DisableClock(kCLOCK_Sai2);
/* Set SAI2_CLK_PRED. */
CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3);
/* Set SAI2_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_Sai2Div, 1);
/* Set Sai2 clock source. */
CLOCK_SetMux(kCLOCK_Sai2Mux, 0);
/* Disable SAI3 clock gate. */
CLOCK_DisableClock(kCLOCK_Sai3);
/* Set SAI3_CLK_PRED. */
CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3);
/* Set SAI3_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_Sai3Div, 1);
/* Set Sai3 clock source. */
CLOCK_SetMux(kCLOCK_Sai3Mux, 0);
/* Disable Lpi2c clock gate. */
CLOCK_DisableClock(kCLOCK_Lpi2c1);
CLOCK_DisableClock(kCLOCK_Lpi2c2);
CLOCK_DisableClock(kCLOCK_Lpi2c3);
/* Set LPI2C_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0);
/* Set Lpi2c clock source. */
CLOCK_SetMux(kCLOCK_Lpi2cMux, 0);
/* Disable CAN clock gate. */
CLOCK_DisableClock(kCLOCK_Can1);
CLOCK_DisableClock(kCLOCK_Can2);
CLOCK_DisableClock(kCLOCK_Can1S);
CLOCK_DisableClock(kCLOCK_Can2S);
/* Set CAN_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_CanDiv, 1);
/* Set Can clock source. */
CLOCK_SetMux(kCLOCK_CanMux, 2);
/* Disable UART clock gate. */
CLOCK_DisableClock(kCLOCK_Lpuart1);
CLOCK_DisableClock(kCLOCK_Lpuart2);
CLOCK_DisableClock(kCLOCK_Lpuart3);
CLOCK_DisableClock(kCLOCK_Lpuart4);
CLOCK_DisableClock(kCLOCK_Lpuart5);
CLOCK_DisableClock(kCLOCK_Lpuart6);
CLOCK_DisableClock(kCLOCK_Lpuart7);
CLOCK_DisableClock(kCLOCK_Lpuart8);
/* Set UART_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_UartDiv, 0);
/* Set Uart clock source. */
CLOCK_SetMux(kCLOCK_UartMux, 0);
/* Disable LCDIF clock gate. */
CLOCK_DisableClock(kCLOCK_LcdPixel);
/* Set LCDIF_PRED. */
CLOCK_SetDiv(kCLOCK_LcdifPreDiv, 1);
/* Set LCDIF_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_LcdifDiv, 3);
/* Set Lcdif pre clock source. */
CLOCK_SetMux(kCLOCK_LcdifPreMux, 5);
/* Disable SPDIF clock gate. */
CLOCK_DisableClock(kCLOCK_Spdif);
/* Set SPDIF0_CLK_PRED. */
CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1);
/* Set SPDIF0_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_Spdif0Div, 7);
/* Set Spdif clock source. */
CLOCK_SetMux(kCLOCK_SpdifMux, 3);
/* Disable Flexio1 clock gate. */
CLOCK_DisableClock(kCLOCK_Flexio1);
/* Set FLEXIO1_CLK_PRED. */
CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1);
/* Set FLEXIO1_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_Flexio1Div, 7);
/* Set Flexio1 clock source. */
CLOCK_SetMux(kCLOCK_Flexio1Mux, 3);
/* Disable Flexio2 clock gate. */
CLOCK_DisableClock(kCLOCK_Flexio2);
/* Set FLEXIO2_CLK_PRED. */
CLOCK_SetDiv(kCLOCK_Flexio2PreDiv, 1);
/* Set FLEXIO2_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_Flexio2Div, 7);
/* Set Flexio2 clock source. */
CLOCK_SetMux(kCLOCK_Flexio2Mux, 3);
/* Set Pll3 sw clock source. */
CLOCK_SetMux(kCLOCK_Pll3SwMux, 0);
/* Init ARM PLL. */
CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN);
/* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
* With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
* Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
#ifndef SKIP_SYSCLK_INIT
#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1)
#warning "SKIP_SYSCLK_INIT should be defined to keep system pll (selected to be SEMC source clock in SDK projects) unchanged."
#endif
/* Init System PLL. */
CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN);
/* Init System pfd0. */
CLOCK_InitSysPfd(kCLOCK_Pfd0, 27);
/* Init System pfd1. */
CLOCK_InitSysPfd(kCLOCK_Pfd1, 16);
/* Init System pfd2. */
CLOCK_InitSysPfd(kCLOCK_Pfd2, 24);
/* Init System pfd3. */
CLOCK_InitSysPfd(kCLOCK_Pfd3, 16);
#endif
/* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
* With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
* Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
/* Init Usb1 PLL. */
CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN);
/* Init Usb1 pfd0. */
CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 33);
/* Init Usb1 pfd1. */
CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16);
/* Init Usb1 pfd2. */
CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17);
/* Init Usb1 pfd3. */
CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 19);
#endif
/* DeInit Audio PLL. */
CLOCK_DeinitAudioPll();
/* Bypass Audio PLL. */
CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1);
/* Set divider for Audio PLL. */
CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK;
CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK;
/* Enable Audio PLL output. */
CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK;
/* Init Video PLL. */
uint32_t pllVideo;
/* Disable Video PLL output before initial Video PLL. */
CCM_ANALOG->PLL_VIDEO &= ~CCM_ANALOG_PLL_VIDEO_ENABLE_MASK;
/* Bypass PLL first */
CCM_ANALOG->PLL_VIDEO = (CCM_ANALOG->PLL_VIDEO & (~CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK)) |
CCM_ANALOG_PLL_VIDEO_BYPASS_MASK | CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(0);
CCM_ANALOG->PLL_VIDEO_NUM = CCM_ANALOG_PLL_VIDEO_NUM_A(0);
CCM_ANALOG->PLL_VIDEO_DENOM = CCM_ANALOG_PLL_VIDEO_DENOM_B(1);
pllVideo = (CCM_ANALOG->PLL_VIDEO & (~(CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK | CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK))) |
CCM_ANALOG_PLL_VIDEO_ENABLE_MASK |CCM_ANALOG_PLL_VIDEO_DIV_SELECT(40);
pllVideo |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(1);
CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(3);
CCM_ANALOG->PLL_VIDEO = pllVideo;
while ((CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) == 0)
{
}
/* Disable bypass for Video PLL. */
CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllVideo, 0);
/* DeInit Enet PLL. */
CLOCK_DeinitEnetPll();
/* Bypass Enet PLL. */
CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllEnet, 1);
/* Set Enet output divider. */
CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_DIV_SELECT(1);
/* Enable Enet output. */
CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENABLE_MASK;
/* Enable Enet25M output. */
CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK;
/* Init Usb2 PLL. */
CLOCK_InitUsb2Pll(&usb2PllConfig_BOARD_BootClockRUN);
/* Set preperiph clock source. */
CLOCK_SetMux(kCLOCK_PrePeriphMux, 3);
/* Set periph clock source. */
CLOCK_SetMux(kCLOCK_PeriphMux, 0);
/* Set periph clock2 clock source. */
CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
/* Set per clock source. */
CLOCK_SetMux(kCLOCK_PerclkMux, 0);
/* Set lvds1 clock source. */
CCM_ANALOG->MISC1 = (CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0);
/* Set clock out1 divider. */
CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0);
/* Set clock out1 source. */
CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1);
/* Set clock out2 divider. */
CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0);
/* Set clock out2 source. */
CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(18);
/* Set clock out1 drives clock out1. */
CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK;
/* Disable clock out1. */
CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK;
/* Disable clock out2. */
CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK;
/* Set SAI1 MCLK1 clock source. */
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0);
/* Set SAI1 MCLK2 clock source. */
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0);
/* Set SAI1 MCLK3 clock source. */
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0);
/* Set SAI2 MCLK3 clock source. */
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0);
/* Set SAI3 MCLK3 clock source. */
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
/* Set MQS configuration. */
IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0);
/* Set ENET Ref clock source. */
#if defined(IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK)
IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK;
#elif defined(IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK)
/* Backward compatibility for original bitfield name */
IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK;
#else
#error "Neither IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK nor IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK is defined."
#endif /* defined(IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK) */
/* Set GPT1 High frequency reference clock source. */
IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK;
/* Set GPT2 High frequency reference clock source. */
IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK;
/* Set SystemCoreClock variable. */
SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
}

119
managed_components/espressif__tinyusb/hw/bsp/imxrt/boards/mimxrt1050_evkb/board/clock_config.h Normal file
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#ifndef _CLOCK_CONFIG_H_
#define _CLOCK_CONFIG_H_
#include "fsl_common.h"
/*******************************************************************************
* Definitions
******************************************************************************/
#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */
#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */
/*******************************************************************************
************************ BOARD_InitBootClocks function ************************
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/
/*!
* @brief This function executes default configuration of clocks.
*
*/
void BOARD_InitBootClocks(void);
#if defined(__cplusplus)
}
#endif /* __cplusplus*/
/*******************************************************************************
********************** Configuration BOARD_BootClockRUN ***********************
******************************************************************************/
/*******************************************************************************
* Definitions for BOARD_BootClockRUN configuration
******************************************************************************/
#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 600000000U /*!< Core clock frequency: 600000000Hz */
/* Clock outputs (values are in Hz): */
#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT 600000000UL
#define BOARD_BOOTCLOCKRUN_CAN_CLK_ROOT 40000000UL
#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL
#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL
#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL
#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL
#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL
#define BOARD_BOOTCLOCKRUN_CSI_CLK_ROOT 12000000UL
#define BOARD_BOOTCLOCKRUN_ENET_125M_CLK 2400000UL
#define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK 1200000UL
#define BOARD_BOOTCLOCKRUN_ENET_REF_CLK 0UL
#define BOARD_BOOTCLOCKRUN_ENET_TX_CLK 0UL
#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL
#define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT 30000000UL
#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 160000000UL
#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 75000000UL
#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 75000000UL
#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 150000000UL
#define BOARD_BOOTCLOCKRUN_LCDIF_CLK_ROOT 67500000UL
#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL
#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL
#define BOARD_BOOTCLOCKRUN_LVDS1_CLK 1200000000UL
#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL
#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 75000000UL
#define BOARD_BOOTCLOCKRUN_PLL7_MAIN_CLK 480000000UL
#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL
#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 63529411UL
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 63529411UL
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 30000000UL
#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL
#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 75000000UL
#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL
#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL
#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 132000000UL
#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL
#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK 480000000UL
#define BOARD_BOOTCLOCKRUN_USBPHY2_CLK 480000000UL
#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 198000000UL
#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 198000000UL
/*! @brief Arm PLL set for BOARD_BootClockRUN configuration.
*/
extern const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN;
/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration.
*/
extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN;
/*! @brief Usb2 PLL set for BOARD_BootClockRUN configuration.
*/
extern const clock_usb_pll_config_t usb2PllConfig_BOARD_BootClockRUN;
/*! @brief Sys PLL for BOARD_BootClockRUN configuration.
*/
extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN;
/*! @brief Video PLL set for BOARD_BootClockRUN configuration.
*/
extern const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN;
/*******************************************************************************
* API for BOARD_BootClockRUN configuration
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/
/*!
* @brief This function executes configuration of clocks.
*
*/
void BOARD_BootClockRUN(void);
#if defined(__cplusplus)
}
#endif /* __cplusplus*/
#endif /* _CLOCK_CONFIG_H_ */

618
managed_components/espressif__tinyusb/hw/bsp/imxrt/boards/mimxrt1050_evkb/board/pin_mux.c Normal file
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/***********************************************************************************************************************
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
**********************************************************************************************************************/
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!GlobalInfo
product: Pins v13.1
processor: MIMXRT1052xxxxB
package_id: MIMXRT1052DVL6B
mcu_data: ksdk2_0
processor_version: 13.0.2
board: IMXRT1050-EVKB
pin_labels:
- {pin_num: F14, pin_signal: GPIO_AD_B0_09, label: 'JTAG_TDI/J21[5]/ENET_RST/J22[5]', identifier: USER_LED}
- {pin_num: L6, pin_signal: WAKEUP, label: SD_PWREN, identifier: USER_BUTTON}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
#include "fsl_common.h"
#include "fsl_iomuxc.h"
#include "fsl_gpio.h"
#include "pin_mux.h"
/* FUNCTION ************************************************************************************************************
*
* Function Name : BOARD_InitBootPins
* Description : Calls initialization functions.
*
* END ****************************************************************************************************************/
void BOARD_InitBootPins(void) {
BOARD_InitPins();
BOARD_InitDEBUG_UARTPins();
}
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
BOARD_InitPins:
- options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'}
- pin_list:
- {pin_num: F14, peripheral: GPIO1, signal: 'gpio_io, 09', pin_signal: GPIO_AD_B0_09, direction: OUTPUT, pull_keeper_select: Keeper}
- {pin_num: L6, peripheral: GPIO5, signal: 'gpio_io, 00', pin_signal: WAKEUP, direction: INPUT, pull_up_down_config: Pull_Up_100K_Ohm}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
/* FUNCTION ************************************************************************************************************
*
* Function Name : BOARD_InitPins
* Description : Configures pin routing and optionally pin electrical features.
*
* END ****************************************************************************************************************/
void BOARD_InitPins(void) {
CLOCK_EnableClock(kCLOCK_Iomuxc);
CLOCK_EnableClock(kCLOCK_IomuxcSnvs);
/* GPIO configuration of USER_LED on GPIO_AD_B0_09 (pin F14) */
gpio_pin_config_t USER_LED_config = {
.direction = kGPIO_DigitalOutput,
.outputLogic = 0U,
.interruptMode = kGPIO_NoIntmode
};
/* Initialize GPIO functionality on GPIO_AD_B0_09 (pin F14) */
GPIO_PinInit(GPIO1, 9U, &USER_LED_config);
/* GPIO configuration of USER_BUTTON on WAKEUP (pin L6) */
gpio_pin_config_t USER_BUTTON_config = {
.direction = kGPIO_DigitalInput,
.outputLogic = 0U,
.interruptMode = kGPIO_NoIntmode
};
/* Initialize GPIO functionality on WAKEUP (pin L6) */
GPIO_PinInit(GPIO5, 0U, &USER_BUTTON_config);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, 0U);
IOMUXC_SetPinMux(IOMUXC_SNVS_WAKEUP_GPIO5_IO00, 0U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, 0x50A0U);
IOMUXC_SetPinConfig(IOMUXC_SNVS_WAKEUP_GPIO5_IO00, 0x01B0A0U);
}
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
BOARD_InitDEBUG_UARTPins:
- options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'}
- pin_list:
- {pin_num: K14, peripheral: LPUART1, signal: TX, pin_signal: GPIO_AD_B0_12, software_input_on: Disable, hysteresis_enable: Disable, pull_up_down_config: Pull_Down_100K_Ohm,
pull_keeper_select: Keeper, pull_keeper_enable: Enable, open_drain: Disable, speed: MHZ_100, drive_strength: R0_6, slew_rate: Slow}
- {pin_num: L14, peripheral: LPUART1, signal: RX, pin_signal: GPIO_AD_B0_13, software_input_on: Disable, hysteresis_enable: Disable, pull_up_down_config: Pull_Down_100K_Ohm,
pull_keeper_select: Keeper, pull_keeper_enable: Enable, open_drain: Disable, speed: MHZ_100, drive_strength: R0_6, slew_rate: Slow}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
/* FUNCTION ************************************************************************************************************
*
* Function Name : BOARD_InitDEBUG_UARTPins
* Description : Configures pin routing and optionally pin electrical features.
*
* END ****************************************************************************************************************/
void BOARD_InitDEBUG_UARTPins(void) {
CLOCK_EnableClock(kCLOCK_Iomuxc);
#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_12_LPUART1_TXD, 0U);
#else
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_12_LPUART1_TX, 0U);
#endif
#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_13_LPUART1_RXD, 0U);
#else
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_13_LPUART1_RX, 0U);
#endif
#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_12_LPUART1_TXD, 0x10B0U);
#else
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_12_LPUART1_TX, 0x10B0U);
#endif
#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_13_LPUART1_RXD, 0x10B0U);
#else
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_13_LPUART1_RX, 0x10B0U);
#endif
}
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
BOARD_InitSDRAMPins:
- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'}
- pin_list:
- {pin_num: C2, peripheral: SEMC, signal: 'ADDR, 00', pin_signal: GPIO_EMC_09}
- {pin_num: G1, peripheral: SEMC, signal: 'ADDR, 01', pin_signal: GPIO_EMC_10}
- {pin_num: G3, peripheral: SEMC, signal: 'ADDR, 02', pin_signal: GPIO_EMC_11}
- {pin_num: H1, peripheral: SEMC, signal: 'ADDR, 03', pin_signal: GPIO_EMC_12}
- {pin_num: A6, peripheral: SEMC, signal: 'ADDR, 04', pin_signal: GPIO_EMC_13}
- {pin_num: B6, peripheral: SEMC, signal: 'ADDR, 05', pin_signal: GPIO_EMC_14}
- {pin_num: B1, peripheral: SEMC, signal: 'ADDR, 06', pin_signal: GPIO_EMC_15}
- {pin_num: A5, peripheral: SEMC, signal: 'ADDR, 07', pin_signal: GPIO_EMC_16}
- {pin_num: A4, peripheral: SEMC, signal: 'ADDR, 08', pin_signal: GPIO_EMC_17}
- {pin_num: B2, peripheral: SEMC, signal: 'ADDR, 09', pin_signal: GPIO_EMC_18}
- {pin_num: G2, peripheral: SEMC, signal: 'ADDR, 10', pin_signal: GPIO_EMC_23}
- {pin_num: B4, peripheral: SEMC, signal: 'ADDR, 11', pin_signal: GPIO_EMC_19}
- {pin_num: A3, peripheral: SEMC, signal: 'ADDR, 12', pin_signal: GPIO_EMC_20}
- {pin_num: C1, peripheral: SEMC, signal: 'BA, 0', pin_signal: GPIO_EMC_21}
- {pin_num: F1, peripheral: SEMC, signal: 'BA, 1', pin_signal: GPIO_EMC_22}
- {pin_num: D3, peripheral: SEMC, signal: semc_cas, pin_signal: GPIO_EMC_24}
- {pin_num: A2, peripheral: SEMC, signal: semc_cke, pin_signal: GPIO_EMC_27}
- {pin_num: B3, peripheral: SEMC, signal: semc_clk, pin_signal: GPIO_EMC_26}
- {pin_num: E3, peripheral: SEMC, signal: 'DATA, 00', pin_signal: GPIO_EMC_00}
- {pin_num: F3, peripheral: SEMC, signal: 'DATA, 01', pin_signal: GPIO_EMC_01}
- {pin_num: F4, peripheral: SEMC, signal: 'DATA, 02', pin_signal: GPIO_EMC_02}
- {pin_num: G4, peripheral: SEMC, signal: 'DATA, 03', pin_signal: GPIO_EMC_03}
- {pin_num: F2, peripheral: SEMC, signal: 'DATA, 04', pin_signal: GPIO_EMC_04}
- {pin_num: G5, peripheral: SEMC, signal: 'DATA, 05', pin_signal: GPIO_EMC_05}
- {pin_num: H5, peripheral: SEMC, signal: 'DATA, 06', pin_signal: GPIO_EMC_06}
- {pin_num: H4, peripheral: SEMC, signal: 'DATA, 07', pin_signal: GPIO_EMC_07}
- {pin_num: C6, peripheral: SEMC, signal: 'DATA, 08', pin_signal: GPIO_EMC_30}
- {pin_num: C5, peripheral: SEMC, signal: 'DATA, 09', pin_signal: GPIO_EMC_31}
- {pin_num: D5, peripheral: SEMC, signal: 'DATA, 10', pin_signal: GPIO_EMC_32}
- {pin_num: C4, peripheral: SEMC, signal: 'DATA, 11', pin_signal: GPIO_EMC_33}
- {pin_num: D4, peripheral: SEMC, signal: 'DATA, 12', pin_signal: GPIO_EMC_34}
- {pin_num: E5, peripheral: SEMC, signal: 'DATA, 13', pin_signal: GPIO_EMC_35}
- {pin_num: C3, peripheral: SEMC, signal: 'DATA, 14', pin_signal: GPIO_EMC_36}
- {pin_num: E4, peripheral: SEMC, signal: 'DATA, 15', pin_signal: GPIO_EMC_37}
- {pin_num: H3, peripheral: SEMC, signal: 'DM, 0', pin_signal: GPIO_EMC_08}
- {pin_num: D6, peripheral: SEMC, signal: 'DM, 1', pin_signal: GPIO_EMC_38}
- {pin_num: D2, peripheral: SEMC, signal: semc_ras, pin_signal: GPIO_EMC_25}
- {pin_num: D1, peripheral: SEMC, signal: semc_we, pin_signal: GPIO_EMC_28}
- {pin_num: C7, peripheral: SEMC, signal: 'CSX, 0', pin_signal: GPIO_EMC_41}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
/* FUNCTION ************************************************************************************************************
*
* Function Name : BOARD_InitSDRAMPins
* Description : Configures pin routing and optionally pin electrical features.
*
* END ****************************************************************************************************************/
void BOARD_InitSDRAMPins(void) {
CLOCK_EnableClock(kCLOCK_Iomuxc);
#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_00_SEMC_DA00, 0U);
#else
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_00_SEMC_DATA00, 0U);
#endif
#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_01_SEMC_DA01, 0U);
#else
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_01_SEMC_DATA01, 0U);
#endif
#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_02_SEMC_DA02, 0U);
#else
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_02_SEMC_DATA02, 0U);
#endif
#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_03_SEMC_DA03, 0U);
#else
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_03_SEMC_DATA03, 0U);
#endif
#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_04_SEMC_DA04, 0U);
#else
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_04_SEMC_DATA04, 0U);
#endif
#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_05_SEMC_DA05, 0U);
#else
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_05_SEMC_DATA05, 0U);
#endif
#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_06_SEMC_DA06, 0U);
#else
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_06_SEMC_DATA06, 0U);
#endif
#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_07_SEMC_DA07, 0U);
#else
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_07_SEMC_DATA07, 0U);
#endif
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_08_SEMC_DM00, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_09_SEMC_ADDR00, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_10_SEMC_ADDR01, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_11_SEMC_ADDR02, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_12_SEMC_ADDR03, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_13_SEMC_ADDR04, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_14_SEMC_ADDR05, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_15_SEMC_ADDR06, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_16_SEMC_ADDR07, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_17_SEMC_ADDR08, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_18_SEMC_ADDR09, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_19_SEMC_ADDR11, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_20_SEMC_ADDR12, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_21_SEMC_BA0, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_22_SEMC_BA1, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_23_SEMC_ADDR10, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_24_SEMC_CAS, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_25_SEMC_RAS, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_26_SEMC_CLK, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_27_SEMC_CKE, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_28_SEMC_WE, 0U);
#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_30_SEMC_DA08, 0U);
#else
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_30_SEMC_DATA08, 0U);
#endif
#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_31_SEMC_DA09, 0U);
#else
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_31_SEMC_DATA09, 0U);
#endif
#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_32_SEMC_DA10, 0U);
#else
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_32_SEMC_DATA10, 0U);
#endif
#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_33_SEMC_DA11, 0U);
#else
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_33_SEMC_DATA11, 0U);
#endif
#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_34_SEMC_DA12, 0U);
#else
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_34_SEMC_DATA12, 0U);
#endif
#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_35_SEMC_DA13, 0U);
#else
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_35_SEMC_DATA13, 0U);
#endif
#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_36_SEMC_DA14, 0U);
#else
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_36_SEMC_DATA14, 0U);
#endif
#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_37_SEMC_DA15, 0U);
#else
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_37_SEMC_DATA15, 0U);
#endif
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_38_SEMC_DM01, 0U);
#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_41_SEMC_CSX0, 0U);
#else
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_41_SEMC_CSX00, 0U);
#endif
}
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
BOARD_InitCSIPins:
- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'}
- pin_list:
- {pin_num: H13, peripheral: CSI, signal: 'csi_data, 09', pin_signal: GPIO_AD_B1_08}
- {pin_num: M13, peripheral: CSI, signal: 'csi_data, 08', pin_signal: GPIO_AD_B1_09}
- {pin_num: L13, peripheral: CSI, signal: 'csi_data, 07', pin_signal: GPIO_AD_B1_10}
- {pin_num: J13, peripheral: CSI, signal: 'csi_data, 06', pin_signal: GPIO_AD_B1_11}
- {pin_num: H12, peripheral: CSI, signal: 'csi_data, 05', pin_signal: GPIO_AD_B1_12}
- {pin_num: H11, peripheral: CSI, signal: 'csi_data, 04', pin_signal: GPIO_AD_B1_13}
- {pin_num: J14, peripheral: CSI, signal: 'csi_data, 02', pin_signal: GPIO_AD_B1_15}
- {pin_num: G12, peripheral: CSI, signal: 'csi_data, 03', pin_signal: GPIO_AD_B1_14}
- {pin_num: L12, peripheral: CSI, signal: csi_pixclk, pin_signal: GPIO_AD_B1_04}
- {pin_num: K12, peripheral: CSI, signal: csi_mclk, pin_signal: GPIO_AD_B1_05}
- {pin_num: J12, peripheral: CSI, signal: csi_vsync, pin_signal: GPIO_AD_B1_06}
- {pin_num: K10, peripheral: CSI, signal: csi_hsync, pin_signal: GPIO_AD_B1_07}
- {pin_num: J11, peripheral: LPI2C1, signal: SCL, pin_signal: GPIO_AD_B1_00, identifier: CSI_I2C_SCL, software_input_on: Disable, hysteresis_enable: Disable, pull_up_down_config: Pull_Up_22K_Ohm,
pull_keeper_select: Keeper, pull_keeper_enable: Enable, open_drain: Enable, speed: MHZ_100, drive_strength: R0_6, slew_rate: Slow}
- {pin_num: K11, peripheral: LPI2C1, signal: SDA, pin_signal: GPIO_AD_B1_01, identifier: CSI_I2C_SDA, software_input_on: Disable, hysteresis_enable: Disable, pull_up_down_config: Pull_Up_22K_Ohm,
pull_keeper_select: Keeper, pull_keeper_enable: Enable, open_drain: Enable, speed: MHZ_100, drive_strength: R0_6, slew_rate: Slow}
- {pin_num: F11, peripheral: GPIO1, signal: 'gpio_io, 04', pin_signal: GPIO_AD_B0_04}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
/* FUNCTION ************************************************************************************************************
*
* Function Name : BOARD_InitCSIPins
* Description : Configures pin routing and optionally pin electrical features.
*
* END ****************************************************************************************************************/
void BOARD_InitCSIPins(void) {
CLOCK_EnableClock(kCLOCK_Iomuxc);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_04_GPIO1_IO04, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_04_CSI_PIXCLK, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_05_CSI_MCLK, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_06_CSI_VSYNC, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_07_CSI_HSYNC, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_08_CSI_DATA09, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_09_CSI_DATA08, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_10_CSI_DATA07, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_11_CSI_DATA06, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_12_CSI_DATA05, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_13_CSI_DATA04, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_14_CSI_DATA03, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_15_CSI_DATA02, 0U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL, 0xD8B0U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA, 0xD8B0U);
}
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
BOARD_InitLCDPins:
- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'}
- pin_list:
- {pin_num: C8, peripheral: LCDIF, signal: 'lcdif_data, 00', pin_signal: GPIO_B0_04, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
- {pin_num: B8, peripheral: LCDIF, signal: 'lcdif_data, 01', pin_signal: GPIO_B0_05, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
- {pin_num: A8, peripheral: LCDIF, signal: 'lcdif_data, 02', pin_signal: GPIO_B0_06, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
- {pin_num: D7, peripheral: LCDIF, signal: lcdif_clk, pin_signal: GPIO_B0_00, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
- {pin_num: A9, peripheral: LCDIF, signal: 'lcdif_data, 03', pin_signal: GPIO_B0_07, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
- {pin_num: B9, peripheral: LCDIF, signal: 'lcdif_data, 04', pin_signal: GPIO_B0_08, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
- {pin_num: C9, peripheral: LCDIF, signal: 'lcdif_data, 05', pin_signal: GPIO_B0_09, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
- {pin_num: D9, peripheral: LCDIF, signal: 'lcdif_data, 06', pin_signal: GPIO_B0_10, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
- {pin_num: A10, peripheral: LCDIF, signal: 'lcdif_data, 07', pin_signal: GPIO_B0_11, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
- {pin_num: C10, peripheral: LCDIF, signal: 'lcdif_data, 08', pin_signal: GPIO_B0_12, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
- {pin_num: D10, peripheral: LCDIF, signal: 'lcdif_data, 09', pin_signal: GPIO_B0_13, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
- {pin_num: E10, peripheral: LCDIF, signal: 'lcdif_data, 10', pin_signal: GPIO_B0_14, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
- {pin_num: E11, peripheral: LCDIF, signal: 'lcdif_data, 11', pin_signal: GPIO_B0_15, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
- {pin_num: A11, peripheral: LCDIF, signal: 'lcdif_data, 12', pin_signal: GPIO_B1_00, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
- {pin_num: B11, peripheral: LCDIF, signal: 'lcdif_data, 13', pin_signal: GPIO_B1_01, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
- {pin_num: C11, peripheral: LCDIF, signal: 'lcdif_data, 14', pin_signal: GPIO_B1_02, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
- {pin_num: D11, peripheral: LCDIF, signal: 'lcdif_data, 15', pin_signal: GPIO_B1_03, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
- {pin_num: E7, peripheral: LCDIF, signal: lcdif_enable, pin_signal: GPIO_B0_01, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
- {pin_num: E8, peripheral: LCDIF, signal: lcdif_hsync, pin_signal: GPIO_B0_02, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
- {pin_num: D8, peripheral: LCDIF, signal: lcdif_vsync, pin_signal: GPIO_B0_03, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
- {pin_num: B14, peripheral: GPIO2, signal: 'gpio_io, 31', pin_signal: GPIO_B1_15, slew_rate: Slow}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
/* FUNCTION ************************************************************************************************************
*
* Function Name : BOARD_InitLCDPins
* Description : Configures pin routing and optionally pin electrical features.
*
* END ****************************************************************************************************************/
void BOARD_InitLCDPins(void) {
CLOCK_EnableClock(kCLOCK_Iomuxc);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_00_LCD_CLK, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_01_LCD_ENABLE, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_02_LCD_HSYNC, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_03_LCD_VSYNC, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_04_LCD_DATA00, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_05_LCD_DATA01, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_06_LCD_DATA02, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_07_LCD_DATA03, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_08_LCD_DATA04, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_09_LCD_DATA05, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_10_LCD_DATA06, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_11_LCD_DATA07, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_12_LCD_DATA08, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_13_LCD_DATA09, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_14_LCD_DATA10, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_15_LCD_DATA11, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_00_LCD_DATA12, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_01_LCD_DATA13, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_02_LCD_DATA14, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_03_LCD_DATA15, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_15_GPIO2_IO31, 0U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_00_LCD_CLK, 0x01B0B0U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_01_LCD_ENABLE, 0x01B0B0U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_02_LCD_HSYNC, 0x01B0B0U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_03_LCD_VSYNC, 0x01B0B0U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_04_LCD_DATA00, 0x01B0B0U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_05_LCD_DATA01, 0x01B0B0U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_06_LCD_DATA02, 0x01B0B0U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_07_LCD_DATA03, 0x01B0B0U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_08_LCD_DATA04, 0x01B0B0U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_09_LCD_DATA05, 0x01B0B0U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_10_LCD_DATA06, 0x01B0B0U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_11_LCD_DATA07, 0x01B0B0U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_12_LCD_DATA08, 0x01B0B0U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_13_LCD_DATA09, 0x01B0B0U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_14_LCD_DATA10, 0x01B0B0U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_15_LCD_DATA11, 0x01B0B0U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_00_LCD_DATA12, 0x01B0B0U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_01_LCD_DATA13, 0x01B0B0U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_02_LCD_DATA14, 0x01B0B0U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_03_LCD_DATA15, 0x01B0B0U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_15_GPIO2_IO31, 0x10B0U);
}
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
BOARD_InitCANPins:
- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'}
- pin_list:
- {pin_num: H14, peripheral: CAN2, signal: TX, pin_signal: GPIO_AD_B0_14}
- {pin_num: L10, peripheral: CAN2, signal: RX, pin_signal: GPIO_AD_B0_15}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
/* FUNCTION ************************************************************************************************************
*
* Function Name : BOARD_InitCANPins
* Description : Configures pin routing and optionally pin electrical features.
*
* END ****************************************************************************************************************/
void BOARD_InitCANPins(void) {
CLOCK_EnableClock(kCLOCK_Iomuxc);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_14_FLEXCAN2_TX, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_15_FLEXCAN2_RX, 0U);
}
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
BOARD_InitENETPins:
- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'}
- pin_list:
- {pin_num: A7, peripheral: ENET, signal: enet_mdc, pin_signal: GPIO_EMC_40}
- {pin_num: C7, peripheral: ENET, signal: enet_mdio, pin_signal: GPIO_EMC_41}
- {pin_num: B13, peripheral: ENET, signal: enet_ref_clk, pin_signal: GPIO_B1_10}
- {pin_num: E12, peripheral: ENET, signal: 'enet_rx_data, 0', pin_signal: GPIO_B1_04}
- {pin_num: D12, peripheral: ENET, signal: 'enet_rx_data, 1', pin_signal: GPIO_B1_05}
- {pin_num: C12, peripheral: ENET, signal: enet_rx_en, pin_signal: GPIO_B1_06}
- {pin_num: C13, peripheral: ENET, signal: enet_rx_er, pin_signal: GPIO_B1_11}
- {pin_num: B12, peripheral: ENET, signal: 'enet_tx_data, 0', pin_signal: GPIO_B1_07}
- {pin_num: A12, peripheral: ENET, signal: 'enet_tx_data, 1', pin_signal: GPIO_B1_08}
- {pin_num: A13, peripheral: ENET, signal: enet_tx_en, pin_signal: GPIO_B1_09}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
/* FUNCTION ************************************************************************************************************
*
* Function Name : BOARD_InitENETPins
* Description : Configures pin routing and optionally pin electrical features.
*
* END ****************************************************************************************************************/
void BOARD_InitENETPins(void) {
CLOCK_EnableClock(kCLOCK_Iomuxc);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_04_ENET_RX_DATA00, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_05_ENET_RX_DATA01, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_06_ENET_RX_EN, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_07_ENET_TX_DATA00, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_08_ENET_TX_DATA01, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_09_ENET_TX_EN, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_10_ENET_REF_CLK, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_11_ENET_RX_ER, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_40_ENET_MDC, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_41_ENET_MDIO, 0U);
}
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
BOARD_InitUSDHCPins:
- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'}
- pin_list:
- {pin_num: J2, peripheral: USDHC1, signal: 'usdhc_data, 3', pin_signal: GPIO_SD_B0_05}
- {pin_num: H2, peripheral: USDHC1, signal: 'usdhc_data, 2', pin_signal: GPIO_SD_B0_04}
- {pin_num: K1, peripheral: USDHC1, signal: 'usdhc_data, 1', pin_signal: GPIO_SD_B0_03}
- {pin_num: J1, peripheral: USDHC1, signal: 'usdhc_data, 0', pin_signal: GPIO_SD_B0_02}
- {pin_num: J4, peripheral: USDHC1, signal: usdhc_cmd, pin_signal: GPIO_SD_B0_00}
- {pin_num: J3, peripheral: USDHC1, signal: usdhc_clk, pin_signal: GPIO_SD_B0_01}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
/* FUNCTION ************************************************************************************************************
*
* Function Name : BOARD_InitUSDHCPins
* Description : Configures pin routing and optionally pin electrical features.
*
* END ****************************************************************************************************************/
void BOARD_InitUSDHCPins(void) {
CLOCK_EnableClock(kCLOCK_Iomuxc);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_00_USDHC1_CMD, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_01_USDHC1_CLK, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3, 0U);
}
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
BOARD_InitHyperFlashPins:
- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'}
- pin_list:
- {pin_num: L4, peripheral: FLEXSPI, signal: FLEXSPI_A_SCLK, pin_signal: GPIO_SD_B1_07}
- {pin_num: P4, peripheral: FLEXSPI, signal: FLEXSPI_A_DATA2, pin_signal: GPIO_SD_B1_10}
- {pin_num: P3, peripheral: FLEXSPI, signal: FLEXSPI_A_DATA0, pin_signal: GPIO_SD_B1_08}
- {pin_num: N4, peripheral: FLEXSPI, signal: FLEXSPI_A_DATA1, pin_signal: GPIO_SD_B1_09}
- {pin_num: L5, peripheral: FLEXSPI, signal: FLEXSPI_B_DATA3, pin_signal: GPIO_SD_B1_00}
- {pin_num: M5, peripheral: FLEXSPI, signal: FLEXSPI_B_DATA2, pin_signal: GPIO_SD_B1_01}
- {pin_num: M3, peripheral: FLEXSPI, signal: FLEXSPI_B_DATA1, pin_signal: GPIO_SD_B1_02}
- {pin_num: M4, peripheral: FLEXSPI, signal: FLEXSPI_B_DATA0, pin_signal: GPIO_SD_B1_03}
- {pin_num: P2, peripheral: FLEXSPI, signal: FLEXSPI_B_SCLK, pin_signal: GPIO_SD_B1_04}
- {pin_num: L3, peripheral: FLEXSPI, signal: FLEXSPI_A_SS0_B, pin_signal: GPIO_SD_B1_06}
- {pin_num: P5, peripheral: FLEXSPI, signal: FLEXSPI_A_DATA3, pin_signal: GPIO_SD_B1_11}
- {pin_num: N3, peripheral: FLEXSPI, signal: FLEXSPI_A_DQS, pin_signal: GPIO_SD_B1_05}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
/* FUNCTION ************************************************************************************************************
*
* Function Name : BOARD_InitHyperFlashPins
* Description : Configures pin routing and optionally pin electrical features.
*
* END ****************************************************************************************************************/
void BOARD_InitHyperFlashPins(void) {
CLOCK_EnableClock(kCLOCK_Iomuxc);
#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_00_FLEXSPI_B_DATA3, 0U);
#else
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_00_FLEXSPIB_DATA03, 0U);
#endif
#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_01_FLEXSPI_B_DATA2, 0U);
#else
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_01_FLEXSPIB_DATA02, 0U);
#endif
#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_02_FLEXSPI_B_DATA1, 0U);
#else
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_02_FLEXSPIB_DATA01, 0U);
#endif
#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_03_FLEXSPI_B_DATA0, 0U);
#else
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_03_FLEXSPIB_DATA00, 0U);
#endif
#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_04_FLEXSPI_B_SCLK, 0U);
#else
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_04_FLEXSPIB_SCLK, 0U);
#endif
#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_05_FLEXSPI_A_DQS, 0U);
#else
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_05_FLEXSPIA_DQS, 0U);
#endif
#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_06_FLEXSPI_A_SS0_B, 0U);
#else
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_06_FLEXSPIA_SS0_B, 0U);
#endif
#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_07_FLEXSPI_A_SCLK, 0U);
#else
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_07_FLEXSPIA_SCLK, 0U);
#endif
#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_08_FLEXSPI_A_DATA00, 0U);
#else
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_08_FLEXSPIA_DATA00, 0U);
#endif
#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_09_FLEXSPI_A_DATA1, 0U);
#else
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_09_FLEXSPIA_DATA01, 0U);
#endif
#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_10_FLEXSPI_A_DATA2, 0U);
#else
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_10_FLEXSPIA_DATA02, 0U);
#endif
#if FSL_IOMUXC_DRIVER_VERSION >= MAKE_VERSION(2, 0, 3)
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_11_FLEXSPI_A_DATA3, 0U);
#else
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_11_FLEXSPIA_DATA03, 0U);
#endif
}
/***********************************************************************************************************************
* EOF
**********************************************************************************************************************/

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managed_components/espressif__tinyusb/hw/bsp/imxrt/boards/mimxrt1050_evkb/board/pin_mux.h Normal file
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/***********************************************************************************************************************
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
**********************************************************************************************************************/
#ifndef _PIN_MUX_H_
#define _PIN_MUX_H_
/***********************************************************************************************************************
* Definitions
**********************************************************************************************************************/
/*! @brief Direction type */
typedef enum _pin_mux_direction
{
kPIN_MUX_DirectionInput = 0U, /* Input direction */
kPIN_MUX_DirectionOutput = 1U, /* Output direction */
kPIN_MUX_DirectionInputOrOutput = 2U /* Input or output direction */
} pin_mux_direction_t;
/*!
* @addtogroup pin_mux
* @{
*/
/***********************************************************************************************************************
* API
**********************************************************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif
/*!
* @brief Calls initialization functions.
*
*/
void BOARD_InitBootPins(void);
/* GPIO_AD_B0_09 (coord F14), JTAG_TDI/J21[5]/ENET_RST/J22[5] */
/* Routed pin properties */
#define BOARD_INITPINS_USER_LED_PERIPHERAL GPIO1 /*!< Peripheral name */
#define BOARD_INITPINS_USER_LED_SIGNAL gpio_io /*!< Signal name */
#define BOARD_INITPINS_USER_LED_CHANNEL 9U /*!< Signal channel */
/* Symbols to be used with GPIO driver */
#define BOARD_INITPINS_USER_LED_GPIO GPIO1 /*!< GPIO peripheral base pointer */
#define BOARD_INITPINS_USER_LED_GPIO_PIN 9U /*!< GPIO pin number */
#define BOARD_INITPINS_USER_LED_GPIO_PIN_MASK (1U << 9U) /*!< GPIO pin mask */
#define BOARD_INITPINS_USER_LED_PORT GPIO1 /*!< PORT peripheral base pointer */
#define BOARD_INITPINS_USER_LED_PIN 9U /*!< PORT pin number */
#define BOARD_INITPINS_USER_LED_PIN_MASK (1U << 9U) /*!< PORT pin mask */
/* WAKEUP (coord L6), SD_PWREN */
/* Routed pin properties */
#define BOARD_INITPINS_USER_BUTTON_PERIPHERAL GPIO5 /*!< Peripheral name */
#define BOARD_INITPINS_USER_BUTTON_SIGNAL gpio_io /*!< Signal name */
#define BOARD_INITPINS_USER_BUTTON_CHANNEL 0U /*!< Signal channel */
/* Symbols to be used with GPIO driver */
#define BOARD_INITPINS_USER_BUTTON_GPIO GPIO5 /*!< GPIO peripheral base pointer */
#define BOARD_INITPINS_USER_BUTTON_GPIO_PIN 0U /*!< GPIO pin number */
#define BOARD_INITPINS_USER_BUTTON_GPIO_PIN_MASK (1U << 0U) /*!< GPIO pin mask */
#define BOARD_INITPINS_USER_BUTTON_PORT GPIO5 /*!< PORT peripheral base pointer */
#define BOARD_INITPINS_USER_BUTTON_PIN 0U /*!< PORT pin number */
#define BOARD_INITPINS_USER_BUTTON_PIN_MASK (1U << 0U) /*!< PORT pin mask */
/*!
* @brief Configures pin routing and optionally pin electrical features.
*
*/
void BOARD_InitPins(void);
/* GPIO_AD_B0_12 (coord K14), UART1_TXD */
/* Routed pin properties */
#define BOARD_INITDEBUG_UARTPINS_UART1_TXD_PERIPHERAL LPUART1 /*!< Peripheral name */
#define BOARD_INITDEBUG_UARTPINS_UART1_TXD_SIGNAL TX /*!< Signal name */
/* GPIO_AD_B0_13 (coord L14), UART1_RXD */
/* Routed pin properties */
#define BOARD_INITDEBUG_UARTPINS_UART1_RXD_PERIPHERAL LPUART1 /*!< Peripheral name */
#define BOARD_INITDEBUG_UARTPINS_UART1_RXD_SIGNAL RX /*!< Signal name */
/*!
* @brief Configures pin routing and optionally pin electrical features.
*
*/
void BOARD_InitDEBUG_UARTPins(void);
/* GPIO_EMC_09 (coord C2), SEMC_A0 */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_A0_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_A0_SIGNAL ADDR /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_A0_CHANNEL 0U /*!< Signal channel */
/* GPIO_EMC_10 (coord G1), SEMC_A1 */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_A1_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_A1_SIGNAL ADDR /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_A1_CHANNEL 1U /*!< Signal channel */
/* GPIO_EMC_11 (coord G3), SEMC_A2 */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_A2_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_A2_SIGNAL ADDR /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_A2_CHANNEL 2U /*!< Signal channel */
/* GPIO_EMC_12 (coord H1), SEMC_A3 */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_A3_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_A3_SIGNAL ADDR /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_A3_CHANNEL 3U /*!< Signal channel */
/* GPIO_EMC_13 (coord A6), SEMC_A4 */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_A4_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_A4_SIGNAL ADDR /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_A4_CHANNEL 4U /*!< Signal channel */
/* GPIO_EMC_14 (coord B6), SEMC_A5 */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_A5_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_A5_SIGNAL ADDR /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_A5_CHANNEL 5U /*!< Signal channel */
/* GPIO_EMC_15 (coord B1), SEMC_A6 */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_A6_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_A6_SIGNAL ADDR /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_A6_CHANNEL 6U /*!< Signal channel */
/* GPIO_EMC_16 (coord A5), SEMC_A7 */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_A7_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_A7_SIGNAL ADDR /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_A7_CHANNEL 7U /*!< Signal channel */
/* GPIO_EMC_17 (coord A4), SEMC_A8 */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_A8_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_A8_SIGNAL ADDR /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_A8_CHANNEL 8U /*!< Signal channel */
/* GPIO_EMC_18 (coord B2), SEMC_A9 */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_A9_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_A9_SIGNAL ADDR /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_A9_CHANNEL 9U /*!< Signal channel */
/* GPIO_EMC_23 (coord G2), SEMC_A10 */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_A10_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_A10_SIGNAL ADDR /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_A10_CHANNEL 10U /*!< Signal channel */
/* GPIO_EMC_19 (coord B4), SEMC_A11 */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_A11_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_A11_SIGNAL ADDR /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_A11_CHANNEL 11U /*!< Signal channel */
/* GPIO_EMC_20 (coord A3), SEMC_A12 */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_A12_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_A12_SIGNAL ADDR /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_A12_CHANNEL 12U /*!< Signal channel */
/* GPIO_EMC_21 (coord C1), SEMC_BA0 */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_BA0_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_BA0_SIGNAL BA /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_BA0_CHANNEL 0U /*!< Signal channel */
/* GPIO_EMC_22 (coord F1), SEMC_BA1 */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_BA1_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_BA1_SIGNAL BA /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_BA1_CHANNEL 1U /*!< Signal channel */
/* GPIO_EMC_24 (coord D3), SEMC_CAS */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_CAS_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_CAS_SIGNAL semc_cas /*!< Signal name */
/* GPIO_EMC_27 (coord A2), SEMC_CKE */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_CKE_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_CKE_SIGNAL semc_cke /*!< Signal name */
/* GPIO_EMC_26 (coord B3), SEMC_CLK */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_CLK_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_CLK_SIGNAL semc_clk /*!< Signal name */
/* GPIO_EMC_00 (coord E3), SEMC_D0 */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_D0_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_D0_SIGNAL DATA /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_D0_CHANNEL 0U /*!< Signal channel */
/* GPIO_EMC_01 (coord F3), SEMC_D1 */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_D1_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_D1_SIGNAL DATA /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_D1_CHANNEL 1U /*!< Signal channel */
/* GPIO_EMC_02 (coord F4), SEMC_D2 */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_D2_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_D2_SIGNAL DATA /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_D2_CHANNEL 2U /*!< Signal channel */
/* GPIO_EMC_03 (coord G4), SEMC_D3 */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_D3_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_D3_SIGNAL DATA /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_D3_CHANNEL 3U /*!< Signal channel */
/* GPIO_EMC_04 (coord F2), SEMC_D4 */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_D4_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_D4_SIGNAL DATA /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_D4_CHANNEL 4U /*!< Signal channel */
/* GPIO_EMC_05 (coord G5), SEMC_D5 */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_D5_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_D5_SIGNAL DATA /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_D5_CHANNEL 5U /*!< Signal channel */
/* GPIO_EMC_06 (coord H5), SEMC_D6 */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_D6_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_D6_SIGNAL DATA /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_D6_CHANNEL 6U /*!< Signal channel */
/* GPIO_EMC_07 (coord H4), SEMC_D7 */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_D7_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_D7_SIGNAL DATA /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_D7_CHANNEL 7U /*!< Signal channel */
/* GPIO_EMC_30 (coord C6), SEMC_D8 */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_D8_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_D8_SIGNAL DATA /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_D8_CHANNEL 8U /*!< Signal channel */
/* GPIO_EMC_31 (coord C5), SEMC_D9 */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_D9_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_D9_SIGNAL DATA /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_D9_CHANNEL 9U /*!< Signal channel */
/* GPIO_EMC_32 (coord D5), SEMC_D10 */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_D10_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_D10_SIGNAL DATA /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_D10_CHANNEL 10U /*!< Signal channel */
/* GPIO_EMC_33 (coord C4), SEMC_D11 */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_D11_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_D11_SIGNAL DATA /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_D11_CHANNEL 11U /*!< Signal channel */
/* GPIO_EMC_34 (coord D4), SEMC_D12 */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_D12_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_D12_SIGNAL DATA /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_D12_CHANNEL 12U /*!< Signal channel */
/* GPIO_EMC_35 (coord E5), SEMC_D13 */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_D13_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_D13_SIGNAL DATA /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_D13_CHANNEL 13U /*!< Signal channel */
/* GPIO_EMC_36 (coord C3), SEMC_D14 */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_D14_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_D14_SIGNAL DATA /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_D14_CHANNEL 14U /*!< Signal channel */
/* GPIO_EMC_37 (coord E4), SEMC_D15 */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_D15_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_D15_SIGNAL DATA /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_D15_CHANNEL 15U /*!< Signal channel */
/* GPIO_EMC_08 (coord H3), SEMC_DM0 */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_DM0_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_DM0_SIGNAL DM /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_DM0_CHANNEL 0U /*!< Signal channel */
/* GPIO_EMC_38 (coord D6), SEMC_DM1 */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_DM1_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_DM1_SIGNAL DM /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_DM1_CHANNEL 1U /*!< Signal channel */
/* GPIO_EMC_25 (coord D2), SEMC_RAS */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_RAS_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_RAS_SIGNAL semc_ras /*!< Signal name */
/* GPIO_EMC_28 (coord D1), SEMC_WE */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_WE_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_WE_SIGNAL semc_we /*!< Signal name */
/* GPIO_EMC_41 (coord C7), ENET_MDIO */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_ENET_MDIO_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_ENET_MDIO_SIGNAL CSX /*!< Signal name */
#define BOARD_INITSDRAMPINS_ENET_MDIO_CHANNEL 0U /*!< Signal channel */
/*!
* @brief Configures pin routing and optionally pin electrical features.
*
*/
void BOARD_InitSDRAMPins(void);
/* GPIO_AD_B1_08 (coord H13), AUD_INT/CSI_D9//J35[13]/J22[4] */
/* Routed pin properties */
#define BOARD_INITCSIPINS_CSI_D9_PERIPHERAL CSI /*!< Peripheral name */
#define BOARD_INITCSIPINS_CSI_D9_SIGNAL csi_data /*!< Signal name */
#define BOARD_INITCSIPINS_CSI_D9_CHANNEL 9U /*!< Signal channel */
/* GPIO_AD_B1_09 (coord M13), SAI1_MCLK/CSI_D8/J35[11] */
/* Routed pin properties */
#define BOARD_INITCSIPINS_CSI_D8_PERIPHERAL CSI /*!< Peripheral name */
#define BOARD_INITCSIPINS_CSI_D8_SIGNAL csi_data /*!< Signal name */
#define BOARD_INITCSIPINS_CSI_D8_CHANNEL 8U /*!< Signal channel */
/* GPIO_AD_B1_10 (coord L13), SAI1_RX_SYNC/CSI_D7/J35[9]/J23[1] */
/* Routed pin properties */
#define BOARD_INITCSIPINS_CSI_D7_PERIPHERAL CSI /*!< Peripheral name */
#define BOARD_INITCSIPINS_CSI_D7_SIGNAL csi_data /*!< Signal name */
#define BOARD_INITCSIPINS_CSI_D7_CHANNEL 7U /*!< Signal channel */
/* GPIO_AD_B1_11 (coord J13), SAI1_RX_BCLK/CSI_D6/J35[7]/J23[2] */
/* Routed pin properties */
#define BOARD_INITCSIPINS_CSI_D6_PERIPHERAL CSI /*!< Peripheral name */
#define BOARD_INITCSIPINS_CSI_D6_SIGNAL csi_data /*!< Signal name */
#define BOARD_INITCSIPINS_CSI_D6_CHANNEL 6U /*!< Signal channel */
/* GPIO_AD_B1_12 (coord H12), SAI1_RXD/CSI_D5/J35[5]/U13[16] */
/* Routed pin properties */
#define BOARD_INITCSIPINS_CSI_D5_PERIPHERAL CSI /*!< Peripheral name */
#define BOARD_INITCSIPINS_CSI_D5_SIGNAL csi_data /*!< Signal name */
#define BOARD_INITCSIPINS_CSI_D5_CHANNEL 5U /*!< Signal channel */
/* GPIO_AD_B1_13 (coord H11), SAI1_TXD/CSI_D4/J35[3]/U13[14] */
/* Routed pin properties */
#define BOARD_INITCSIPINS_CSI_D4_PERIPHERAL CSI /*!< Peripheral name */
#define BOARD_INITCSIPINS_CSI_D4_SIGNAL csi_data /*!< Signal name */
#define BOARD_INITCSIPINS_CSI_D4_CHANNEL 4U /*!< Signal channel */
/* GPIO_AD_B1_15 (coord J14), SAI1_TX_SYNC/CSI_D2/J35[6]/U13[13] */
/* Routed pin properties */
#define BOARD_INITCSIPINS_CSI_D2_PERIPHERAL CSI /*!< Peripheral name */
#define BOARD_INITCSIPINS_CSI_D2_SIGNAL csi_data /*!< Signal name */
#define BOARD_INITCSIPINS_CSI_D2_CHANNEL 2U /*!< Signal channel */
/* GPIO_AD_B1_14 (coord G12), SAI1_TX_BCLK/CSI_D3/J35[4]/U13[12] */
/* Routed pin properties */
#define BOARD_INITCSIPINS_CSI_D3_PERIPHERAL CSI /*!< Peripheral name */
#define BOARD_INITCSIPINS_CSI_D3_SIGNAL csi_data /*!< Signal name */
#define BOARD_INITCSIPINS_CSI_D3_CHANNEL 3U /*!< Signal channel */
/* GPIO_AD_B1_04 (coord L12), CSI_PIXCLK/J35[8]/J23[3] */
/* Routed pin properties */
#define BOARD_INITCSIPINS_CSI_PIXCLK_PERIPHERAL CSI /*!< Peripheral name */
#define BOARD_INITCSIPINS_CSI_PIXCLK_SIGNAL csi_pixclk /*!< Signal name */
/* GPIO_AD_B1_05 (coord K12), CSI_MCLK/J35[12]/J23[4] */
/* Routed pin properties */
#define BOARD_INITCSIPINS_CSI_MCLK_PERIPHERAL CSI /*!< Peripheral name */
#define BOARD_INITCSIPINS_CSI_MCLK_SIGNAL csi_mclk /*!< Signal name */
/* GPIO_AD_B1_06 (coord J12), CSI_VSYNC/J35[18]/J22[2]/UART_TX */
/* Routed pin properties */
#define BOARD_INITCSIPINS_CSI_VSYNC_PERIPHERAL CSI /*!< Peripheral name */
#define BOARD_INITCSIPINS_CSI_VSYNC_SIGNAL csi_vsync /*!< Signal name */
/* GPIO_AD_B1_07 (coord K10), CSI_HSYNC/J35[16]/J22[1]/UART_RX */
/* Routed pin properties */
#define BOARD_INITCSIPINS_CSI_HSYNC_PERIPHERAL CSI /*!< Peripheral name */
#define BOARD_INITCSIPINS_CSI_HSYNC_SIGNAL csi_hsync /*!< Signal name */
/* GPIO_AD_B1_00 (coord J11), I2C1_SCL/CSI_I2C_SCL/J35[20]/J23[6]/U13[17]/U32[4] */
/* Routed pin properties */
#define BOARD_INITCSIPINS_CSI_I2C_SCL_PERIPHERAL LPI2C1 /*!< Peripheral name */
#define BOARD_INITCSIPINS_CSI_I2C_SCL_SIGNAL SCL /*!< Signal name */
/* GPIO_AD_B1_01 (coord K11), I2C1_SDA/CSI_I2C_SDA/J35[22]/J23[5]/U13[18]/U32[6] */
/* Routed pin properties */
#define BOARD_INITCSIPINS_CSI_I2C_SDA_PERIPHERAL LPI2C1 /*!< Peripheral name */
#define BOARD_INITCSIPINS_CSI_I2C_SDA_SIGNAL SDA /*!< Signal name */
/* GPIO_AD_B0_04 (coord F11), CSI_PWDN/J35[17]/BOOT_MODE[0] */
/* Routed pin properties */
#define BOARD_INITCSIPINS_CSI_PWDN_PERIPHERAL GPIO1 /*!< Peripheral name */
#define BOARD_INITCSIPINS_CSI_PWDN_SIGNAL gpio_io /*!< Signal name */
#define BOARD_INITCSIPINS_CSI_PWDN_CHANNEL 4U /*!< Signal channel */
/* Symbols to be used with GPIO driver */
#define BOARD_INITCSIPINS_CSI_PWDN_GPIO GPIO1 /*!< GPIO peripheral base pointer */
#define BOARD_INITCSIPINS_CSI_PWDN_GPIO_PIN 4U /*!< GPIO pin number */
#define BOARD_INITCSIPINS_CSI_PWDN_GPIO_PIN_MASK (1U << 4U) /*!< GPIO pin mask */
#define BOARD_INITCSIPINS_CSI_PWDN_PORT GPIO1 /*!< PORT peripheral base pointer */
#define BOARD_INITCSIPINS_CSI_PWDN_PIN 4U /*!< PORT pin number */
#define BOARD_INITCSIPINS_CSI_PWDN_PIN_MASK (1U << 4U) /*!< PORT pin mask */
/*!
* @brief Configures pin routing and optionally pin electrical features.
*
*/
void BOARD_InitCSIPins(void);
/* GPIO_B0_04 (coord C8), LCDIF_D0/BT_CFG[0] */
/* Routed pin properties */
#define BOARD_INITLCDPINS_LCDIF_D0_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITLCDPINS_LCDIF_D0_SIGNAL lcdif_data /*!< Signal name */
#define BOARD_INITLCDPINS_LCDIF_D0_CHANNEL 0U /*!< Signal channel */
/* GPIO_B0_05 (coord B8), LCDIF_D1/BT_CFG[1] */
/* Routed pin properties */
#define BOARD_INITLCDPINS_LCDIF_D1_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITLCDPINS_LCDIF_D1_SIGNAL lcdif_data /*!< Signal name */
#define BOARD_INITLCDPINS_LCDIF_D1_CHANNEL 1U /*!< Signal channel */
/* GPIO_B0_06 (coord A8), LCDIF_D2/BT_CFG[2] */
/* Routed pin properties */
#define BOARD_INITLCDPINS_LCDIF_D2_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITLCDPINS_LCDIF_D2_SIGNAL lcdif_data /*!< Signal name */
#define BOARD_INITLCDPINS_LCDIF_D2_CHANNEL 2U /*!< Signal channel */
/* GPIO_B0_00 (coord D7), LCDIF_CLK */
/* Routed pin properties */
#define BOARD_INITLCDPINS_LCDIF_CLK_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITLCDPINS_LCDIF_CLK_SIGNAL lcdif_clk /*!< Signal name */
/* GPIO_B0_07 (coord A9), LCDIF_D3/BT_CFG[3] */
/* Routed pin properties */
#define BOARD_INITLCDPINS_LCDIF_D3_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITLCDPINS_LCDIF_D3_SIGNAL lcdif_data /*!< Signal name */
#define BOARD_INITLCDPINS_LCDIF_D3_CHANNEL 3U /*!< Signal channel */
/* GPIO_B0_08 (coord B9), LCDIF_D4/BT_CFG[4] */
/* Routed pin properties */
#define BOARD_INITLCDPINS_LCDIF_D4_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITLCDPINS_LCDIF_D4_SIGNAL lcdif_data /*!< Signal name */
#define BOARD_INITLCDPINS_LCDIF_D4_CHANNEL 4U /*!< Signal channel */
/* GPIO_B0_09 (coord C9), LCDIF_D5/BT_CFG[5] */
/* Routed pin properties */
#define BOARD_INITLCDPINS_LCDIF_D5_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITLCDPINS_LCDIF_D5_SIGNAL lcdif_data /*!< Signal name */
#define BOARD_INITLCDPINS_LCDIF_D5_CHANNEL 5U /*!< Signal channel */
/* GPIO_B0_10 (coord D9), LCDIF_D6/BT_CFG[6] */
/* Routed pin properties */
#define BOARD_INITLCDPINS_LCDIF_D6_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITLCDPINS_LCDIF_D6_SIGNAL lcdif_data /*!< Signal name */
#define BOARD_INITLCDPINS_LCDIF_D6_CHANNEL 6U /*!< Signal channel */
/* GPIO_B0_11 (coord A10), LCDIF_D7/BT_CFG[7] */
/* Routed pin properties */
#define BOARD_INITLCDPINS_LCDIF_D7_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITLCDPINS_LCDIF_D7_SIGNAL lcdif_data /*!< Signal name */
#define BOARD_INITLCDPINS_LCDIF_D7_CHANNEL 7U /*!< Signal channel */
/* GPIO_B0_12 (coord C10), LCDIF_D8/BT_CFG[8] */
/* Routed pin properties */
#define BOARD_INITLCDPINS_LCDIF_D8_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITLCDPINS_LCDIF_D8_SIGNAL lcdif_data /*!< Signal name */
#define BOARD_INITLCDPINS_LCDIF_D8_CHANNEL 8U /*!< Signal channel */
/* GPIO_B0_13 (coord D10), LCDIF_D9/BT_CFG[9] */
/* Routed pin properties */
#define BOARD_INITLCDPINS_LCDIF_D9_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITLCDPINS_LCDIF_D9_SIGNAL lcdif_data /*!< Signal name */
#define BOARD_INITLCDPINS_LCDIF_D9_CHANNEL 9U /*!< Signal channel */
/* GPIO_B0_14 (coord E10), LCDIF_D10/BT_CFG[10] */
/* Routed pin properties */
#define BOARD_INITLCDPINS_LCDIF_D10_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITLCDPINS_LCDIF_D10_SIGNAL lcdif_data /*!< Signal name */
#define BOARD_INITLCDPINS_LCDIF_D10_CHANNEL 10U /*!< Signal channel */
/* GPIO_B0_15 (coord E11), LCDIF_D11/BT_CFG[11] */
/* Routed pin properties */
#define BOARD_INITLCDPINS_LCDIF_D11_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITLCDPINS_LCDIF_D11_SIGNAL lcdif_data /*!< Signal name */
#define BOARD_INITLCDPINS_LCDIF_D11_CHANNEL 11U /*!< Signal channel */
/* GPIO_B1_00 (coord A11), LCDIF_D12 */
/* Routed pin properties */
#define BOARD_INITLCDPINS_LCDIF_D12_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITLCDPINS_LCDIF_D12_SIGNAL lcdif_data /*!< Signal name */
#define BOARD_INITLCDPINS_LCDIF_D12_CHANNEL 12U /*!< Signal channel */
/* GPIO_B1_01 (coord B11), LCDIF_D13 */
/* Routed pin properties */
#define BOARD_INITLCDPINS_LCDIF_D13_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITLCDPINS_LCDIF_D13_SIGNAL lcdif_data /*!< Signal name */
#define BOARD_INITLCDPINS_LCDIF_D13_CHANNEL 13U /*!< Signal channel */
/* GPIO_B1_02 (coord C11), LCDIF_D14 */
/* Routed pin properties */
#define BOARD_INITLCDPINS_LCDIF_D14_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITLCDPINS_LCDIF_D14_SIGNAL lcdif_data /*!< Signal name */
#define BOARD_INITLCDPINS_LCDIF_D14_CHANNEL 14U /*!< Signal channel */
/* GPIO_B1_03 (coord D11), LCDIF_D15 */
/* Routed pin properties */
#define BOARD_INITLCDPINS_LCDIF_D15_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITLCDPINS_LCDIF_D15_SIGNAL lcdif_data /*!< Signal name */
#define BOARD_INITLCDPINS_LCDIF_D15_CHANNEL 15U /*!< Signal channel */
/* GPIO_B0_01 (coord E7), LCDIF_ENABLE */
/* Routed pin properties */
#define BOARD_INITLCDPINS_LCDIF_ENABLE_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITLCDPINS_LCDIF_ENABLE_SIGNAL lcdif_enable /*!< Signal name */
/* GPIO_B0_02 (coord E8), LCDIF_HSYNC */
/* Routed pin properties */
#define BOARD_INITLCDPINS_LCDIF_HSYNC_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITLCDPINS_LCDIF_HSYNC_SIGNAL lcdif_hsync /*!< Signal name */
/* GPIO_B0_03 (coord D8), LCDIF_VSYNC */
/* Routed pin properties */
#define BOARD_INITLCDPINS_LCDIF_VSYNC_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITLCDPINS_LCDIF_VSYNC_SIGNAL lcdif_vsync /*!< Signal name */
/* GPIO_B1_15 (coord B14), USB_HOST_PWR/BACKLIGHT_CTL */
/* Routed pin properties */
#define BOARD_INITLCDPINS_BACKLIGHT_CTL_PERIPHERAL GPIO2 /*!< Peripheral name */
#define BOARD_INITLCDPINS_BACKLIGHT_CTL_SIGNAL gpio_io /*!< Signal name */
#define BOARD_INITLCDPINS_BACKLIGHT_CTL_CHANNEL 31U /*!< Signal channel */
/* Symbols to be used with GPIO driver */
#define BOARD_INITLCDPINS_BACKLIGHT_CTL_GPIO GPIO2 /*!< GPIO peripheral base pointer */
#define BOARD_INITLCDPINS_BACKLIGHT_CTL_GPIO_PIN 31U /*!< GPIO pin number */
#define BOARD_INITLCDPINS_BACKLIGHT_CTL_GPIO_PIN_MASK (1U << 31U) /*!< GPIO pin mask */
#define BOARD_INITLCDPINS_BACKLIGHT_CTL_PORT GPIO2 /*!< PORT peripheral base pointer */
#define BOARD_INITLCDPINS_BACKLIGHT_CTL_PIN 31U /*!< PORT pin number */
#define BOARD_INITLCDPINS_BACKLIGHT_CTL_PIN_MASK (1U << 31U) /*!< PORT pin mask */
/*!
* @brief Configures pin routing and optionally pin electrical features.
*
*/
void BOARD_InitLCDPins(void);
/* GPIO_AD_B0_14 (coord H14), CAN2_TX/U12[1] */
/* Routed pin properties */
#define BOARD_INITCANPINS_CAN2_TX_PERIPHERAL CAN2 /*!< Peripheral name */
#define BOARD_INITCANPINS_CAN2_TX_SIGNAL TX /*!< Signal name */
/* GPIO_AD_B0_15 (coord L10), CAN2_RX/U12[4] */
/* Routed pin properties */
#define BOARD_INITCANPINS_CAN2_RX_PERIPHERAL CAN2 /*!< Peripheral name */
#define BOARD_INITCANPINS_CAN2_RX_SIGNAL RX /*!< Signal name */
/*!
* @brief Configures pin routing and optionally pin electrical features.
*
*/
void BOARD_InitCANPins(void);
/* GPIO_EMC_40 (coord A7), ENET_MDC */
/* Routed pin properties */
#define BOARD_INITENETPINS_ENET_MDC_PERIPHERAL ENET /*!< Peripheral name */
#define BOARD_INITENETPINS_ENET_MDC_SIGNAL enet_mdc /*!< Signal name */
/* GPIO_EMC_41 (coord C7), ENET_MDIO */
/* Routed pin properties */
#define BOARD_INITENETPINS_ENET_MDIO_PERIPHERAL ENET /*!< Peripheral name */
#define BOARD_INITENETPINS_ENET_MDIO_SIGNAL enet_mdio /*!< Signal name */
/* GPIO_B1_10 (coord B13), ENET_TX_CLK */
/* Routed pin properties */
#define BOARD_INITENETPINS_ENET_TX_CLK_PERIPHERAL ENET /*!< Peripheral name */
#define BOARD_INITENETPINS_ENET_TX_CLK_SIGNAL enet_ref_clk /*!< Signal name */
/* GPIO_B1_04 (coord E12), ENET_RXD0 */
/* Routed pin properties */
#define BOARD_INITENETPINS_ENET_RXD0_PERIPHERAL ENET /*!< Peripheral name */
#define BOARD_INITENETPINS_ENET_RXD0_SIGNAL enet_rx_data /*!< Signal name */
#define BOARD_INITENETPINS_ENET_RXD0_CHANNEL 0U /*!< Signal channel */
/* GPIO_B1_05 (coord D12), ENET_RXD1 */
/* Routed pin properties */
#define BOARD_INITENETPINS_ENET_RXD1_PERIPHERAL ENET /*!< Peripheral name */
#define BOARD_INITENETPINS_ENET_RXD1_SIGNAL enet_rx_data /*!< Signal name */
#define BOARD_INITENETPINS_ENET_RXD1_CHANNEL 1U /*!< Signal channel */
/* GPIO_B1_06 (coord C12), ENET_CRS_DV */
/* Routed pin properties */
#define BOARD_INITENETPINS_ENET_CRS_DV_PERIPHERAL ENET /*!< Peripheral name */
#define BOARD_INITENETPINS_ENET_CRS_DV_SIGNAL enet_rx_en /*!< Signal name */
/* GPIO_B1_11 (coord C13), ENET_RXER */
/* Routed pin properties */
#define BOARD_INITENETPINS_ENET_RXER_PERIPHERAL ENET /*!< Peripheral name */
#define BOARD_INITENETPINS_ENET_RXER_SIGNAL enet_rx_er /*!< Signal name */
/* GPIO_B1_07 (coord B12), ENET_TXD0 */
/* Routed pin properties */
#define BOARD_INITENETPINS_ENET_TXD0_PERIPHERAL ENET /*!< Peripheral name */
#define BOARD_INITENETPINS_ENET_TXD0_SIGNAL enet_tx_data /*!< Signal name */
#define BOARD_INITENETPINS_ENET_TXD0_CHANNEL 0U /*!< Signal channel */
/* GPIO_B1_08 (coord A12), ENET_TXD1 */
/* Routed pin properties */
#define BOARD_INITENETPINS_ENET_TXD1_PERIPHERAL ENET /*!< Peripheral name */
#define BOARD_INITENETPINS_ENET_TXD1_SIGNAL enet_tx_data /*!< Signal name */
#define BOARD_INITENETPINS_ENET_TXD1_CHANNEL 1U /*!< Signal channel */
/* GPIO_B1_09 (coord A13), ENET_TXEN */
/* Routed pin properties */
#define BOARD_INITENETPINS_ENET_TXEN_PERIPHERAL ENET /*!< Peripheral name */
#define BOARD_INITENETPINS_ENET_TXEN_SIGNAL enet_tx_en /*!< Signal name */
/*!
* @brief Configures pin routing and optionally pin electrical features.
*
*/
void BOARD_InitENETPins(void);
/* GPIO_SD_B0_05 (coord J2), SD1_D3 */
/* Routed pin properties */
#define BOARD_INITUSDHCPINS_SD1_D3_PERIPHERAL USDHC1 /*!< Peripheral name */
#define BOARD_INITUSDHCPINS_SD1_D3_SIGNAL usdhc_data /*!< Signal name */
#define BOARD_INITUSDHCPINS_SD1_D3_CHANNEL 3U /*!< Signal channel */
/* GPIO_SD_B0_04 (coord H2), SD1_D2 */
/* Routed pin properties */
#define BOARD_INITUSDHCPINS_SD1_D2_PERIPHERAL USDHC1 /*!< Peripheral name */
#define BOARD_INITUSDHCPINS_SD1_D2_SIGNAL usdhc_data /*!< Signal name */
#define BOARD_INITUSDHCPINS_SD1_D2_CHANNEL 2U /*!< Signal channel */
/* GPIO_SD_B0_03 (coord K1), SD1_D1/J24[5]/SPI_MISO */
/* Routed pin properties */
#define BOARD_INITUSDHCPINS_SD1_D1_PERIPHERAL USDHC1 /*!< Peripheral name */
#define BOARD_INITUSDHCPINS_SD1_D1_SIGNAL usdhc_data /*!< Signal name */
#define BOARD_INITUSDHCPINS_SD1_D1_CHANNEL 1U /*!< Signal channel */
/* GPIO_SD_B0_02 (coord J1), SD1_D0/J24[4]/SPI_MOSI/PWM */
/* Routed pin properties */
#define BOARD_INITUSDHCPINS_SD1_D0_PERIPHERAL USDHC1 /*!< Peripheral name */
#define BOARD_INITUSDHCPINS_SD1_D0_SIGNAL usdhc_data /*!< Signal name */
#define BOARD_INITUSDHCPINS_SD1_D0_CHANNEL 0U /*!< Signal channel */
/* GPIO_SD_B0_00 (coord J4), SD1_CMD/J24[6] */
/* Routed pin properties */
#define BOARD_INITUSDHCPINS_SD1_CMD_PERIPHERAL USDHC1 /*!< Peripheral name */
#define BOARD_INITUSDHCPINS_SD1_CMD_SIGNAL usdhc_cmd /*!< Signal name */
/* GPIO_SD_B0_01 (coord J3), SD1_CLK/J24[3] */
/* Routed pin properties */
#define BOARD_INITUSDHCPINS_SD1_CLK_PERIPHERAL USDHC1 /*!< Peripheral name */
#define BOARD_INITUSDHCPINS_SD1_CLK_SIGNAL usdhc_clk /*!< Signal name */
/*!
* @brief Configures pin routing and optionally pin electrical features.
*
*/
void BOARD_InitUSDHCPins(void);
/* GPIO_SD_B1_07 (coord L4), FlexSPI_CLK */
/* Routed pin properties */
#define BOARD_INITHYPERFLASHPINS_FlexSPI_CLK_PERIPHERAL FLEXSPI /*!< Peripheral name */
#define BOARD_INITHYPERFLASHPINS_FlexSPI_CLK_SIGNAL FLEXSPI_A_SCLK /*!< Signal name */
/* GPIO_SD_B1_10 (coord P4), FlexSPI_D2_A */
/* Routed pin properties */
#define BOARD_INITHYPERFLASHPINS_FlexSPI_D2_A_PERIPHERAL FLEXSPI /*!< Peripheral name */
#define BOARD_INITHYPERFLASHPINS_FlexSPI_D2_A_SIGNAL FLEXSPI_A_DATA2 /*!< Signal name */
/* GPIO_SD_B1_08 (coord P3), FlexSPI_D0_A */
/* Routed pin properties */
#define BOARD_INITHYPERFLASHPINS_FlexSPI_D0_A_PERIPHERAL FLEXSPI /*!< Peripheral name */
#define BOARD_INITHYPERFLASHPINS_FlexSPI_D0_A_SIGNAL FLEXSPI_A_DATA0 /*!< Signal name */
/* GPIO_SD_B1_09 (coord N4), FlexSPI_D1_A */
/* Routed pin properties */
#define BOARD_INITHYPERFLASHPINS_FlexSPI_D1_A_PERIPHERAL FLEXSPI /*!< Peripheral name */
#define BOARD_INITHYPERFLASHPINS_FlexSPI_D1_A_SIGNAL FLEXSPI_A_DATA1 /*!< Signal name */
/* GPIO_SD_B1_00 (coord L5), FlexSPI_D3_B */
/* Routed pin properties */
#define BOARD_INITHYPERFLASHPINS_FlexSPI_D3_B_PERIPHERAL FLEXSPI /*!< Peripheral name */
#define BOARD_INITHYPERFLASHPINS_FlexSPI_D3_B_SIGNAL FLEXSPI_B_DATA3 /*!< Signal name */
/* GPIO_SD_B1_01 (coord M5), FlexSPI_D2_B */
/* Routed pin properties */
#define BOARD_INITHYPERFLASHPINS_FlexSPI_D2_B_PERIPHERAL FLEXSPI /*!< Peripheral name */
#define BOARD_INITHYPERFLASHPINS_FlexSPI_D2_B_SIGNAL FLEXSPI_B_DATA2 /*!< Signal name */
/* GPIO_SD_B1_02 (coord M3), FlexSPI_D1_B */
/* Routed pin properties */
#define BOARD_INITHYPERFLASHPINS_FlexSPI_D1_B_PERIPHERAL FLEXSPI /*!< Peripheral name */
#define BOARD_INITHYPERFLASHPINS_FlexSPI_D1_B_SIGNAL FLEXSPI_B_DATA1 /*!< Signal name */
/* GPIO_SD_B1_03 (coord M4), FlexSPI_D0_B */
/* Routed pin properties */
#define BOARD_INITHYPERFLASHPINS_FlexSPI_D0_B_PERIPHERAL FLEXSPI /*!< Peripheral name */
#define BOARD_INITHYPERFLASHPINS_FlexSPI_D0_B_SIGNAL FLEXSPI_B_DATA0 /*!< Signal name */
/* GPIO_SD_B1_04 (coord P2), FlexSPI_CLK_B */
/* Routed pin properties */
#define BOARD_INITHYPERFLASHPINS_FlexSPI_CLK_B_PERIPHERAL FLEXSPI /*!< Peripheral name */
#define BOARD_INITHYPERFLASHPINS_FlexSPI_CLK_B_SIGNAL FLEXSPI_B_SCLK /*!< Signal name */
/* GPIO_SD_B1_06 (coord L3), FlexSPI_SS0 */
/* Routed pin properties */
#define BOARD_INITHYPERFLASHPINS_FlexSPI_SS0_PERIPHERAL FLEXSPI /*!< Peripheral name */
#define BOARD_INITHYPERFLASHPINS_FlexSPI_SS0_SIGNAL FLEXSPI_A_SS0_B /*!< Signal name */
/* GPIO_SD_B1_11 (coord P5), FlexSPI_D3_A */
/* Routed pin properties */
#define BOARD_INITHYPERFLASHPINS_FlexSPI_D3_A_PERIPHERAL FLEXSPI /*!< Peripheral name */
#define BOARD_INITHYPERFLASHPINS_FlexSPI_D3_A_SIGNAL FLEXSPI_A_DATA3 /*!< Signal name */
/* GPIO_SD_B1_05 (coord N3), FlexSPI_DQS */
/* Routed pin properties */
#define BOARD_INITHYPERFLASHPINS_FlexSPI_DQS_PERIPHERAL FLEXSPI /*!< Peripheral name */
#define BOARD_INITHYPERFLASHPINS_FlexSPI_DQS_SIGNAL FLEXSPI_A_DQS /*!< Signal name */
/*!
* @brief Configures pin routing and optionally pin electrical features.
*
*/
void BOARD_InitHyperFlashPins(void);
#if defined(__cplusplus)
}
#endif
/*!
* @}
*/
#endif /* _PIN_MUX_H_ */
/***********************************************************************************************************************
* EOF
**********************************************************************************************************************/

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managed_components/espressif__tinyusb/hw/bsp/imxrt/boards/mimxrt1050_evkb/evkbimxrt1050_flexspi_nor_config.c Normal file
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/*
* Copyright 2017 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "evkbimxrt1050_flexspi_nor_config.h"
/* Component ID definition, used by tools. */
#ifndef FSL_COMPONENT_ID
#define FSL_COMPONENT_ID "platform.drivers.xip_board"
#endif
/*******************************************************************************
* Code
******************************************************************************/
#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
__attribute__((section(".boot_hdr.conf")))
#elif defined(__ICCARM__)
#pragma location = ".boot_hdr.conf"
#endif
const flexspi_nor_config_t hyperflash_config = {
.memConfig =
{
.tag = FLEXSPI_CFG_BLK_TAG,
.version = FLEXSPI_CFG_BLK_VERSION,
.readSampleClkSrc = kFlexSPIReadSampleClk_ExternalInputFromDqsPad,
.csHoldTime = 3u,
.csSetupTime = 3u,
.columnAddressWidth = 3u,
// Enable DDR mode, Wordaddassable, Safe configuration, Differential clock
.controllerMiscOption =
(1u << kFlexSpiMiscOffset_DdrModeEnable) | (1u << kFlexSpiMiscOffset_WordAddressableEnable) |
(1u << kFlexSpiMiscOffset_SafeConfigFreqEnable) | (1u << kFlexSpiMiscOffset_DiffClkEnable),
.sflashPadType = kSerialFlash_8Pads,
.serialClkFreq = kFlexSpiSerialClk_133MHz,
.sflashA1Size = 64u * 1024u * 1024u,
.dataValidTime = {16u, 16u},
.lookupTable =
{
// Read LUTs
FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0xA0, RADDR_DDR, FLEXSPI_8PAD, 0x18),
FLEXSPI_LUT_SEQ(CADDR_DDR, FLEXSPI_8PAD, 0x10, DUMMY_DDR, FLEXSPI_8PAD, 0x06),
FLEXSPI_LUT_SEQ(READ_DDR, FLEXSPI_8PAD, 0x04, STOP, FLEXSPI_1PAD, 0x0),
},
},
.pageSize = 512u,
.sectorSize = 256u * 1024u,
.blockSize = 256u * 1024u,
.isUniformBlockSize = true,
};
#endif /* XIP_BOOT_HEADER_ENABLE */

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/*
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __EVKBIMXRT1050_FLEXSPI_NOR_CONFIG__
#define __EVKBIMXRT1050_FLEXSPI_NOR_CONFIG__
#include <stdint.h>
#include <stdbool.h>
#include "fsl_common.h"
/*! @name Driver version */
/*@{*/
/*! @brief XIP_BOARD driver version 2.0.0. */
#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
/*@}*/
/* FLEXSPI memory config block related definitions */
#define FLEXSPI_CFG_BLK_TAG (0x42464346UL) // ascii "FCFB" Big Endian
#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0
#define FLEXSPI_CFG_BLK_SIZE (512)
/* FLEXSPI Feature related definitions */
#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1
/* Lookup table related definitions */
#define CMD_INDEX_READ 0
#define CMD_INDEX_READSTATUS 1
#define CMD_INDEX_WRITEENABLE 2
#define CMD_INDEX_WRITE 4
#define CMD_LUT_SEQ_IDX_READ 0
#define CMD_LUT_SEQ_IDX_READSTATUS 1
#define CMD_LUT_SEQ_IDX_WRITEENABLE 3
#define CMD_LUT_SEQ_IDX_WRITE 9
#define CMD_SDR 0x01
#define CMD_DDR 0x21
#define RADDR_SDR 0x02
#define RADDR_DDR 0x22
#define CADDR_SDR 0x03
#define CADDR_DDR 0x23
#define MODE1_SDR 0x04
#define MODE1_DDR 0x24
#define MODE2_SDR 0x05
#define MODE2_DDR 0x25
#define MODE4_SDR 0x06
#define MODE4_DDR 0x26
#define MODE8_SDR 0x07
#define MODE8_DDR 0x27
#define WRITE_SDR 0x08
#define WRITE_DDR 0x28
#define READ_SDR 0x09
#define READ_DDR 0x29
#define LEARN_SDR 0x0A
#define LEARN_DDR 0x2A
#define DATSZ_SDR 0x0B
#define DATSZ_DDR 0x2B
#define DUMMY_SDR 0x0C
#define DUMMY_DDR 0x2C
#define DUMMY_RWDS_SDR 0x0D
#define DUMMY_RWDS_DDR 0x2D
#define JMP_ON_CS 0x1F
#define STOP 0
#define FLEXSPI_1PAD 0
#define FLEXSPI_2PAD 1
#define FLEXSPI_4PAD 2
#define FLEXSPI_8PAD 3
#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \
(FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \
FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))
//!@brief Definitions for FlexSPI Serial Clock Frequency
typedef enum _FlexSpiSerialClockFreq
{
kFlexSpiSerialClk_30MHz = 1,
kFlexSpiSerialClk_50MHz = 2,
kFlexSpiSerialClk_60MHz = 3,
kFlexSpiSerialClk_75MHz = 4,
kFlexSpiSerialClk_80MHz = 5,
kFlexSpiSerialClk_100MHz = 6,
kFlexSpiSerialClk_133MHz = 7,
kFlexSpiSerialClk_166MHz = 8,
kFlexSpiSerialClk_200MHz = 9,
} flexspi_serial_clk_freq_t;
//!@brief FlexSPI clock configuration type
enum
{
kFlexSpiClk_SDR, //!< Clock configure for SDR mode
kFlexSpiClk_DDR, //!< Clock configurat for DDR mode
};
//!@brief FlexSPI Read Sample Clock Source definition
typedef enum _FlashReadSampleClkSource
{
kFlexSPIReadSampleClk_LoopbackInternally = 0,
kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1,
kFlexSPIReadSampleClk_LoopbackFromSckPad = 2,
kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3,
} flexspi_read_sample_clk_t;
//!@brief Misc feature bit definitions
enum
{
kFlexSpiMiscOffset_DiffClkEnable = 0, //!< Bit for Differential clock enable
kFlexSpiMiscOffset_Ck2Enable = 1, //!< Bit for CK2 enable
kFlexSpiMiscOffset_ParallelEnable = 2, //!< Bit for Parallel mode enable
kFlexSpiMiscOffset_WordAddressableEnable = 3, //!< Bit for Word Addressable enable
kFlexSpiMiscOffset_SafeConfigFreqEnable = 4, //!< Bit for Safe Configuration Frequency enable
kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, //!< Bit for Pad setting override enable
kFlexSpiMiscOffset_DdrModeEnable = 6, //!< Bit for DDR clock confiuration indication.
};
//!@brief Flash Type Definition
enum
{
kFlexSpiDeviceType_SerialNOR = 1, //!< Flash devices are Serial NOR
kFlexSpiDeviceType_SerialNAND = 2, //!< Flash devices are Serial NAND
kFlexSpiDeviceType_SerialRAM = 3, //!< Flash devices are Serial RAM/HyperFLASH
kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND
kFlexSpiDeviceType_MCP_NOR_RAM = 0x13, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial RAMs
};
//!@brief Flash Pad Definitions
enum
{
kSerialFlash_1Pad = 1,
kSerialFlash_2Pads = 2,
kSerialFlash_4Pads = 4,
kSerialFlash_8Pads = 8,
};
//!@brief FlexSPI LUT Sequence structure
typedef struct _lut_sequence
{
uint8_t seqNum; //!< Sequence Number, valid number: 1-16
uint8_t seqId; //!< Sequence Index, valid number: 0-15
uint16_t reserved;
} flexspi_lut_seq_t;
//!@brief Flash Configuration Command Type
enum
{
kDeviceConfigCmdType_Generic, //!< Generic command, for example: configure dummy cycles, drive strength, etc
kDeviceConfigCmdType_QuadEnable, //!< Quad Enable command
kDeviceConfigCmdType_Spi2Xpi, //!< Switch from SPI to DPI/QPI/OPI mode
kDeviceConfigCmdType_Xpi2Spi, //!< Switch from DPI/QPI/OPI to SPI mode
kDeviceConfigCmdType_Spi2NoCmd, //!< Switch to 0-4-4/0-8-8 mode
kDeviceConfigCmdType_Reset, //!< Reset device command
};
//!@brief FlexSPI Memory Configuration Block
typedef struct _FlexSPIConfig
{
uint32_t tag; //!< [0x000-0x003] Tag, fixed value 0x42464346UL
uint32_t version; //!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix
uint32_t reserved0; //!< [0x008-0x00b] Reserved for future use
uint8_t readSampleClkSrc; //!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3
uint8_t csHoldTime; //!< [0x00d-0x00d] CS hold time, default value: 3
uint8_t csSetupTime; //!< [0x00e-0x00e] CS setup time, default value: 3
uint8_t columnAddressWidth; //!< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For
//! Serial NAND, need to refer to datasheet
uint8_t deviceModeCfgEnable; //!< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable
uint8_t deviceModeType; //!< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch,
//! Generic configuration, etc.
uint16_t waitTimeCfgCommands; //!< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for
//! DPI/QPI/OPI switch or reset command
flexspi_lut_seq_t deviceModeSeq; //!< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt
//! sequence number, [31:16] Reserved
uint32_t deviceModeArg; //!< [0x018-0x01b] Argument/Parameter for device configuration
uint8_t configCmdEnable; //!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable
uint8_t configModeType[3]; //!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe
flexspi_lut_seq_t
configCmdSeqs[3]; //!< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq
uint32_t reserved1; //!< [0x02c-0x02f] Reserved for future use
uint32_t configCmdArgs[3]; //!< [0x030-0x03b] Arguments/Parameters for device Configuration commands
uint32_t reserved2; //!< [0x03c-0x03f] Reserved for future use
uint32_t controllerMiscOption; //!< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more
//! details
uint8_t deviceType; //!< [0x044-0x044] Device Type: See Flash Type Definition for more details
uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal
uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequency, device specific definitions, See System Boot
//! Chapter for more details
uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot
//! be done using 1 LUT sequence, currently, only applicable to HyperFLASH
uint32_t reserved3[2]; //!< [0x048-0x04f] Reserved for future use
uint32_t sflashA1Size; //!< [0x050-0x053] Size of Flash connected to A1
uint32_t sflashA2Size; //!< [0x054-0x057] Size of Flash connected to A2
uint32_t sflashB1Size; //!< [0x058-0x05b] Size of Flash connected to B1
uint32_t sflashB2Size; //!< [0x05c-0x05f] Size of Flash connected to B2
uint32_t csPadSettingOverride; //!< [0x060-0x063] CS pad setting override value
uint32_t sclkPadSettingOverride; //!< [0x064-0x067] SCK pad setting override value
uint32_t dataPadSettingOverride; //!< [0x068-0x06b] data pad setting override value
uint32_t dqsPadSettingOverride; //!< [0x06c-0x06f] DQS pad setting override value
uint32_t timeoutInMs; //!< [0x070-0x073] Timeout threshold for read status command
uint32_t commandInterval; //!< [0x074-0x077] CS deselect interval between two commands
uint16_t dataValidTime[2]; //!< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns
uint16_t busyOffset; //!< [0x07c-0x07d] Busy offset, valid value: 0-31
uint16_t busyBitPolarity; //!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 -
//! busy flag is 0 when flash device is busy
uint32_t lookupTable[64]; //!< [0x080-0x17f] Lookup table holds Flash command sequences
flexspi_lut_seq_t lutCustomSeq[12]; //!< [0x180-0x1af] Customizable LUT Sequences
uint32_t reserved4[4]; //!< [0x1b0-0x1bf] Reserved for future use
} flexspi_mem_config_t;
/* */
#define NOR_CMD_INDEX_READ CMD_INDEX_READ //!< 0
#define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS //!< 1
#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE //!< 2
#define NOR_CMD_INDEX_ERASESECTOR 3 //!< 3
#define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE //!< 4
#define NOR_CMD_INDEX_CHIPERASE 5 //!< 5
#define NOR_CMD_INDEX_DUMMY 6 //!< 6
#define NOR_CMD_INDEX_ERASEBLOCK 7 //!< 7
#define NOR_CMD_LUT_SEQ_IDX_READ CMD_LUT_SEQ_IDX_READ //!< 0 READ LUT sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_READSTATUS \
CMD_LUT_SEQ_IDX_READSTATUS //!< 1 Read Status LUT sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \
2 //!< 2 Read status DPI/QPI/OPI sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE \
CMD_LUT_SEQ_IDX_WRITEENABLE //!< 3 Write Enable sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \
4 //!< 4 Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5 //!< 5 Erase Sector sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8 //!< 8 Erase Block sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM \
CMD_LUT_SEQ_IDX_WRITE //!< 9 Program sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11 //!< 11 Chip Erase sequence in lookupTable id stored in config block
#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13 //!< 13 Read SFDP sequence in lookupTable id stored in config block
#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \
14 //!< 14 Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \
15 //!< 15 Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config blobk
/*
* Serial NOR configuration block
*/
typedef struct _flexspi_nor_config
{
flexspi_mem_config_t memConfig; //!< Common memory configuration info via FlexSPI
uint32_t pageSize; //!< Page size of Serial NOR
uint32_t sectorSize; //!< Sector size of Serial NOR
uint8_t ipcmdSerialClkFreq; //!< Clock frequency for IP command
uint8_t isUniformBlockSize; //!< Sector/Block size is the same
uint8_t reserved0[2]; //!< Reserved for future use
uint8_t serialNorType; //!< Serial NOR Flash type: 0/1/2/3
uint8_t needExitNoCmdMode; //!< Need to exit NoCmd mode before other IP command
uint8_t halfClkForNonReadCmd; //!< Half the Serial Clock for non-read command: true/false
uint8_t needRestoreNoCmdMode; //!< Need to Restore NoCmd mode after IP command execution
uint32_t blockSize; //!< Block size
uint32_t reserve2[11]; //!< Reserved for future use
} flexspi_nor_config_t;
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __cplusplus
}
#endif
#endif /* __EVKBIMXRT1050_FLEXSPI_NOR_CONFIG__ */

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17
managed_components/espressif__tinyusb/hw/bsp/imxrt/boards/mimxrt1060_evk/board.cmake Normal file
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set(MCU_VARIANT MIMXRT1062)
set(JLINK_DEVICE MIMXRT1062xxx6A)
#set(JLINK_OPTION "-USB 000726129165")
set(PYOCD_TARGET mimxrt1060)
set(NXPLINK_DEVICE MIMXRT1062xxxxA:EVK-MIMXRT1060)
function(update_board TARGET)
target_sources(${TARGET} PUBLIC
${CMAKE_CURRENT_FUNCTION_LIST_DIR}/evkmimxrt1060_flexspi_nor_config.c
)
target_compile_definitions(${TARGET} PUBLIC
CPU_MIMXRT1062DVL6A
BOARD_TUD_RHPORT=0
BOARD_TUH_RHPORT=1
)
endfunction()

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managed_components/espressif__tinyusb/hw/bsp/imxrt/boards/mimxrt1060_evk/board.h Normal file
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/*
* The MIT License (MIT)
*
* Copyright (c) 2019, Ha Thach (tinyusb.org)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* This file is part of the TinyUSB stack.
*/
/* metadata:
name: i.MX RT1060 Evaluation Kit revB
url: https://www.nxp.com/design/design-center/development-boards-and-designs/MIMXRT1060-EVKB
*/
#ifndef BOARD_MIMXRT1060_EVKB_H_
#define BOARD_MIMXRT1060_EVKB_H_
// required since iMXRT MCUX-SDK include this file for board size
#define BOARD_FLASH_SIZE (0x800000U)
// LED: IOMUXC_GPIO_AD_B0_09_GPIO1_IO09
#define LED_PORT BOARD_INITPINS_USER_LED_PERIPHERAL
#define LED_PIN BOARD_INITPINS_USER_LED_CHANNEL
#define LED_STATE_ON 0
// SW8 button: IOMUXC_SNVS_WAKEUP_GPIO5_IO00
#define BUTTON_PORT BOARD_INITPINS_USER_BUTTON_PERIPHERAL
#define BUTTON_PIN BOARD_INITPINS_USER_BUTTON_CHANNEL
#define BUTTON_STATE_ACTIVE 0
// UART: IOMUXC_GPIO_AD_B0_13_LPUART1_RX, IOMUXC_GPIO_AD_B0_12_LPUART1_TX
#define UART_PORT LPUART1
#define UART_CLK_ROOT BOARD_BOOTCLOCKRUN_UART_CLK_ROOT
static inline void BOARD_ConfigMPU(void) {
}
#endif

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managed_components/espressif__tinyusb/hw/bsp/imxrt/boards/mimxrt1060_evk/board.mk Normal file
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CFLAGS += -DCPU_MIMXRT1062DVL6A
MCU_VARIANT = MIMXRT1062
# For flash-jlink target
JLINK_DEVICE = MIMXRT1062xxx6A
# For flash-pyocd target
PYOCD_TARGET = mimxrt1060
BOARD_TUD_RHPORT = 0
BOARD_TUH_RHPORT = 1
# flash using pyocd
flash: flash-pyocd

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managed_components/espressif__tinyusb/hw/bsp/imxrt/boards/mimxrt1060_evk/board/clock_config.c Normal file
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/*
* How to setup clock using clock driver functions:
*
* 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock.
*
* 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock.
*
* 3. Call CLOCK_SetMux() to configure corresponding clock source for target clock out.
*
* 4. Call CLOCK_SetDiv() to configure corresponding clock divider for target clock out.
*
* 5. Call CLOCK_SetXtalFreq() to set XTAL frequency based on board settings.
*
*/
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!GlobalInfo
product: Clocks v11.0
processor: MIMXRT1062xxxxA
package_id: MIMXRT1062DVL6A
mcu_data: ksdk2_0
processor_version: 13.0.2
board: MIMXRT1060-EVK
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
#include "clock_config.h"
#include "fsl_iomuxc.h"
/*******************************************************************************
* Definitions
******************************************************************************/
/*******************************************************************************
* Variables
******************************************************************************/
/*******************************************************************************
************************ BOARD_InitBootClocks function ************************
******************************************************************************/
void BOARD_InitBootClocks(void)
{
BOARD_BootClockRUN();
}
/*******************************************************************************
********************** Configuration BOARD_BootClockRUN ***********************
******************************************************************************/
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!Configuration
name: BOARD_BootClockRUN
called_from_default_init: true
outputs:
- {id: AHB_CLK_ROOT.outFreq, value: 600 MHz}
- {id: CAN_CLK_ROOT.outFreq, value: 40 MHz}
- {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz}
- {id: CLK_1M.outFreq, value: 1 MHz}
- {id: CLK_24M.outFreq, value: 24 MHz}
- {id: CSI_CLK_ROOT.outFreq, value: 12 MHz}
- {id: ENET2_125M_CLK.outFreq, value: 1.2 MHz}
- {id: ENET_125M_CLK.outFreq, value: 2.4 MHz}
- {id: ENET_25M_REF_CLK.outFreq, value: 1.2 MHz}
- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz}
- {id: FLEXIO2_CLK_ROOT.outFreq, value: 30 MHz}
- {id: FLEXSPI2_CLK_ROOT.outFreq, value: 1440/11 MHz}
- {id: FLEXSPI_CLK_ROOT.outFreq, value: 1440/11 MHz}
- {id: GPT1_ipg_clk_highfreq.outFreq, value: 75 MHz}
- {id: GPT2_ipg_clk_highfreq.outFreq, value: 75 MHz}
- {id: IPG_CLK_ROOT.outFreq, value: 150 MHz}
- {id: LCDIF_CLK_ROOT.outFreq, value: 67.5 MHz}
- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz}
- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz}
- {id: LVDS1_CLK.outFreq, value: 1.2 GHz}
- {id: MQS_MCLK.outFreq, value: 1080/17 MHz}
- {id: PERCLK_CLK_ROOT.outFreq, value: 75 MHz}
- {id: PLL7_MAIN_CLK.outFreq, value: 480 MHz}
- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz}
- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz}
- {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz}
- {id: SAI1_MCLK3.outFreq, value: 30 MHz}
- {id: SAI2_CLK_ROOT.outFreq, value: 1080/17 MHz}
- {id: SAI2_MCLK1.outFreq, value: 1080/17 MHz}
- {id: SAI2_MCLK3.outFreq, value: 30 MHz}
- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz}
- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz}
- {id: SAI3_MCLK3.outFreq, value: 30 MHz}
- {id: SEMC_CLK_ROOT.outFreq, value: 75 MHz}
- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz}
- {id: TRACE_CLK_ROOT.outFreq, value: 132 MHz}
- {id: UART_CLK_ROOT.outFreq, value: 80 MHz}
- {id: USBPHY1_CLK.outFreq, value: 480 MHz}
- {id: USBPHY2_CLK.outFreq, value: 480 MHz}
- {id: USDHC1_CLK_ROOT.outFreq, value: 198 MHz}
- {id: USDHC2_CLK_ROOT.outFreq, value: 198 MHz}
settings:
- {id: CCM.AHB_PODF.scale, value: '1', locked: true}
- {id: CCM.ARM_PODF.scale, value: '2', locked: true}
- {id: CCM.FLEXSPI2_PODF.scale, value: '2', locked: true}
- {id: CCM.FLEXSPI2_SEL.sel, value: CCM_ANALOG.PLL3_PFD0_CLK}
- {id: CCM.FLEXSPI_PODF.scale, value: '2', locked: true}
- {id: CCM.FLEXSPI_SEL.sel, value: CCM_ANALOG.PLL3_PFD0_CLK}
- {id: CCM.LCDIF_PODF.scale, value: '4', locked: true}
- {id: CCM.LCDIF_PRED.scale, value: '2', locked: true}
- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true}
- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true}
- {id: CCM.SEMC_PODF.scale, value: '8'}
- {id: CCM.TRACE_CLK_SEL.sel, value: CCM_ANALOG.PLL2_MAIN_CLK}
- {id: CCM.TRACE_PODF.scale, value: '4', locked: true}
- {id: CCM_ANALOG.PLL1_BYPASS.sel, value: CCM_ANALOG.PLL1}
- {id: CCM_ANALOG.PLL1_PREDIV.scale, value: '1', locked: true}
- {id: CCM_ANALOG.PLL1_VDIV.scale, value: '50', locked: true}
- {id: CCM_ANALOG.PLL2.denom, value: '1', locked: true}
- {id: CCM_ANALOG.PLL2.num, value: '0', locked: true}
- {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK}
- {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0}
- {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1}
- {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2}
- {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3}
- {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3}
- {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0}
- {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '33', locked: true}
- {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true}
- {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1}
- {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2}
- {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3}
- {id: CCM_ANALOG.PLL4.denom, value: '50'}
- {id: CCM_ANALOG.PLL4.div, value: '47'}
- {id: CCM_ANALOG.PLL5.denom, value: '1'}
- {id: CCM_ANALOG.PLL5.div, value: '31', locked: true}
- {id: CCM_ANALOG.PLL5.num, value: '0'}
- {id: CCM_ANALOG.PLL5_BYPASS.sel, value: CCM_ANALOG.PLL5_POST_DIV}
- {id: CCM_ANALOG.PLL5_POST_DIV.scale, value: '2', locked: true}
- {id: CCM_ANALOG.PLL7_BYPASS.sel, value: CCM_ANALOG.PLL7}
- {id: CCM_ANALOG.VIDEO_DIV.scale, value: '4', locked: true}
- {id: CCM_ANALOG_PLL_ENET_POWERDOWN_CFG, value: 'Yes'}
- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_CFG, value: Enabled}
- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_OUT_CFG, value: Enabled}
- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'}
- {id: CCM_ANALOG_PLL_USB2_EN_USB_CLKS_CFG, value: Enabled}
- {id: CCM_ANALOG_PLL_USB2_EN_USB_CLKS_OUT_CFG, value: Enabled}
- {id: CCM_ANALOG_PLL_USB2_POWER_CFG, value: 'Yes'}
- {id: CCM_ANALOG_PLL_VIDEO_POWERDOWN_CFG, value: 'No'}
sources:
- {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/*******************************************************************************
* Variables for BOARD_BootClockRUN configuration
******************************************************************************/
const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN =
{
.loopDivider = 100, /* PLL loop divider, Fout = Fin * 50 */
.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
};
const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN =
{
.loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */
.numerator = 0, /* 30 bit numerator of fractional loop divider */
.denominator = 1, /* 30 bit denominator of fractional loop divider */
.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
};
const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN =
{
.loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */
.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
};
const clock_usb_pll_config_t usb2PllConfig_BOARD_BootClockRUN =
{
.loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */
.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
};
const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN =
{
.loopDivider = 31, /* PLL loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
.postDivider = 8, /* Divider after PLL */
.numerator = 0, /* 30 bit numerator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
.denominator = 1, /* 30 bit denominator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
};
/*******************************************************************************
* Code for BOARD_BootClockRUN configuration
******************************************************************************/
void BOARD_BootClockRUN(void)
{
/* Init RTC OSC clock frequency. */
CLOCK_SetRtcXtalFreq(32768U);
/* Enable 1MHz clock output. */
XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK;
/* Use free 1MHz clock output. */
XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK;
/* Set XTAL 24MHz clock frequency. */
CLOCK_SetXtalFreq(24000000U);
/* Enable XTAL 24MHz clock source. */
CLOCK_InitExternalClk(0);
/* Enable internal RC. */
CLOCK_InitRcOsc24M();
/* Switch clock source to external OSC. */
CLOCK_SwitchOsc(kCLOCK_XtalOsc);
/* Set Oscillator ready counter value. */
CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127);
/* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */
CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */
CLOCK_SetMux(kCLOCK_PeriphMux, 1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */
/* Setting the VDD_SOC to 1.275V. It is necessary to config AHB to 600Mhz. */
DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x13);
/* Waiting for DCDC_STS_DC_OK bit is asserted */
while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0))
{
}
/* Set AHB_PODF. */
CLOCK_SetDiv(kCLOCK_AhbDiv, 0);
/* Disable IPG clock gate. */
CLOCK_DisableClock(kCLOCK_Adc1);
CLOCK_DisableClock(kCLOCK_Adc2);
CLOCK_DisableClock(kCLOCK_Xbar1);
CLOCK_DisableClock(kCLOCK_Xbar2);
CLOCK_DisableClock(kCLOCK_Xbar3);
/* Set IPG_PODF. */
CLOCK_SetDiv(kCLOCK_IpgDiv, 3);
/* Set ARM_PODF. */
CLOCK_SetDiv(kCLOCK_ArmDiv, 1);
/* Set PERIPH_CLK2_PODF. */
CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0);
/* Disable PERCLK clock gate. */
CLOCK_DisableClock(kCLOCK_Gpt1);
CLOCK_DisableClock(kCLOCK_Gpt1S);
CLOCK_DisableClock(kCLOCK_Gpt2);
CLOCK_DisableClock(kCLOCK_Gpt2S);
CLOCK_DisableClock(kCLOCK_Pit);
/* Set PERCLK_PODF. */
CLOCK_SetDiv(kCLOCK_PerclkDiv, 1);
/* Disable USDHC1 clock gate. */
CLOCK_DisableClock(kCLOCK_Usdhc1);
/* Set USDHC1_PODF. */
CLOCK_SetDiv(kCLOCK_Usdhc1Div, 1);
/* Set Usdhc1 clock source. */
CLOCK_SetMux(kCLOCK_Usdhc1Mux, 0);
/* Disable USDHC2 clock gate. */
CLOCK_DisableClock(kCLOCK_Usdhc2);
/* Set USDHC2_PODF. */
CLOCK_SetDiv(kCLOCK_Usdhc2Div, 1);
/* Set Usdhc2 clock source. */
CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0);
/* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
* With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
* Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
#ifndef SKIP_SYSCLK_INIT
/* Disable Semc clock gate. */
CLOCK_DisableClock(kCLOCK_Semc);
/* Set SEMC_PODF. */
CLOCK_SetDiv(kCLOCK_SemcDiv, 7);
/* Set Semc alt clock source. */
CLOCK_SetMux(kCLOCK_SemcAltMux, 0);
/* Set Semc clock source. */
CLOCK_SetMux(kCLOCK_SemcMux, 0);
#endif
/* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
* With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
* Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
/* Disable Flexspi clock gate. */
CLOCK_DisableClock(kCLOCK_FlexSpi);
/* Set FLEXSPI_PODF. */
CLOCK_SetDiv(kCLOCK_FlexspiDiv, 1);
/* Set Flexspi clock source. */
CLOCK_SetMux(kCLOCK_FlexspiMux, 3);
#endif
/* Disable Flexspi2 clock gate. */
CLOCK_DisableClock(kCLOCK_FlexSpi2);
/* Set FLEXSPI2_PODF. */
CLOCK_SetDiv(kCLOCK_Flexspi2Div, 1);
/* Set Flexspi2 clock source. */
CLOCK_SetMux(kCLOCK_Flexspi2Mux, 1);
/* Disable CSI clock gate. */
CLOCK_DisableClock(kCLOCK_Csi);
/* Set CSI_PODF. */
CLOCK_SetDiv(kCLOCK_CsiDiv, 1);
/* Set Csi clock source. */
CLOCK_SetMux(kCLOCK_CsiMux, 0);
/* Disable LPSPI clock gate. */
CLOCK_DisableClock(kCLOCK_Lpspi1);
CLOCK_DisableClock(kCLOCK_Lpspi2);
CLOCK_DisableClock(kCLOCK_Lpspi3);
CLOCK_DisableClock(kCLOCK_Lpspi4);
/* Set LPSPI_PODF. */
CLOCK_SetDiv(kCLOCK_LpspiDiv, 4);
/* Set Lpspi clock source. */
CLOCK_SetMux(kCLOCK_LpspiMux, 2);
/* Disable TRACE clock gate. */
CLOCK_DisableClock(kCLOCK_Trace);
/* Set TRACE_PODF. */
CLOCK_SetDiv(kCLOCK_TraceDiv, 3);
/* Set Trace clock source. */
CLOCK_SetMux(kCLOCK_TraceMux, 0);
/* Disable SAI1 clock gate. */
CLOCK_DisableClock(kCLOCK_Sai1);
/* Set SAI1_CLK_PRED. */
CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3);
/* Set SAI1_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_Sai1Div, 1);
/* Set Sai1 clock source. */
CLOCK_SetMux(kCLOCK_Sai1Mux, 0);
/* Disable SAI2 clock gate. */
CLOCK_DisableClock(kCLOCK_Sai2);
/* Set SAI2_CLK_PRED. */
CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3);
/* Set SAI2_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_Sai2Div, 1);
/* Set Sai2 clock source. */
CLOCK_SetMux(kCLOCK_Sai2Mux, 0);
/* Disable SAI3 clock gate. */
CLOCK_DisableClock(kCLOCK_Sai3);
/* Set SAI3_CLK_PRED. */
CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3);
/* Set SAI3_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_Sai3Div, 1);
/* Set Sai3 clock source. */
CLOCK_SetMux(kCLOCK_Sai3Mux, 0);
/* Disable Lpi2c clock gate. */
CLOCK_DisableClock(kCLOCK_Lpi2c1);
CLOCK_DisableClock(kCLOCK_Lpi2c2);
CLOCK_DisableClock(kCLOCK_Lpi2c3);
/* Set LPI2C_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0);
/* Set Lpi2c clock source. */
CLOCK_SetMux(kCLOCK_Lpi2cMux, 0);
/* Disable CAN clock gate. */
CLOCK_DisableClock(kCLOCK_Can1);
CLOCK_DisableClock(kCLOCK_Can2);
CLOCK_DisableClock(kCLOCK_Can3);
CLOCK_DisableClock(kCLOCK_Can1S);
CLOCK_DisableClock(kCLOCK_Can2S);
CLOCK_DisableClock(kCLOCK_Can3S);
/* Set CAN_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_CanDiv, 1);
/* Set Can clock source. */
CLOCK_SetMux(kCLOCK_CanMux, 2);
/* Disable UART clock gate. */
CLOCK_DisableClock(kCLOCK_Lpuart1);
CLOCK_DisableClock(kCLOCK_Lpuart2);
CLOCK_DisableClock(kCLOCK_Lpuart3);
CLOCK_DisableClock(kCLOCK_Lpuart4);
CLOCK_DisableClock(kCLOCK_Lpuart5);
CLOCK_DisableClock(kCLOCK_Lpuart6);
CLOCK_DisableClock(kCLOCK_Lpuart7);
CLOCK_DisableClock(kCLOCK_Lpuart8);
/* Set UART_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_UartDiv, 0);
/* Set Uart clock source. */
CLOCK_SetMux(kCLOCK_UartMux, 0);
/* Disable LCDIF clock gate. */
CLOCK_DisableClock(kCLOCK_LcdPixel);
/* Set LCDIF_PRED. */
CLOCK_SetDiv(kCLOCK_LcdifPreDiv, 1);
/* Set LCDIF_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_LcdifDiv, 3);
/* Set Lcdif pre clock source. */
CLOCK_SetMux(kCLOCK_LcdifPreMux, 5);
/* Disable SPDIF clock gate. */
CLOCK_DisableClock(kCLOCK_Spdif);
/* Set SPDIF0_CLK_PRED. */
CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1);
/* Set SPDIF0_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_Spdif0Div, 7);
/* Set Spdif clock source. */
CLOCK_SetMux(kCLOCK_SpdifMux, 3);
/* Disable Flexio1 clock gate. */
CLOCK_DisableClock(kCLOCK_Flexio1);
/* Set FLEXIO1_CLK_PRED. */
CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1);
/* Set FLEXIO1_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_Flexio1Div, 7);
/* Set Flexio1 clock source. */
CLOCK_SetMux(kCLOCK_Flexio1Mux, 3);
/* Disable Flexio2 clock gate. */
CLOCK_DisableClock(kCLOCK_Flexio2);
/* Set FLEXIO2_CLK_PRED. */
CLOCK_SetDiv(kCLOCK_Flexio2PreDiv, 1);
/* Set FLEXIO2_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_Flexio2Div, 7);
/* Set Flexio2 clock source. */
CLOCK_SetMux(kCLOCK_Flexio2Mux, 3);
/* Set Pll3 sw clock source. */
CLOCK_SetMux(kCLOCK_Pll3SwMux, 0);
/* Init ARM PLL. */
CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN);
/* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
* With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
* Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
#ifndef SKIP_SYSCLK_INIT
#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1)
#warning "SKIP_SYSCLK_INIT should be defined to keep system pll (selected to be SEMC source clock in SDK projects) unchanged."
#endif
/* Init System PLL. */
CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN);
/* Init System pfd0. */
CLOCK_InitSysPfd(kCLOCK_Pfd0, 27);
/* Init System pfd1. */
CLOCK_InitSysPfd(kCLOCK_Pfd1, 16);
/* Init System pfd2. */
CLOCK_InitSysPfd(kCLOCK_Pfd2, 24);
/* Init System pfd3. */
CLOCK_InitSysPfd(kCLOCK_Pfd3, 16);
#endif
/* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
* With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
* Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
/* Init Usb1 PLL. */
CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN);
/* Init Usb1 pfd0. */
CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 33);
/* Init Usb1 pfd1. */
CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16);
/* Init Usb1 pfd2. */
CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17);
/* Init Usb1 pfd3. */
CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 19);
#endif
/* DeInit Audio PLL. */
CLOCK_DeinitAudioPll();
/* Bypass Audio PLL. */
CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1);
/* Set divider for Audio PLL. */
CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK;
CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK;
/* Enable Audio PLL output. */
CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK;
/* Init Video PLL. */
uint32_t pllVideo;
/* Disable Video PLL output before initial Video PLL. */
CCM_ANALOG->PLL_VIDEO &= ~CCM_ANALOG_PLL_VIDEO_ENABLE_MASK;
/* Bypass PLL first */
CCM_ANALOG->PLL_VIDEO = (CCM_ANALOG->PLL_VIDEO & (~CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK)) |
CCM_ANALOG_PLL_VIDEO_BYPASS_MASK | CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(0);
CCM_ANALOG->PLL_VIDEO_NUM = CCM_ANALOG_PLL_VIDEO_NUM_A(0);
CCM_ANALOG->PLL_VIDEO_DENOM = CCM_ANALOG_PLL_VIDEO_DENOM_B(1);
pllVideo = (CCM_ANALOG->PLL_VIDEO & (~(CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK | CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK))) |
CCM_ANALOG_PLL_VIDEO_ENABLE_MASK |CCM_ANALOG_PLL_VIDEO_DIV_SELECT(31);
pllVideo |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(1);
CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(3);
CCM_ANALOG->PLL_VIDEO = pllVideo;
while ((CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) == 0)
{
}
/* Disable bypass for Video PLL. */
CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllVideo, 0);
/* DeInit Enet PLL. */
CLOCK_DeinitEnetPll();
/* Bypass Enet PLL. */
CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllEnet, 1);
/* Set Enet output divider. */
CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_DIV_SELECT(1);
/* Enable Enet output. */
CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENABLE_MASK;
/* Set Enet2 output divider. */
CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT(0);
/* Enable Enet2 output. */
CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET2_REF_EN_MASK;
/* Enable Enet25M output. */
CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK;
/* Init Usb2 PLL. */
CLOCK_InitUsb2Pll(&usb2PllConfig_BOARD_BootClockRUN);
/* Set preperiph clock source. */
CLOCK_SetMux(kCLOCK_PrePeriphMux, 3);
/* Set periph clock source. */
CLOCK_SetMux(kCLOCK_PeriphMux, 0);
/* Set periph clock2 clock source. */
CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
/* Set per clock source. */
CLOCK_SetMux(kCLOCK_PerclkMux, 0);
/* Set lvds1 clock source. */
CCM_ANALOG->MISC1 = (CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0);
/* Set clock out1 divider. */
CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0);
/* Set clock out1 source. */
CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1);
/* Set clock out2 divider. */
CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0);
/* Set clock out2 source. */
CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(18);
/* Set clock out1 drives clock out1. */
CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK;
/* Disable clock out1. */
CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK;
/* Disable clock out2. */
CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK;
/* Set SAI1 MCLK1 clock source. */
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0);
/* Set SAI1 MCLK2 clock source. */
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0);
/* Set SAI1 MCLK3 clock source. */
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0);
/* Set SAI2 MCLK3 clock source. */
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0);
/* Set SAI3 MCLK3 clock source. */
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
/* Set MQS configuration. */
IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0);
/* Set ENET Ref clock source. */
IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK;
/* Set ENET2 Ref clock source. */
IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR_MASK;
/* Set GPT1 High frequency reference clock source. */
IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK;
/* Set GPT2 High frequency reference clock source. */
IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK;
/* Set SystemCoreClock variable. */
SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
}

123
managed_components/espressif__tinyusb/hw/bsp/imxrt/boards/mimxrt1060_evk/board/clock_config.h Normal file
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@@ -0,0 +1,123 @@
#ifndef _CLOCK_CONFIG_H_
#define _CLOCK_CONFIG_H_
#include "fsl_common.h"
/*******************************************************************************
* Definitions
******************************************************************************/
#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */
#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */
/*******************************************************************************
************************ BOARD_InitBootClocks function ************************
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/
/*!
* @brief This function executes default configuration of clocks.
*
*/
void BOARD_InitBootClocks(void);
#if defined(__cplusplus)
}
#endif /* __cplusplus*/
/*******************************************************************************
********************** Configuration BOARD_BootClockRUN ***********************
******************************************************************************/
/*******************************************************************************
* Definitions for BOARD_BootClockRUN configuration
******************************************************************************/
#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 600000000U /*!< Core clock frequency: 600000000Hz */
/* Clock outputs (values are in Hz): */
#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT 600000000UL
#define BOARD_BOOTCLOCKRUN_CAN_CLK_ROOT 40000000UL
#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL
#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL
#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL
#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL
#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL
#define BOARD_BOOTCLOCKRUN_CSI_CLK_ROOT 12000000UL
#define BOARD_BOOTCLOCKRUN_ENET2_125M_CLK 1200000UL
#define BOARD_BOOTCLOCKRUN_ENET2_REF_CLK 0UL
#define BOARD_BOOTCLOCKRUN_ENET2_TX_CLK 0UL
#define BOARD_BOOTCLOCKRUN_ENET_125M_CLK 2400000UL
#define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK 1200000UL
#define BOARD_BOOTCLOCKRUN_ENET_REF_CLK 0UL
#define BOARD_BOOTCLOCKRUN_ENET_TX_CLK 0UL
#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL
#define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT 30000000UL
#define BOARD_BOOTCLOCKRUN_FLEXSPI2_CLK_ROOT 130909090UL
#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 130909090UL
#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 75000000UL
#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 75000000UL
#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 150000000UL
#define BOARD_BOOTCLOCKRUN_LCDIF_CLK_ROOT 67500000UL
#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL
#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL
#define BOARD_BOOTCLOCKRUN_LVDS1_CLK 1200000000UL
#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL
#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 75000000UL
#define BOARD_BOOTCLOCKRUN_PLL7_MAIN_CLK 480000000UL
#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL
#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 63529411UL
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 63529411UL
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 30000000UL
#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL
#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 75000000UL
#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL
#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL
#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 132000000UL
#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL
#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK 480000000UL
#define BOARD_BOOTCLOCKRUN_USBPHY2_CLK 480000000UL
#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 198000000UL
#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 198000000UL
/*! @brief Arm PLL set for BOARD_BootClockRUN configuration.
*/
extern const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN;
/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration.
*/
extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN;
/*! @brief Usb2 PLL set for BOARD_BootClockRUN configuration.
*/
extern const clock_usb_pll_config_t usb2PllConfig_BOARD_BootClockRUN;
/*! @brief Sys PLL for BOARD_BootClockRUN configuration.
*/
extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN;
/*! @brief Video PLL set for BOARD_BootClockRUN configuration.
*/
extern const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN;
/*******************************************************************************
* API for BOARD_BootClockRUN configuration
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/
/*!
* @brief This function executes configuration of clocks.
*
*/
void BOARD_BootClockRUN(void);
#if defined(__cplusplus)
}
#endif /* __cplusplus*/
#endif /* _CLOCK_CONFIG_H_ */

497
managed_components/espressif__tinyusb/hw/bsp/imxrt/boards/mimxrt1060_evk/board/pin_mux.c Normal file
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/***********************************************************************************************************************
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
**********************************************************************************************************************/
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!GlobalInfo
product: Pins v13.1
processor: MIMXRT1062xxxxA
package_id: MIMXRT1062DVL6A
mcu_data: ksdk2_0
processor_version: 13.0.2
board: MIMXRT1060-EVK
pin_labels:
- {pin_num: F14, pin_signal: GPIO_AD_B0_09, label: 'JTAG_TDI/J21[5]/ENET_RST/J22[5]', identifier: USER_LED}
- {pin_num: L6, pin_signal: WAKEUP, label: SD_PWREN, identifier: USER_BUTTON}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
#include "fsl_common.h"
#include "fsl_iomuxc.h"
#include "fsl_gpio.h"
#include "pin_mux.h"
/* FUNCTION ************************************************************************************************************
*
* Function Name : BOARD_InitBootPins
* Description : Calls initialization functions.
*
* END ****************************************************************************************************************/
void BOARD_InitBootPins(void) {
BOARD_InitPins();
BOARD_InitDEBUG_UARTPins();
}
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
BOARD_InitPins:
- options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'}
- pin_list:
- {pin_num: F14, peripheral: GPIO1, signal: 'gpio_io, 09', pin_signal: GPIO_AD_B0_09, direction: OUTPUT, pull_keeper_select: Keeper}
- {pin_num: L6, peripheral: GPIO5, signal: 'gpio_io, 00', pin_signal: WAKEUP, direction: INPUT}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
/* FUNCTION ************************************************************************************************************
*
* Function Name : BOARD_InitPins
* Description : Configures pin routing and optionally pin electrical features.
*
* END ****************************************************************************************************************/
void BOARD_InitPins(void) {
CLOCK_EnableClock(kCLOCK_Iomuxc);
CLOCK_EnableClock(kCLOCK_IomuxcSnvs);
/* GPIO configuration of USER_LED on GPIO_AD_B0_09 (pin F14) */
gpio_pin_config_t USER_LED_config = {
.direction = kGPIO_DigitalOutput,
.outputLogic = 0U,
.interruptMode = kGPIO_NoIntmode
};
/* Initialize GPIO functionality on GPIO_AD_B0_09 (pin F14) */
GPIO_PinInit(GPIO1, 9U, &USER_LED_config);
/* GPIO configuration of USER_BUTTON on WAKEUP (pin L6) */
gpio_pin_config_t USER_BUTTON_config = {
.direction = kGPIO_DigitalInput,
.outputLogic = 0U,
.interruptMode = kGPIO_NoIntmode
};
/* Initialize GPIO functionality on WAKEUP (pin L6) */
GPIO_PinInit(GPIO5, 0U, &USER_BUTTON_config);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, 0U);
IOMUXC_GPR->GPR26 = ((IOMUXC_GPR->GPR26 &
(~(BOARD_INITPINS_IOMUXC_GPR_GPR26_GPIO_MUX1_GPIO_SEL_MASK)))
| IOMUXC_GPR_GPR26_GPIO_MUX1_GPIO_SEL(0x00U)
);
IOMUXC_SetPinMux(IOMUXC_SNVS_WAKEUP_GPIO5_IO00, 0U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, 0x50A0U);
}
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
BOARD_InitDEBUG_UARTPins:
- options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'}
- pin_list:
- {pin_num: K14, peripheral: LPUART1, signal: TX, pin_signal: GPIO_AD_B0_12, software_input_on: Disable, hysteresis_enable: Disable, pull_up_down_config: Pull_Down_100K_Ohm,
pull_keeper_select: Keeper, pull_keeper_enable: Enable, open_drain: Disable, speed: MHZ_100, drive_strength: R0_6, slew_rate: Slow}
- {pin_num: L14, peripheral: LPUART1, signal: RX, pin_signal: GPIO_AD_B0_13, software_input_on: Disable, hysteresis_enable: Disable, pull_up_down_config: Pull_Down_100K_Ohm,
pull_keeper_select: Keeper, pull_keeper_enable: Enable, open_drain: Disable, speed: MHZ_100, drive_strength: R0_6, slew_rate: Slow}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
/* FUNCTION ************************************************************************************************************
*
* Function Name : BOARD_InitDEBUG_UARTPins
* Description : Configures pin routing and optionally pin electrical features.
*
* END ****************************************************************************************************************/
void BOARD_InitDEBUG_UARTPins(void) {
CLOCK_EnableClock(kCLOCK_Iomuxc);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_12_LPUART1_TX, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_13_LPUART1_RX, 0U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_12_LPUART1_TX, 0x10B0U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_13_LPUART1_RX, 0x10B0U);
}
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
BOARD_InitSDRAMPins:
- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'}
- pin_list:
- {pin_num: C2, peripheral: SEMC, signal: 'ADDR, 00', pin_signal: GPIO_EMC_09}
- {pin_num: G1, peripheral: SEMC, signal: 'ADDR, 01', pin_signal: GPIO_EMC_10}
- {pin_num: G3, peripheral: SEMC, signal: 'ADDR, 02', pin_signal: GPIO_EMC_11}
- {pin_num: H1, peripheral: SEMC, signal: 'ADDR, 03', pin_signal: GPIO_EMC_12}
- {pin_num: A6, peripheral: SEMC, signal: 'ADDR, 04', pin_signal: GPIO_EMC_13}
- {pin_num: B6, peripheral: SEMC, signal: 'ADDR, 05', pin_signal: GPIO_EMC_14}
- {pin_num: B1, peripheral: SEMC, signal: 'ADDR, 06', pin_signal: GPIO_EMC_15}
- {pin_num: A5, peripheral: SEMC, signal: 'ADDR, 07', pin_signal: GPIO_EMC_16}
- {pin_num: A4, peripheral: SEMC, signal: 'ADDR, 08', pin_signal: GPIO_EMC_17}
- {pin_num: B2, peripheral: SEMC, signal: 'ADDR, 09', pin_signal: GPIO_EMC_18}
- {pin_num: G2, peripheral: SEMC, signal: 'ADDR, 10', pin_signal: GPIO_EMC_23}
- {pin_num: B4, peripheral: SEMC, signal: 'ADDR, 11', pin_signal: GPIO_EMC_19}
- {pin_num: A3, peripheral: SEMC, signal: 'ADDR, 12', pin_signal: GPIO_EMC_20}
- {pin_num: C1, peripheral: SEMC, signal: 'BA, 0', pin_signal: GPIO_EMC_21}
- {pin_num: F1, peripheral: SEMC, signal: 'BA, 1', pin_signal: GPIO_EMC_22}
- {pin_num: D3, peripheral: SEMC, signal: semc_cas, pin_signal: GPIO_EMC_24}
- {pin_num: A2, peripheral: SEMC, signal: semc_cke, pin_signal: GPIO_EMC_27}
- {pin_num: B3, peripheral: SEMC, signal: semc_clk, pin_signal: GPIO_EMC_26}
- {pin_num: E3, peripheral: SEMC, signal: 'DATA, 00', pin_signal: GPIO_EMC_00}
- {pin_num: F3, peripheral: SEMC, signal: 'DATA, 01', pin_signal: GPIO_EMC_01}
- {pin_num: F4, peripheral: SEMC, signal: 'DATA, 02', pin_signal: GPIO_EMC_02}
- {pin_num: G4, peripheral: SEMC, signal: 'DATA, 03', pin_signal: GPIO_EMC_03}
- {pin_num: F2, peripheral: SEMC, signal: 'DATA, 04', pin_signal: GPIO_EMC_04}
- {pin_num: G5, peripheral: SEMC, signal: 'DATA, 05', pin_signal: GPIO_EMC_05}
- {pin_num: H5, peripheral: SEMC, signal: 'DATA, 06', pin_signal: GPIO_EMC_06}
- {pin_num: H4, peripheral: SEMC, signal: 'DATA, 07', pin_signal: GPIO_EMC_07}
- {pin_num: C6, peripheral: SEMC, signal: 'DATA, 08', pin_signal: GPIO_EMC_30}
- {pin_num: C5, peripheral: SEMC, signal: 'DATA, 09', pin_signal: GPIO_EMC_31}
- {pin_num: D5, peripheral: SEMC, signal: 'DATA, 10', pin_signal: GPIO_EMC_32}
- {pin_num: C4, peripheral: SEMC, signal: 'DATA, 11', pin_signal: GPIO_EMC_33}
- {pin_num: D4, peripheral: SEMC, signal: 'DATA, 12', pin_signal: GPIO_EMC_34}
- {pin_num: E5, peripheral: SEMC, signal: 'DATA, 13', pin_signal: GPIO_EMC_35}
- {pin_num: C3, peripheral: SEMC, signal: 'DATA, 14', pin_signal: GPIO_EMC_36}
- {pin_num: E4, peripheral: SEMC, signal: 'DATA, 15', pin_signal: GPIO_EMC_37}
- {pin_num: H3, peripheral: SEMC, signal: 'DM, 0', pin_signal: GPIO_EMC_08}
- {pin_num: D6, peripheral: SEMC, signal: 'DM, 1', pin_signal: GPIO_EMC_38}
- {pin_num: D2, peripheral: SEMC, signal: semc_ras, pin_signal: GPIO_EMC_25}
- {pin_num: D1, peripheral: SEMC, signal: semc_we, pin_signal: GPIO_EMC_28}
- {pin_num: E1, peripheral: SEMC, signal: 'CS, 0', pin_signal: GPIO_EMC_29}
- {pin_num: B7, peripheral: SEMC, signal: semc_dqs, pin_signal: GPIO_EMC_39}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
/* FUNCTION ************************************************************************************************************
*
* Function Name : BOARD_InitSDRAMPins
* Description : Configures pin routing and optionally pin electrical features.
*
* END ****************************************************************************************************************/
void BOARD_InitSDRAMPins(void) {
CLOCK_EnableClock(kCLOCK_Iomuxc);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_00_SEMC_DATA00, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_01_SEMC_DATA01, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_02_SEMC_DATA02, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_03_SEMC_DATA03, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_04_SEMC_DATA04, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_05_SEMC_DATA05, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_06_SEMC_DATA06, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_07_SEMC_DATA07, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_08_SEMC_DM00, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_09_SEMC_ADDR00, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_10_SEMC_ADDR01, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_11_SEMC_ADDR02, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_12_SEMC_ADDR03, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_13_SEMC_ADDR04, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_14_SEMC_ADDR05, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_15_SEMC_ADDR06, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_16_SEMC_ADDR07, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_17_SEMC_ADDR08, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_18_SEMC_ADDR09, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_19_SEMC_ADDR11, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_20_SEMC_ADDR12, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_21_SEMC_BA0, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_22_SEMC_BA1, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_23_SEMC_ADDR10, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_24_SEMC_CAS, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_25_SEMC_RAS, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_26_SEMC_CLK, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_27_SEMC_CKE, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_28_SEMC_WE, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_29_SEMC_CS0, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_30_SEMC_DATA08, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_31_SEMC_DATA09, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_32_SEMC_DATA10, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_33_SEMC_DATA11, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_34_SEMC_DATA12, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_35_SEMC_DATA13, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_36_SEMC_DATA14, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_37_SEMC_DATA15, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_38_SEMC_DM01, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_39_SEMC_DQS, 0U);
}
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
BOARD_InitCSIPins:
- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'}
- pin_list:
- {pin_num: H13, peripheral: CSI, signal: 'csi_data, 09', pin_signal: GPIO_AD_B1_08}
- {pin_num: M13, peripheral: CSI, signal: 'csi_data, 08', pin_signal: GPIO_AD_B1_09}
- {pin_num: L13, peripheral: CSI, signal: 'csi_data, 07', pin_signal: GPIO_AD_B1_10}
- {pin_num: J13, peripheral: CSI, signal: 'csi_data, 06', pin_signal: GPIO_AD_B1_11}
- {pin_num: H12, peripheral: CSI, signal: 'csi_data, 05', pin_signal: GPIO_AD_B1_12}
- {pin_num: H11, peripheral: CSI, signal: 'csi_data, 04', pin_signal: GPIO_AD_B1_13}
- {pin_num: J14, peripheral: CSI, signal: 'csi_data, 02', pin_signal: GPIO_AD_B1_15}
- {pin_num: G12, peripheral: CSI, signal: 'csi_data, 03', pin_signal: GPIO_AD_B1_14}
- {pin_num: L12, peripheral: CSI, signal: csi_pixclk, pin_signal: GPIO_AD_B1_04}
- {pin_num: K12, peripheral: CSI, signal: csi_mclk, pin_signal: GPIO_AD_B1_05}
- {pin_num: J12, peripheral: CSI, signal: csi_vsync, pin_signal: GPIO_AD_B1_06}
- {pin_num: K10, peripheral: CSI, signal: csi_hsync, pin_signal: GPIO_AD_B1_07}
- {pin_num: J11, peripheral: LPI2C1, signal: SCL, pin_signal: GPIO_AD_B1_00, identifier: CSI_I2C_SCL, software_input_on: Disable, hysteresis_enable: Disable, pull_up_down_config: Pull_Up_22K_Ohm,
pull_keeper_select: Keeper, pull_keeper_enable: Enable, open_drain: Enable, speed: MHZ_100, drive_strength: R0_6, slew_rate: Slow}
- {pin_num: K11, peripheral: LPI2C1, signal: SDA, pin_signal: GPIO_AD_B1_01, identifier: CSI_I2C_SDA, software_input_on: Disable, hysteresis_enable: Disable, pull_up_down_config: Pull_Up_22K_Ohm,
pull_keeper_select: Keeper, pull_keeper_enable: Enable, open_drain: Enable, speed: MHZ_100, drive_strength: R0_6, slew_rate: Slow}
- {pin_num: F11, peripheral: GPIO1, signal: 'gpio_io, 04', pin_signal: GPIO_AD_B0_04}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
/* FUNCTION ************************************************************************************************************
*
* Function Name : BOARD_InitCSIPins
* Description : Configures pin routing and optionally pin electrical features.
*
* END ****************************************************************************************************************/
void BOARD_InitCSIPins(void) {
CLOCK_EnableClock(kCLOCK_Iomuxc);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_04_GPIO1_IO04, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_04_CSI_PIXCLK, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_05_CSI_MCLK, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_06_CSI_VSYNC, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_07_CSI_HSYNC, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_08_CSI_DATA09, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_09_CSI_DATA08, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_10_CSI_DATA07, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_11_CSI_DATA06, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_12_CSI_DATA05, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_13_CSI_DATA04, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_14_CSI_DATA03, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_15_CSI_DATA02, 0U);
IOMUXC_GPR->GPR26 = ((IOMUXC_GPR->GPR26 &
(~(BOARD_INITCSIPINS_IOMUXC_GPR_GPR26_GPIO_MUX1_GPIO_SEL_MASK)))
| IOMUXC_GPR_GPR26_GPIO_MUX1_GPIO_SEL(0x00U)
);
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL, 0xD8B0U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA, 0xD8B0U);
}
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
BOARD_InitLCDPins:
- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'}
- pin_list:
- {pin_num: C8, peripheral: LCDIF, signal: 'lcdif_data, 00', pin_signal: GPIO_B0_04, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
- {pin_num: B8, peripheral: LCDIF, signal: 'lcdif_data, 01', pin_signal: GPIO_B0_05, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
- {pin_num: A8, peripheral: LCDIF, signal: 'lcdif_data, 02', pin_signal: GPIO_B0_06, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
- {pin_num: D7, peripheral: LCDIF, signal: lcdif_clk, pin_signal: GPIO_B0_00, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
- {pin_num: A9, peripheral: LCDIF, signal: 'lcdif_data, 03', pin_signal: GPIO_B0_07, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
- {pin_num: B9, peripheral: LCDIF, signal: 'lcdif_data, 04', pin_signal: GPIO_B0_08, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
- {pin_num: C9, peripheral: LCDIF, signal: 'lcdif_data, 05', pin_signal: GPIO_B0_09, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
- {pin_num: D9, peripheral: LCDIF, signal: 'lcdif_data, 06', pin_signal: GPIO_B0_10, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
- {pin_num: A10, peripheral: LCDIF, signal: 'lcdif_data, 07', pin_signal: GPIO_B0_11, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
- {pin_num: C10, peripheral: LCDIF, signal: 'lcdif_data, 08', pin_signal: GPIO_B0_12, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
- {pin_num: D10, peripheral: LCDIF, signal: 'lcdif_data, 09', pin_signal: GPIO_B0_13, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
- {pin_num: E10, peripheral: LCDIF, signal: 'lcdif_data, 10', pin_signal: GPIO_B0_14, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
- {pin_num: E11, peripheral: LCDIF, signal: 'lcdif_data, 11', pin_signal: GPIO_B0_15, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
- {pin_num: A11, peripheral: LCDIF, signal: 'lcdif_data, 12', pin_signal: GPIO_B1_00, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
- {pin_num: B11, peripheral: LCDIF, signal: 'lcdif_data, 13', pin_signal: GPIO_B1_01, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
- {pin_num: C11, peripheral: LCDIF, signal: 'lcdif_data, 14', pin_signal: GPIO_B1_02, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
- {pin_num: D11, peripheral: LCDIF, signal: 'lcdif_data, 15', pin_signal: GPIO_B1_03, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
- {pin_num: E7, peripheral: LCDIF, signal: lcdif_enable, pin_signal: GPIO_B0_01, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
- {pin_num: E8, peripheral: LCDIF, signal: lcdif_hsync, pin_signal: GPIO_B0_02, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
- {pin_num: D8, peripheral: LCDIF, signal: lcdif_vsync, pin_signal: GPIO_B0_03, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
- {pin_num: B14, peripheral: GPIO2, signal: 'gpio_io, 31', pin_signal: GPIO_B1_15, slew_rate: Slow}
- {pin_num: M11, peripheral: GPIO1, signal: 'gpio_io, 02', pin_signal: GPIO_AD_B0_02}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
/* FUNCTION ************************************************************************************************************
*
* Function Name : BOARD_InitLCDPins
* Description : Configures pin routing and optionally pin electrical features.
*
* END ****************************************************************************************************************/
void BOARD_InitLCDPins(void) {
CLOCK_EnableClock(kCLOCK_Iomuxc);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_02_GPIO1_IO02, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_00_LCD_CLK, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_01_LCD_ENABLE, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_02_LCD_HSYNC, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_03_LCD_VSYNC, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_04_LCD_DATA00, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_05_LCD_DATA01, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_06_LCD_DATA02, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_07_LCD_DATA03, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_08_LCD_DATA04, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_09_LCD_DATA05, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_10_LCD_DATA06, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_11_LCD_DATA07, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_12_LCD_DATA08, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_13_LCD_DATA09, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_14_LCD_DATA10, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_15_LCD_DATA11, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_00_LCD_DATA12, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_01_LCD_DATA13, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_02_LCD_DATA14, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_03_LCD_DATA15, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_15_GPIO2_IO31, 0U);
IOMUXC_GPR->GPR26 = ((IOMUXC_GPR->GPR26 &
(~(BOARD_INITLCDPINS_IOMUXC_GPR_GPR26_GPIO_MUX1_GPIO_SEL_MASK)))
| IOMUXC_GPR_GPR26_GPIO_MUX1_GPIO_SEL(0x00U)
);
IOMUXC_GPR->GPR27 = ((IOMUXC_GPR->GPR27 &
(~(BOARD_INITLCDPINS_IOMUXC_GPR_GPR27_GPIO_MUX2_GPIO_SEL_MASK)))
| IOMUXC_GPR_GPR27_GPIO_MUX2_GPIO_SEL(0x00U)
);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_00_LCD_CLK, 0x01B0B0U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_01_LCD_ENABLE, 0x01B0B0U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_02_LCD_HSYNC, 0x01B0B0U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_03_LCD_VSYNC, 0x01B0B0U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_04_LCD_DATA00, 0x01B0B0U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_05_LCD_DATA01, 0x01B0B0U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_06_LCD_DATA02, 0x01B0B0U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_07_LCD_DATA03, 0x01B0B0U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_08_LCD_DATA04, 0x01B0B0U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_09_LCD_DATA05, 0x01B0B0U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_10_LCD_DATA06, 0x01B0B0U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_11_LCD_DATA07, 0x01B0B0U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_12_LCD_DATA08, 0x01B0B0U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_13_LCD_DATA09, 0x01B0B0U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_14_LCD_DATA10, 0x01B0B0U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_15_LCD_DATA11, 0x01B0B0U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_00_LCD_DATA12, 0x01B0B0U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_01_LCD_DATA13, 0x01B0B0U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_02_LCD_DATA14, 0x01B0B0U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_03_LCD_DATA15, 0x01B0B0U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_15_GPIO2_IO31, 0x10B0U);
}
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
BOARD_InitCANPins:
- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'}
- pin_list:
- {pin_num: H14, peripheral: CAN2, signal: TX, pin_signal: GPIO_AD_B0_14}
- {pin_num: L10, peripheral: CAN2, signal: RX, pin_signal: GPIO_AD_B0_15}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
/* FUNCTION ************************************************************************************************************
*
* Function Name : BOARD_InitCANPins
* Description : Configures pin routing and optionally pin electrical features.
*
* END ****************************************************************************************************************/
void BOARD_InitCANPins(void) {
CLOCK_EnableClock(kCLOCK_Iomuxc);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_14_FLEXCAN2_TX, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_15_FLEXCAN2_RX, 0U);
}
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
BOARD_InitENETPins:
- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'}
- pin_list:
- {pin_num: A7, peripheral: ENET, signal: enet_mdc, pin_signal: GPIO_EMC_40}
- {pin_num: C7, peripheral: ENET, signal: enet_mdio, pin_signal: GPIO_EMC_41}
- {pin_num: B13, peripheral: ENET, signal: enet_ref_clk, pin_signal: GPIO_B1_10}
- {pin_num: E12, peripheral: ENET, signal: 'enet_rx_data, 0', pin_signal: GPIO_B1_04}
- {pin_num: D12, peripheral: ENET, signal: 'enet_rx_data, 1', pin_signal: GPIO_B1_05}
- {pin_num: C12, peripheral: ENET, signal: enet_rx_en, pin_signal: GPIO_B1_06}
- {pin_num: C13, peripheral: ENET, signal: enet_rx_er, pin_signal: GPIO_B1_11}
- {pin_num: B12, peripheral: ENET, signal: 'enet_tx_data, 0', pin_signal: GPIO_B1_07}
- {pin_num: A12, peripheral: ENET, signal: 'enet_tx_data, 1', pin_signal: GPIO_B1_08}
- {pin_num: A13, peripheral: ENET, signal: enet_tx_en, pin_signal: GPIO_B1_09}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
/* FUNCTION ************************************************************************************************************
*
* Function Name : BOARD_InitENETPins
* Description : Configures pin routing and optionally pin electrical features.
*
* END ****************************************************************************************************************/
void BOARD_InitENETPins(void) {
CLOCK_EnableClock(kCLOCK_Iomuxc);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_04_ENET_RX_DATA00, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_05_ENET_RX_DATA01, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_06_ENET_RX_EN, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_07_ENET_TX_DATA00, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_08_ENET_TX_DATA01, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_09_ENET_TX_EN, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_10_ENET_REF_CLK, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_11_ENET_RX_ER, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_40_ENET_MDC, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_41_ENET_MDIO, 0U);
}
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
BOARD_InitUSDHCPins:
- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'}
- pin_list:
- {pin_num: J2, peripheral: USDHC1, signal: 'usdhc_data, 3', pin_signal: GPIO_SD_B0_05}
- {pin_num: H2, peripheral: USDHC1, signal: 'usdhc_data, 2', pin_signal: GPIO_SD_B0_04}
- {pin_num: K1, peripheral: USDHC1, signal: 'usdhc_data, 1', pin_signal: GPIO_SD_B0_03}
- {pin_num: J1, peripheral: USDHC1, signal: 'usdhc_data, 0', pin_signal: GPIO_SD_B0_02}
- {pin_num: J4, peripheral: USDHC1, signal: usdhc_cmd, pin_signal: GPIO_SD_B0_00}
- {pin_num: J3, peripheral: USDHC1, signal: usdhc_clk, pin_signal: GPIO_SD_B0_01}
- {pin_num: C14, peripheral: USDHC1, signal: usdhc_vselect, pin_signal: GPIO_B1_14}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
/* FUNCTION ************************************************************************************************************
*
* Function Name : BOARD_InitUSDHCPins
* Description : Configures pin routing and optionally pin electrical features.
*
* END ****************************************************************************************************************/
void BOARD_InitUSDHCPins(void) {
CLOCK_EnableClock(kCLOCK_Iomuxc);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_14_USDHC1_VSELECT, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_00_USDHC1_CMD, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_01_USDHC1_CLK, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3, 0U);
}
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
BOARD_InitQSPIPins:
- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'}
- pin_list:
- {pin_num: P3, peripheral: FLEXSPI, signal: FLEXSPI_A_DATA0, pin_signal: GPIO_SD_B1_08}
- {pin_num: N4, peripheral: FLEXSPI, signal: FLEXSPI_A_DATA1, pin_signal: GPIO_SD_B1_09}
- {pin_num: P4, peripheral: FLEXSPI, signal: FLEXSPI_A_DATA2, pin_signal: GPIO_SD_B1_10}
- {pin_num: P5, peripheral: FLEXSPI, signal: FLEXSPI_A_DATA3, pin_signal: GPIO_SD_B1_11}
- {pin_num: L4, peripheral: FLEXSPI, signal: FLEXSPI_A_SCLK, pin_signal: GPIO_SD_B1_07}
- {pin_num: L3, peripheral: FLEXSPI, signal: FLEXSPI_A_SS0_B, pin_signal: GPIO_SD_B1_06}
- {pin_num: N3, peripheral: FLEXSPI, signal: FLEXSPI_A_DQS, pin_signal: GPIO_SD_B1_05}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
/* FUNCTION ************************************************************************************************************
*
* Function Name : BOARD_InitQSPIPins
* Description : Configures pin routing and optionally pin electrical features.
*
* END ****************************************************************************************************************/
void BOARD_InitQSPIPins(void) {
CLOCK_EnableClock(kCLOCK_Iomuxc);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_05_FLEXSPIA_DQS, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_06_FLEXSPIA_SS0_B, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_07_FLEXSPIA_SCLK, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_08_FLEXSPIA_DATA00, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_09_FLEXSPIA_DATA01, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_10_FLEXSPIA_DATA02, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_11_FLEXSPIA_DATA03, 0U);
}
/***********************************************************************************************************************
* EOF
**********************************************************************************************************************/

744
managed_components/espressif__tinyusb/hw/bsp/imxrt/boards/mimxrt1060_evk/board/pin_mux.h Normal file
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@@ -0,0 +1,744 @@
/***********************************************************************************************************************
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
**********************************************************************************************************************/
#ifndef _PIN_MUX_H_
#define _PIN_MUX_H_
/***********************************************************************************************************************
* Definitions
**********************************************************************************************************************/
/*! @brief Direction type */
typedef enum _pin_mux_direction
{
kPIN_MUX_DirectionInput = 0U, /* Input direction */
kPIN_MUX_DirectionOutput = 1U, /* Output direction */
kPIN_MUX_DirectionInputOrOutput = 2U /* Input or output direction */
} pin_mux_direction_t;
/*!
* @addtogroup pin_mux
* @{
*/
/***********************************************************************************************************************
* API
**********************************************************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif
/*!
* @brief Calls initialization functions.
*
*/
void BOARD_InitBootPins(void);
#define BOARD_INITPINS_IOMUXC_GPR_GPR26_GPIO_MUX1_GPIO_SEL_MASK 0x0200U /*!< GPIO1 and GPIO6 share same IO MUX function, GPIO_MUX1 selects one GPIO function: affected bits mask */
/* GPIO_AD_B0_09 (coord F14), JTAG_TDI/J21[5]/ENET_RST/J22[5] */
/* Routed pin properties */
#define BOARD_INITPINS_USER_LED_PERIPHERAL GPIO1 /*!< Peripheral name */
#define BOARD_INITPINS_USER_LED_SIGNAL gpio_io /*!< Signal name */
#define BOARD_INITPINS_USER_LED_CHANNEL 9U /*!< Signal channel */
/* Symbols to be used with GPIO driver */
#define BOARD_INITPINS_USER_LED_GPIO GPIO1 /*!< GPIO peripheral base pointer */
#define BOARD_INITPINS_USER_LED_GPIO_PIN 9U /*!< GPIO pin number */
#define BOARD_INITPINS_USER_LED_GPIO_PIN_MASK (1U << 9U) /*!< GPIO pin mask */
#define BOARD_INITPINS_USER_LED_PORT GPIO1 /*!< PORT peripheral base pointer */
#define BOARD_INITPINS_USER_LED_PIN 9U /*!< PORT pin number */
#define BOARD_INITPINS_USER_LED_PIN_MASK (1U << 9U) /*!< PORT pin mask */
/* WAKEUP (coord L6), SD_PWREN */
/* Routed pin properties */
#define BOARD_INITPINS_USER_BUTTON_PERIPHERAL GPIO5 /*!< Peripheral name */
#define BOARD_INITPINS_USER_BUTTON_SIGNAL gpio_io /*!< Signal name */
#define BOARD_INITPINS_USER_BUTTON_CHANNEL 0U /*!< Signal channel */
/* Symbols to be used with GPIO driver */
#define BOARD_INITPINS_USER_BUTTON_GPIO GPIO5 /*!< GPIO peripheral base pointer */
#define BOARD_INITPINS_USER_BUTTON_GPIO_PIN 0U /*!< GPIO pin number */
#define BOARD_INITPINS_USER_BUTTON_GPIO_PIN_MASK (1U << 0U) /*!< GPIO pin mask */
#define BOARD_INITPINS_USER_BUTTON_PORT GPIO5 /*!< PORT peripheral base pointer */
#define BOARD_INITPINS_USER_BUTTON_PIN 0U /*!< PORT pin number */
#define BOARD_INITPINS_USER_BUTTON_PIN_MASK (1U << 0U) /*!< PORT pin mask */
/*!
* @brief Configures pin routing and optionally pin electrical features.
*
*/
void BOARD_InitPins(void);
/* GPIO_AD_B0_12 (coord K14), UART1_TXD */
/* Routed pin properties */
#define BOARD_INITDEBUG_UARTPINS_UART1_TXD_PERIPHERAL LPUART1 /*!< Peripheral name */
#define BOARD_INITDEBUG_UARTPINS_UART1_TXD_SIGNAL TX /*!< Signal name */
/* GPIO_AD_B0_13 (coord L14), UART1_RXD */
/* Routed pin properties */
#define BOARD_INITDEBUG_UARTPINS_UART1_RXD_PERIPHERAL LPUART1 /*!< Peripheral name */
#define BOARD_INITDEBUG_UARTPINS_UART1_RXD_SIGNAL RX /*!< Signal name */
/*!
* @brief Configures pin routing and optionally pin electrical features.
*
*/
void BOARD_InitDEBUG_UARTPins(void);
/* GPIO_EMC_09 (coord C2), SEMC_A0 */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_A0_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_A0_SIGNAL ADDR /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_A0_CHANNEL 0U /*!< Signal channel */
/* GPIO_EMC_10 (coord G1), SEMC_A1 */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_A1_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_A1_SIGNAL ADDR /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_A1_CHANNEL 1U /*!< Signal channel */
/* GPIO_EMC_11 (coord G3), SEMC_A2 */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_A2_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_A2_SIGNAL ADDR /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_A2_CHANNEL 2U /*!< Signal channel */
/* GPIO_EMC_12 (coord H1), SEMC_A3 */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_A3_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_A3_SIGNAL ADDR /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_A3_CHANNEL 3U /*!< Signal channel */
/* GPIO_EMC_13 (coord A6), SEMC_A4 */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_A4_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_A4_SIGNAL ADDR /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_A4_CHANNEL 4U /*!< Signal channel */
/* GPIO_EMC_14 (coord B6), SEMC_A5 */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_A5_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_A5_SIGNAL ADDR /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_A5_CHANNEL 5U /*!< Signal channel */
/* GPIO_EMC_15 (coord B1), SEMC_A6 */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_A6_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_A6_SIGNAL ADDR /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_A6_CHANNEL 6U /*!< Signal channel */
/* GPIO_EMC_16 (coord A5), SEMC_A7 */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_A7_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_A7_SIGNAL ADDR /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_A7_CHANNEL 7U /*!< Signal channel */
/* GPIO_EMC_17 (coord A4), SEMC_A8 */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_A8_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_A8_SIGNAL ADDR /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_A8_CHANNEL 8U /*!< Signal channel */
/* GPIO_EMC_18 (coord B2), SEMC_A9 */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_A9_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_A9_SIGNAL ADDR /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_A9_CHANNEL 9U /*!< Signal channel */
/* GPIO_EMC_23 (coord G2), SEMC_A10 */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_A10_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_A10_SIGNAL ADDR /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_A10_CHANNEL 10U /*!< Signal channel */
/* GPIO_EMC_19 (coord B4), SEMC_A11 */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_A11_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_A11_SIGNAL ADDR /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_A11_CHANNEL 11U /*!< Signal channel */
/* GPIO_EMC_20 (coord A3), SEMC_A12 */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_A12_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_A12_SIGNAL ADDR /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_A12_CHANNEL 12U /*!< Signal channel */
/* GPIO_EMC_21 (coord C1), SEMC_BA0 */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_BA0_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_BA0_SIGNAL BA /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_BA0_CHANNEL 0U /*!< Signal channel */
/* GPIO_EMC_22 (coord F1), SEMC_BA1 */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_BA1_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_BA1_SIGNAL BA /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_BA1_CHANNEL 1U /*!< Signal channel */
/* GPIO_EMC_24 (coord D3), SEMC_CAS */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_CAS_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_CAS_SIGNAL semc_cas /*!< Signal name */
/* GPIO_EMC_27 (coord A2), SEMC_CKE */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_CKE_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_CKE_SIGNAL semc_cke /*!< Signal name */
/* GPIO_EMC_26 (coord B3), SEMC_CLK */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_CLK_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_CLK_SIGNAL semc_clk /*!< Signal name */
/* GPIO_EMC_00 (coord E3), SEMC_D0 */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_D0_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_D0_SIGNAL DATA /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_D0_CHANNEL 0U /*!< Signal channel */
/* GPIO_EMC_01 (coord F3), SEMC_D1 */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_D1_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_D1_SIGNAL DATA /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_D1_CHANNEL 1U /*!< Signal channel */
/* GPIO_EMC_02 (coord F4), SEMC_D2 */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_D2_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_D2_SIGNAL DATA /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_D2_CHANNEL 2U /*!< Signal channel */
/* GPIO_EMC_03 (coord G4), SEMC_D3 */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_D3_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_D3_SIGNAL DATA /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_D3_CHANNEL 3U /*!< Signal channel */
/* GPIO_EMC_04 (coord F2), SEMC_D4 */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_D4_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_D4_SIGNAL DATA /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_D4_CHANNEL 4U /*!< Signal channel */
/* GPIO_EMC_05 (coord G5), SEMC_D5 */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_D5_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_D5_SIGNAL DATA /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_D5_CHANNEL 5U /*!< Signal channel */
/* GPIO_EMC_06 (coord H5), SEMC_D6 */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_D6_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_D6_SIGNAL DATA /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_D6_CHANNEL 6U /*!< Signal channel */
/* GPIO_EMC_07 (coord H4), SEMC_D7 */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_D7_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_D7_SIGNAL DATA /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_D7_CHANNEL 7U /*!< Signal channel */
/* GPIO_EMC_30 (coord C6), SEMC_D8 */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_D8_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_D8_SIGNAL DATA /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_D8_CHANNEL 8U /*!< Signal channel */
/* GPIO_EMC_31 (coord C5), SEMC_D9 */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_D9_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_D9_SIGNAL DATA /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_D9_CHANNEL 9U /*!< Signal channel */
/* GPIO_EMC_32 (coord D5), SEMC_D10 */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_D10_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_D10_SIGNAL DATA /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_D10_CHANNEL 10U /*!< Signal channel */
/* GPIO_EMC_33 (coord C4), SEMC_D11 */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_D11_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_D11_SIGNAL DATA /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_D11_CHANNEL 11U /*!< Signal channel */
/* GPIO_EMC_34 (coord D4), SEMC_D12 */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_D12_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_D12_SIGNAL DATA /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_D12_CHANNEL 12U /*!< Signal channel */
/* GPIO_EMC_35 (coord E5), SEMC_D13 */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_D13_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_D13_SIGNAL DATA /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_D13_CHANNEL 13U /*!< Signal channel */
/* GPIO_EMC_36 (coord C3), SEMC_D14 */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_D14_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_D14_SIGNAL DATA /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_D14_CHANNEL 14U /*!< Signal channel */
/* GPIO_EMC_37 (coord E4), SEMC_D15 */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_D15_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_D15_SIGNAL DATA /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_D15_CHANNEL 15U /*!< Signal channel */
/* GPIO_EMC_08 (coord H3), SEMC_DM0 */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_DM0_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_DM0_SIGNAL DM /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_DM0_CHANNEL 0U /*!< Signal channel */
/* GPIO_EMC_38 (coord D6), SEMC_DM1 */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_DM1_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_DM1_SIGNAL DM /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_DM1_CHANNEL 1U /*!< Signal channel */
/* GPIO_EMC_25 (coord D2), SEMC_RAS */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_RAS_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_RAS_SIGNAL semc_ras /*!< Signal name */
/* GPIO_EMC_28 (coord D1), SEMC_WE */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_WE_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_WE_SIGNAL semc_we /*!< Signal name */
/* GPIO_EMC_29 (coord E1), SEMC_CS0 */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_CS0_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_CS0_SIGNAL CS /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_CS0_CHANNEL 0U /*!< Signal channel */
/* GPIO_EMC_39 (coord B7), SEMC_DQS */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_DQS_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_DQS_SIGNAL semc_dqs /*!< Signal name */
/*!
* @brief Configures pin routing and optionally pin electrical features.
*
*/
void BOARD_InitSDRAMPins(void);
#define BOARD_INITCSIPINS_IOMUXC_GPR_GPR26_GPIO_MUX1_GPIO_SEL_MASK 0x10U /*!< GPIO1 and GPIO6 share same IO MUX function, GPIO_MUX1 selects one GPIO function: affected bits mask */
/* GPIO_AD_B1_08 (coord H13), AUD_INT/CSI_D9//J35[13]/J22[4] */
/* Routed pin properties */
#define BOARD_INITCSIPINS_CSI_D9_PERIPHERAL CSI /*!< Peripheral name */
#define BOARD_INITCSIPINS_CSI_D9_SIGNAL csi_data /*!< Signal name */
#define BOARD_INITCSIPINS_CSI_D9_CHANNEL 9U /*!< Signal channel */
/* GPIO_AD_B1_09 (coord M13), SAI1_MCLK/CSI_D8/J35[11] */
/* Routed pin properties */
#define BOARD_INITCSIPINS_CSI_D8_PERIPHERAL CSI /*!< Peripheral name */
#define BOARD_INITCSIPINS_CSI_D8_SIGNAL csi_data /*!< Signal name */
#define BOARD_INITCSIPINS_CSI_D8_CHANNEL 8U /*!< Signal channel */
/* GPIO_AD_B1_10 (coord L13), SAI1_RX_SYNC/CSI_D7/J35[9]/J23[1] */
/* Routed pin properties */
#define BOARD_INITCSIPINS_CSI_D7_PERIPHERAL CSI /*!< Peripheral name */
#define BOARD_INITCSIPINS_CSI_D7_SIGNAL csi_data /*!< Signal name */
#define BOARD_INITCSIPINS_CSI_D7_CHANNEL 7U /*!< Signal channel */
/* GPIO_AD_B1_11 (coord J13), SAI1_RX_BCLK/CSI_D6/J35[7]/J23[2] */
/* Routed pin properties */
#define BOARD_INITCSIPINS_CSI_D6_PERIPHERAL CSI /*!< Peripheral name */
#define BOARD_INITCSIPINS_CSI_D6_SIGNAL csi_data /*!< Signal name */
#define BOARD_INITCSIPINS_CSI_D6_CHANNEL 6U /*!< Signal channel */
/* GPIO_AD_B1_12 (coord H12), SAI1_RXD/CSI_D5/J35[5]/U13[16] */
/* Routed pin properties */
#define BOARD_INITCSIPINS_CSI_D5_PERIPHERAL CSI /*!< Peripheral name */
#define BOARD_INITCSIPINS_CSI_D5_SIGNAL csi_data /*!< Signal name */
#define BOARD_INITCSIPINS_CSI_D5_CHANNEL 5U /*!< Signal channel */
/* GPIO_AD_B1_13 (coord H11), SAI1_TXD/CSI_D4/J35[3]/U13[14] */
/* Routed pin properties */
#define BOARD_INITCSIPINS_CSI_D4_PERIPHERAL CSI /*!< Peripheral name */
#define BOARD_INITCSIPINS_CSI_D4_SIGNAL csi_data /*!< Signal name */
#define BOARD_INITCSIPINS_CSI_D4_CHANNEL 4U /*!< Signal channel */
/* GPIO_AD_B1_15 (coord J14), SAI1_TX_SYNC/CSI_D2/J35[6]/U13[13] */
/* Routed pin properties */
#define BOARD_INITCSIPINS_CSI_D2_PERIPHERAL CSI /*!< Peripheral name */
#define BOARD_INITCSIPINS_CSI_D2_SIGNAL csi_data /*!< Signal name */
#define BOARD_INITCSIPINS_CSI_D2_CHANNEL 2U /*!< Signal channel */
/* GPIO_AD_B1_14 (coord G12), SAI1_TX_BCLK/CSI_D3/J35[4]/U13[12] */
/* Routed pin properties */
#define BOARD_INITCSIPINS_CSI_D3_PERIPHERAL CSI /*!< Peripheral name */
#define BOARD_INITCSIPINS_CSI_D3_SIGNAL csi_data /*!< Signal name */
#define BOARD_INITCSIPINS_CSI_D3_CHANNEL 3U /*!< Signal channel */
/* GPIO_AD_B1_04 (coord L12), CSI_PIXCLK/J35[8]/J23[3] */
/* Routed pin properties */
#define BOARD_INITCSIPINS_CSI_PIXCLK_PERIPHERAL CSI /*!< Peripheral name */
#define BOARD_INITCSIPINS_CSI_PIXCLK_SIGNAL csi_pixclk /*!< Signal name */
/* GPIO_AD_B1_05 (coord K12), CSI_MCLK/J35[12]/J23[4] */
/* Routed pin properties */
#define BOARD_INITCSIPINS_CSI_MCLK_PERIPHERAL CSI /*!< Peripheral name */
#define BOARD_INITCSIPINS_CSI_MCLK_SIGNAL csi_mclk /*!< Signal name */
/* GPIO_AD_B1_06 (coord J12), CSI_VSYNC/J35[18]/J22[2]/UART_TX */
/* Routed pin properties */
#define BOARD_INITCSIPINS_CSI_VSYNC_PERIPHERAL CSI /*!< Peripheral name */
#define BOARD_INITCSIPINS_CSI_VSYNC_SIGNAL csi_vsync /*!< Signal name */
/* GPIO_AD_B1_07 (coord K10), CSI_HSYNC/J35[16]/J22[1]/UART_RX */
/* Routed pin properties */
#define BOARD_INITCSIPINS_CSI_HSYNC_PERIPHERAL CSI /*!< Peripheral name */
#define BOARD_INITCSIPINS_CSI_HSYNC_SIGNAL csi_hsync /*!< Signal name */
/* GPIO_AD_B1_00 (coord J11), I2C1_SCL/CSI_I2C_SCL/J35[20]/J23[6]/U13[17]/U32[4] */
/* Routed pin properties */
#define BOARD_INITCSIPINS_CSI_I2C_SCL_PERIPHERAL LPI2C1 /*!< Peripheral name */
#define BOARD_INITCSIPINS_CSI_I2C_SCL_SIGNAL SCL /*!< Signal name */
/* GPIO_AD_B1_01 (coord K11), I2C1_SDA/CSI_I2C_SDA/J35[22]/J23[5]/U13[18]/U32[6] */
/* Routed pin properties */
#define BOARD_INITCSIPINS_CSI_I2C_SDA_PERIPHERAL LPI2C1 /*!< Peripheral name */
#define BOARD_INITCSIPINS_CSI_I2C_SDA_SIGNAL SDA /*!< Signal name */
/* GPIO_AD_B0_04 (coord F11), CSI_PWDN/J35[17]/BOOT_MODE[0] */
/* Routed pin properties */
#define BOARD_INITCSIPINS_CSI_PWDN_PERIPHERAL GPIO1 /*!< Peripheral name */
#define BOARD_INITCSIPINS_CSI_PWDN_SIGNAL gpio_io /*!< Signal name */
#define BOARD_INITCSIPINS_CSI_PWDN_CHANNEL 4U /*!< Signal channel */
/* Symbols to be used with GPIO driver */
#define BOARD_INITCSIPINS_CSI_PWDN_GPIO GPIO1 /*!< GPIO peripheral base pointer */
#define BOARD_INITCSIPINS_CSI_PWDN_GPIO_PIN 4U /*!< GPIO pin number */
#define BOARD_INITCSIPINS_CSI_PWDN_GPIO_PIN_MASK (1U << 4U) /*!< GPIO pin mask */
#define BOARD_INITCSIPINS_CSI_PWDN_PORT GPIO1 /*!< PORT peripheral base pointer */
#define BOARD_INITCSIPINS_CSI_PWDN_PIN 4U /*!< PORT pin number */
#define BOARD_INITCSIPINS_CSI_PWDN_PIN_MASK (1U << 4U) /*!< PORT pin mask */
/*!
* @brief Configures pin routing and optionally pin electrical features.
*
*/
void BOARD_InitCSIPins(void);
#define BOARD_INITLCDPINS_IOMUXC_GPR_GPR26_GPIO_MUX1_GPIO_SEL_MASK 0x04U /*!< GPIO1 and GPIO6 share same IO MUX function, GPIO_MUX1 selects one GPIO function: affected bits mask */
#define BOARD_INITLCDPINS_IOMUXC_GPR_GPR27_GPIO_MUX2_GPIO_SEL_MASK 0x80000000U /*!< GPIO2 and GPIO7 share same IO MUX function, GPIO_MUX2 selects one GPIO function: affected bits mask */
/* GPIO_B0_04 (coord C8), LCDIF_D0/BT_CFG[0] */
/* Routed pin properties */
#define BOARD_INITLCDPINS_LCDIF_D0_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITLCDPINS_LCDIF_D0_SIGNAL lcdif_data /*!< Signal name */
#define BOARD_INITLCDPINS_LCDIF_D0_CHANNEL 0U /*!< Signal channel */
/* GPIO_B0_05 (coord B8), LCDIF_D1/BT_CFG[1] */
/* Routed pin properties */
#define BOARD_INITLCDPINS_LCDIF_D1_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITLCDPINS_LCDIF_D1_SIGNAL lcdif_data /*!< Signal name */
#define BOARD_INITLCDPINS_LCDIF_D1_CHANNEL 1U /*!< Signal channel */
/* GPIO_B0_06 (coord A8), LCDIF_D2/BT_CFG[2] */
/* Routed pin properties */
#define BOARD_INITLCDPINS_LCDIF_D2_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITLCDPINS_LCDIF_D2_SIGNAL lcdif_data /*!< Signal name */
#define BOARD_INITLCDPINS_LCDIF_D2_CHANNEL 2U /*!< Signal channel */
/* GPIO_B0_00 (coord D7), LCDIF_CLK */
/* Routed pin properties */
#define BOARD_INITLCDPINS_LCDIF_CLK_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITLCDPINS_LCDIF_CLK_SIGNAL lcdif_clk /*!< Signal name */
/* GPIO_B0_07 (coord A9), LCDIF_D3/BT_CFG[3] */
/* Routed pin properties */
#define BOARD_INITLCDPINS_LCDIF_D3_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITLCDPINS_LCDIF_D3_SIGNAL lcdif_data /*!< Signal name */
#define BOARD_INITLCDPINS_LCDIF_D3_CHANNEL 3U /*!< Signal channel */
/* GPIO_B0_08 (coord B9), LCDIF_D4/BT_CFG[4] */
/* Routed pin properties */
#define BOARD_INITLCDPINS_LCDIF_D4_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITLCDPINS_LCDIF_D4_SIGNAL lcdif_data /*!< Signal name */
#define BOARD_INITLCDPINS_LCDIF_D4_CHANNEL 4U /*!< Signal channel */
/* GPIO_B0_09 (coord C9), LCDIF_D5/BT_CFG[5] */
/* Routed pin properties */
#define BOARD_INITLCDPINS_LCDIF_D5_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITLCDPINS_LCDIF_D5_SIGNAL lcdif_data /*!< Signal name */
#define BOARD_INITLCDPINS_LCDIF_D5_CHANNEL 5U /*!< Signal channel */
/* GPIO_B0_10 (coord D9), LCDIF_D6/BT_CFG[6] */
/* Routed pin properties */
#define BOARD_INITLCDPINS_LCDIF_D6_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITLCDPINS_LCDIF_D6_SIGNAL lcdif_data /*!< Signal name */
#define BOARD_INITLCDPINS_LCDIF_D6_CHANNEL 6U /*!< Signal channel */
/* GPIO_B0_11 (coord A10), LCDIF_D7/BT_CFG[7] */
/* Routed pin properties */
#define BOARD_INITLCDPINS_LCDIF_D7_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITLCDPINS_LCDIF_D7_SIGNAL lcdif_data /*!< Signal name */
#define BOARD_INITLCDPINS_LCDIF_D7_CHANNEL 7U /*!< Signal channel */
/* GPIO_B0_12 (coord C10), LCDIF_D8/BT_CFG[8] */
/* Routed pin properties */
#define BOARD_INITLCDPINS_LCDIF_D8_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITLCDPINS_LCDIF_D8_SIGNAL lcdif_data /*!< Signal name */
#define BOARD_INITLCDPINS_LCDIF_D8_CHANNEL 8U /*!< Signal channel */
/* GPIO_B0_13 (coord D10), LCDIF_D9/BT_CFG[9] */
/* Routed pin properties */
#define BOARD_INITLCDPINS_LCDIF_D9_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITLCDPINS_LCDIF_D9_SIGNAL lcdif_data /*!< Signal name */
#define BOARD_INITLCDPINS_LCDIF_D9_CHANNEL 9U /*!< Signal channel */
/* GPIO_B0_14 (coord E10), LCDIF_D10/BT_CFG[10] */
/* Routed pin properties */
#define BOARD_INITLCDPINS_LCDIF_D10_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITLCDPINS_LCDIF_D10_SIGNAL lcdif_data /*!< Signal name */
#define BOARD_INITLCDPINS_LCDIF_D10_CHANNEL 10U /*!< Signal channel */
/* GPIO_B0_15 (coord E11), LCDIF_D11/BT_CFG[11] */
/* Routed pin properties */
#define BOARD_INITLCDPINS_LCDIF_D11_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITLCDPINS_LCDIF_D11_SIGNAL lcdif_data /*!< Signal name */
#define BOARD_INITLCDPINS_LCDIF_D11_CHANNEL 11U /*!< Signal channel */
/* GPIO_B1_00 (coord A11), LCDIF_D12 */
/* Routed pin properties */
#define BOARD_INITLCDPINS_LCDIF_D12_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITLCDPINS_LCDIF_D12_SIGNAL lcdif_data /*!< Signal name */
#define BOARD_INITLCDPINS_LCDIF_D12_CHANNEL 12U /*!< Signal channel */
/* GPIO_B1_01 (coord B11), LCDIF_D13 */
/* Routed pin properties */
#define BOARD_INITLCDPINS_LCDIF_D13_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITLCDPINS_LCDIF_D13_SIGNAL lcdif_data /*!< Signal name */
#define BOARD_INITLCDPINS_LCDIF_D13_CHANNEL 13U /*!< Signal channel */
/* GPIO_B1_02 (coord C11), LCDIF_D14 */
/* Routed pin properties */
#define BOARD_INITLCDPINS_LCDIF_D14_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITLCDPINS_LCDIF_D14_SIGNAL lcdif_data /*!< Signal name */
#define BOARD_INITLCDPINS_LCDIF_D14_CHANNEL 14U /*!< Signal channel */
/* GPIO_B1_03 (coord D11), LCDIF_D15 */
/* Routed pin properties */
#define BOARD_INITLCDPINS_LCDIF_D15_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITLCDPINS_LCDIF_D15_SIGNAL lcdif_data /*!< Signal name */
#define BOARD_INITLCDPINS_LCDIF_D15_CHANNEL 15U /*!< Signal channel */
/* GPIO_B0_01 (coord E7), LCDIF_ENABLE */
/* Routed pin properties */
#define BOARD_INITLCDPINS_LCDIF_ENABLE_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITLCDPINS_LCDIF_ENABLE_SIGNAL lcdif_enable /*!< Signal name */
/* GPIO_B0_02 (coord E8), LCDIF_HSYNC */
/* Routed pin properties */
#define BOARD_INITLCDPINS_LCDIF_HSYNC_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITLCDPINS_LCDIF_HSYNC_SIGNAL lcdif_hsync /*!< Signal name */
/* GPIO_B0_03 (coord D8), LCDIF_VSYNC */
/* Routed pin properties */
#define BOARD_INITLCDPINS_LCDIF_VSYNC_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITLCDPINS_LCDIF_VSYNC_SIGNAL lcdif_vsync /*!< Signal name */
/* GPIO_B1_15 (coord B14), USB_HOST_PWR/BACKLIGHT_CTL */
/* Routed pin properties */
#define BOARD_INITLCDPINS_BACKLIGHT_CTL_PERIPHERAL GPIO2 /*!< Peripheral name */
#define BOARD_INITLCDPINS_BACKLIGHT_CTL_SIGNAL gpio_io /*!< Signal name */
#define BOARD_INITLCDPINS_BACKLIGHT_CTL_CHANNEL 31U /*!< Signal channel */
/* Symbols to be used with GPIO driver */
#define BOARD_INITLCDPINS_BACKLIGHT_CTL_GPIO GPIO2 /*!< GPIO peripheral base pointer */
#define BOARD_INITLCDPINS_BACKLIGHT_CTL_GPIO_PIN 31U /*!< GPIO pin number */
#define BOARD_INITLCDPINS_BACKLIGHT_CTL_GPIO_PIN_MASK (1U << 31U) /*!< GPIO pin mask */
#define BOARD_INITLCDPINS_BACKLIGHT_CTL_PORT GPIO2 /*!< PORT peripheral base pointer */
#define BOARD_INITLCDPINS_BACKLIGHT_CTL_PIN 31U /*!< PORT pin number */
#define BOARD_INITLCDPINS_BACKLIGHT_CTL_PIN_MASK (1U << 31U) /*!< PORT pin mask */
/*!
* @brief Configures pin routing and optionally pin electrical features.
*
*/
void BOARD_InitLCDPins(void);
/* GPIO_AD_B0_14 (coord H14), CAN2_TX/U12[1] */
/* Routed pin properties */
#define BOARD_INITCANPINS_CAN2_TX_PERIPHERAL CAN2 /*!< Peripheral name */
#define BOARD_INITCANPINS_CAN2_TX_SIGNAL TX /*!< Signal name */
/* GPIO_AD_B0_15 (coord L10), CAN2_RX/U12[4] */
/* Routed pin properties */
#define BOARD_INITCANPINS_CAN2_RX_PERIPHERAL CAN2 /*!< Peripheral name */
#define BOARD_INITCANPINS_CAN2_RX_SIGNAL RX /*!< Signal name */
/*!
* @brief Configures pin routing and optionally pin electrical features.
*
*/
void BOARD_InitCANPins(void);
/* GPIO_EMC_40 (coord A7), ENET_MDC */
/* Routed pin properties */
#define BOARD_INITENETPINS_ENET_MDC_PERIPHERAL ENET /*!< Peripheral name */
#define BOARD_INITENETPINS_ENET_MDC_SIGNAL enet_mdc /*!< Signal name */
/* GPIO_EMC_41 (coord C7), ENET_MDIO */
/* Routed pin properties */
#define BOARD_INITENETPINS_ENET_MDIO_PERIPHERAL ENET /*!< Peripheral name */
#define BOARD_INITENETPINS_ENET_MDIO_SIGNAL enet_mdio /*!< Signal name */
/* GPIO_B1_10 (coord B13), ENET_TX_CLK */
/* Routed pin properties */
#define BOARD_INITENETPINS_ENET_TX_CLK_PERIPHERAL ENET /*!< Peripheral name */
#define BOARD_INITENETPINS_ENET_TX_CLK_SIGNAL enet_ref_clk /*!< Signal name */
/* GPIO_B1_04 (coord E12), ENET_RXD0 */
/* Routed pin properties */
#define BOARD_INITENETPINS_ENET_RXD0_PERIPHERAL ENET /*!< Peripheral name */
#define BOARD_INITENETPINS_ENET_RXD0_SIGNAL enet_rx_data /*!< Signal name */
#define BOARD_INITENETPINS_ENET_RXD0_CHANNEL 0U /*!< Signal channel */
/* GPIO_B1_05 (coord D12), ENET_RXD1 */
/* Routed pin properties */
#define BOARD_INITENETPINS_ENET_RXD1_PERIPHERAL ENET /*!< Peripheral name */
#define BOARD_INITENETPINS_ENET_RXD1_SIGNAL enet_rx_data /*!< Signal name */
#define BOARD_INITENETPINS_ENET_RXD1_CHANNEL 1U /*!< Signal channel */
/* GPIO_B1_06 (coord C12), ENET_CRS_DV */
/* Routed pin properties */
#define BOARD_INITENETPINS_ENET_CRS_DV_PERIPHERAL ENET /*!< Peripheral name */
#define BOARD_INITENETPINS_ENET_CRS_DV_SIGNAL enet_rx_en /*!< Signal name */
/* GPIO_B1_11 (coord C13), ENET_RXER */
/* Routed pin properties */
#define BOARD_INITENETPINS_ENET_RXER_PERIPHERAL ENET /*!< Peripheral name */
#define BOARD_INITENETPINS_ENET_RXER_SIGNAL enet_rx_er /*!< Signal name */
/* GPIO_B1_07 (coord B12), ENET_TXD0 */
/* Routed pin properties */
#define BOARD_INITENETPINS_ENET_TXD0_PERIPHERAL ENET /*!< Peripheral name */
#define BOARD_INITENETPINS_ENET_TXD0_SIGNAL enet_tx_data /*!< Signal name */
#define BOARD_INITENETPINS_ENET_TXD0_CHANNEL 0U /*!< Signal channel */
/* GPIO_B1_08 (coord A12), ENET_TXD1 */
/* Routed pin properties */
#define BOARD_INITENETPINS_ENET_TXD1_PERIPHERAL ENET /*!< Peripheral name */
#define BOARD_INITENETPINS_ENET_TXD1_SIGNAL enet_tx_data /*!< Signal name */
#define BOARD_INITENETPINS_ENET_TXD1_CHANNEL 1U /*!< Signal channel */
/* GPIO_B1_09 (coord A13), ENET_TXEN */
/* Routed pin properties */
#define BOARD_INITENETPINS_ENET_TXEN_PERIPHERAL ENET /*!< Peripheral name */
#define BOARD_INITENETPINS_ENET_TXEN_SIGNAL enet_tx_en /*!< Signal name */
/*!
* @brief Configures pin routing and optionally pin electrical features.
*
*/
void BOARD_InitENETPins(void);
/* GPIO_SD_B0_05 (coord J2), SD1_D3 */
/* Routed pin properties */
#define BOARD_INITUSDHCPINS_SD1_D3_PERIPHERAL USDHC1 /*!< Peripheral name */
#define BOARD_INITUSDHCPINS_SD1_D3_SIGNAL usdhc_data /*!< Signal name */
#define BOARD_INITUSDHCPINS_SD1_D3_CHANNEL 3U /*!< Signal channel */
/* GPIO_SD_B0_04 (coord H2), SD1_D2 */
/* Routed pin properties */
#define BOARD_INITUSDHCPINS_SD1_D2_PERIPHERAL USDHC1 /*!< Peripheral name */
#define BOARD_INITUSDHCPINS_SD1_D2_SIGNAL usdhc_data /*!< Signal name */
#define BOARD_INITUSDHCPINS_SD1_D2_CHANNEL 2U /*!< Signal channel */
/* GPIO_SD_B0_03 (coord K1), SD1_D1/J24[5]/SPI_MISO */
/* Routed pin properties */
#define BOARD_INITUSDHCPINS_SD1_D1_PERIPHERAL USDHC1 /*!< Peripheral name */
#define BOARD_INITUSDHCPINS_SD1_D1_SIGNAL usdhc_data /*!< Signal name */
#define BOARD_INITUSDHCPINS_SD1_D1_CHANNEL 1U /*!< Signal channel */
/* GPIO_SD_B0_02 (coord J1), SD1_D0/J24[4]/SPI_MOSI/PWM */
/* Routed pin properties */
#define BOARD_INITUSDHCPINS_SD1_D0_PERIPHERAL USDHC1 /*!< Peripheral name */
#define BOARD_INITUSDHCPINS_SD1_D0_SIGNAL usdhc_data /*!< Signal name */
#define BOARD_INITUSDHCPINS_SD1_D0_CHANNEL 0U /*!< Signal channel */
/* GPIO_SD_B0_00 (coord J4), SD1_CMD/J24[6] */
/* Routed pin properties */
#define BOARD_INITUSDHCPINS_SD1_CMD_PERIPHERAL USDHC1 /*!< Peripheral name */
#define BOARD_INITUSDHCPINS_SD1_CMD_SIGNAL usdhc_cmd /*!< Signal name */
/* GPIO_SD_B0_01 (coord J3), SD1_CLK/J24[3] */
/* Routed pin properties */
#define BOARD_INITUSDHCPINS_SD1_CLK_PERIPHERAL USDHC1 /*!< Peripheral name */
#define BOARD_INITUSDHCPINS_SD1_CLK_SIGNAL usdhc_clk /*!< Signal name */
/* GPIO_B1_14 (coord C14), SD0_VSELECT */
/* Routed pin properties */
#define BOARD_INITUSDHCPINS_SD0_VSELECT_PERIPHERAL USDHC1 /*!< Peripheral name */
#define BOARD_INITUSDHCPINS_SD0_VSELECT_SIGNAL usdhc_vselect /*!< Signal name */
/*!
* @brief Configures pin routing and optionally pin electrical features.
*
*/
void BOARD_InitUSDHCPins(void);
/* GPIO_SD_B1_08 (coord P3), FlexSPI_D0_A */
/* Routed pin properties */
#define BOARD_INITQSPIPINS_FlexSPI_D0_A_PERIPHERAL FLEXSPI /*!< Peripheral name */
#define BOARD_INITQSPIPINS_FlexSPI_D0_A_SIGNAL FLEXSPI_A_DATA0 /*!< Signal name */
/* GPIO_SD_B1_09 (coord N4), FlexSPI_D1_A */
/* Routed pin properties */
#define BOARD_INITQSPIPINS_FlexSPI_D1_A_PERIPHERAL FLEXSPI /*!< Peripheral name */
#define BOARD_INITQSPIPINS_FlexSPI_D1_A_SIGNAL FLEXSPI_A_DATA1 /*!< Signal name */
/* GPIO_SD_B1_10 (coord P4), FlexSPI_D2_A */
/* Routed pin properties */
#define BOARD_INITQSPIPINS_FlexSPI_D2_A_PERIPHERAL FLEXSPI /*!< Peripheral name */
#define BOARD_INITQSPIPINS_FlexSPI_D2_A_SIGNAL FLEXSPI_A_DATA2 /*!< Signal name */
/* GPIO_SD_B1_11 (coord P5), FlexSPI_D3_A */
/* Routed pin properties */
#define BOARD_INITQSPIPINS_FlexSPI_D3_A_PERIPHERAL FLEXSPI /*!< Peripheral name */
#define BOARD_INITQSPIPINS_FlexSPI_D3_A_SIGNAL FLEXSPI_A_DATA3 /*!< Signal name */
/* GPIO_SD_B1_07 (coord L4), FlexSPI_CLK */
/* Routed pin properties */
#define BOARD_INITQSPIPINS_FlexSPI_CLK_PERIPHERAL FLEXSPI /*!< Peripheral name */
#define BOARD_INITQSPIPINS_FlexSPI_CLK_SIGNAL FLEXSPI_A_SCLK /*!< Signal name */
/* GPIO_SD_B1_06 (coord L3), FlexSPI_SS0 */
/* Routed pin properties */
#define BOARD_INITQSPIPINS_FlexSPI_SS0_PERIPHERAL FLEXSPI /*!< Peripheral name */
#define BOARD_INITQSPIPINS_FlexSPI_SS0_SIGNAL FLEXSPI_A_SS0_B /*!< Signal name */
/* GPIO_SD_B1_05 (coord N3), FlexSPI_DQS */
/* Routed pin properties */
#define BOARD_INITQSPIPINS_FlexSPI_DQS_PERIPHERAL FLEXSPI /*!< Peripheral name */
#define BOARD_INITQSPIPINS_FlexSPI_DQS_SIGNAL FLEXSPI_A_DQS /*!< Signal name */
/*!
* @brief Configures pin routing and optionally pin electrical features.
*
*/
void BOARD_InitQSPIPins(void);
#if defined(__cplusplus)
}
#endif
/*!
* @}
*/
#endif /* _PIN_MUX_H_ */
/***********************************************************************************************************************
* EOF
**********************************************************************************************************************/

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managed_components/espressif__tinyusb/hw/bsp/imxrt/boards/mimxrt1060_evk/evkmimxrt1060_flexspi_nor_config.c Normal file
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/*
* Copyright 2018 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "evkmimxrt1060_flexspi_nor_config.h"
/* Component ID definition, used by tools. */
#ifndef FSL_COMPONENT_ID
#define FSL_COMPONENT_ID "platform.drivers.xip_board"
#endif
/*******************************************************************************
* Code
******************************************************************************/
#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
__attribute__((section(".boot_hdr.conf")))
#elif defined(__ICCARM__)
#pragma location = ".boot_hdr.conf"
#endif
const flexspi_nor_config_t qspiflash_config = {
.memConfig =
{
.tag = FLEXSPI_CFG_BLK_TAG,
.version = FLEXSPI_CFG_BLK_VERSION,
.readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad,
.csHoldTime = 3u,
.csSetupTime = 3u,
// Enable DDR mode, Wordaddassable, Safe configuration, Differential clock
.sflashPadType = kSerialFlash_4Pads,
.serialClkFreq = kFlexSpiSerialClk_100MHz,
.sflashA1Size = 8u * 1024u * 1024u,
.lookupTable =
{
// Read LUTs
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18),
FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04),
},
},
.pageSize = 256u,
.sectorSize = 4u * 1024u,
.blockSize = 256u * 1024u,
.isUniformBlockSize = false,
};
#endif /* XIP_BOOT_HEADER_ENABLE */

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/*
* Copyright 2018 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __EVKMIMXRT1060_FLEXSPI_NOR_CONFIG__
#define __EVKMIMXRT1060_FLEXSPI_NOR_CONFIG__
#include <stdint.h>
#include <stdbool.h>
#include "fsl_common.h"
/*! @name Driver version */
/*@{*/
/*! @brief XIP_BOARD driver version 2.0.0. */
#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
/*@}*/
/* FLEXSPI memory config block related definitions */
#define FLEXSPI_CFG_BLK_TAG (0x42464346UL) // ascii "FCFB" Big Endian
#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0
#define FLEXSPI_CFG_BLK_SIZE (512)
/* FLEXSPI Feature related definitions */
#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1
/* Lookup table related definitions */
#define CMD_INDEX_READ 0
#define CMD_INDEX_READSTATUS 1
#define CMD_INDEX_WRITEENABLE 2
#define CMD_INDEX_WRITE 4
#define CMD_LUT_SEQ_IDX_READ 0
#define CMD_LUT_SEQ_IDX_READSTATUS 1
#define CMD_LUT_SEQ_IDX_WRITEENABLE 3
#define CMD_LUT_SEQ_IDX_WRITE 9
#define CMD_SDR 0x01
#define CMD_DDR 0x21
#define RADDR_SDR 0x02
#define RADDR_DDR 0x22
#define CADDR_SDR 0x03
#define CADDR_DDR 0x23
#define MODE1_SDR 0x04
#define MODE1_DDR 0x24
#define MODE2_SDR 0x05
#define MODE2_DDR 0x25
#define MODE4_SDR 0x06
#define MODE4_DDR 0x26
#define MODE8_SDR 0x07
#define MODE8_DDR 0x27
#define WRITE_SDR 0x08
#define WRITE_DDR 0x28
#define READ_SDR 0x09
#define READ_DDR 0x29
#define LEARN_SDR 0x0A
#define LEARN_DDR 0x2A
#define DATSZ_SDR 0x0B
#define DATSZ_DDR 0x2B
#define DUMMY_SDR 0x0C
#define DUMMY_DDR 0x2C
#define DUMMY_RWDS_SDR 0x0D
#define DUMMY_RWDS_DDR 0x2D
#define JMP_ON_CS 0x1F
#define STOP 0
#define FLEXSPI_1PAD 0
#define FLEXSPI_2PAD 1
#define FLEXSPI_4PAD 2
#define FLEXSPI_8PAD 3
#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \
(FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \
FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))
//!@brief Definitions for FlexSPI Serial Clock Frequency
typedef enum _FlexSpiSerialClockFreq
{
kFlexSpiSerialClk_30MHz = 1,
kFlexSpiSerialClk_50MHz = 2,
kFlexSpiSerialClk_60MHz = 3,
kFlexSpiSerialClk_75MHz = 4,
kFlexSpiSerialClk_80MHz = 5,
kFlexSpiSerialClk_100MHz = 6,
kFlexSpiSerialClk_120MHz = 7,
kFlexSpiSerialClk_133MHz = 8,
kFlexSpiSerialClk_166MHz = 9,
} flexspi_serial_clk_freq_t;
//!@brief FlexSPI clock configuration type
enum
{
kFlexSpiClk_SDR, //!< Clock configure for SDR mode
kFlexSpiClk_DDR, //!< Clock configurat for DDR mode
};
//!@brief FlexSPI Read Sample Clock Source definition
typedef enum _FlashReadSampleClkSource
{
kFlexSPIReadSampleClk_LoopbackInternally = 0,
kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1,
kFlexSPIReadSampleClk_LoopbackFromSckPad = 2,
kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3,
} flexspi_read_sample_clk_t;
//!@brief Misc feature bit definitions
enum
{
kFlexSpiMiscOffset_DiffClkEnable = 0, //!< Bit for Differential clock enable
kFlexSpiMiscOffset_Ck2Enable = 1, //!< Bit for CK2 enable
kFlexSpiMiscOffset_ParallelEnable = 2, //!< Bit for Parallel mode enable
kFlexSpiMiscOffset_WordAddressableEnable = 3, //!< Bit for Word Addressable enable
kFlexSpiMiscOffset_SafeConfigFreqEnable = 4, //!< Bit for Safe Configuration Frequency enable
kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, //!< Bit for Pad setting override enable
kFlexSpiMiscOffset_DdrModeEnable = 6, //!< Bit for DDR clock confiuration indication.
};
//!@brief Flash Type Definition
enum
{
kFlexSpiDeviceType_SerialNOR = 1, //!< Flash devices are Serial NOR
kFlexSpiDeviceType_SerialNAND = 2, //!< Flash devices are Serial NAND
kFlexSpiDeviceType_SerialRAM = 3, //!< Flash devices are Serial RAM/HyperFLASH
kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND
kFlexSpiDeviceType_MCP_NOR_RAM = 0x13, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial RAMs
};
//!@brief Flash Pad Definitions
enum
{
kSerialFlash_1Pad = 1,
kSerialFlash_2Pads = 2,
kSerialFlash_4Pads = 4,
kSerialFlash_8Pads = 8,
};
//!@brief FlexSPI LUT Sequence structure
typedef struct _lut_sequence
{
uint8_t seqNum; //!< Sequence Number, valid number: 1-16
uint8_t seqId; //!< Sequence Index, valid number: 0-15
uint16_t reserved;
} flexspi_lut_seq_t;
//!@brief Flash Configuration Command Type
enum
{
kDeviceConfigCmdType_Generic, //!< Generic command, for example: configure dummy cycles, drive strength, etc
kDeviceConfigCmdType_QuadEnable, //!< Quad Enable command
kDeviceConfigCmdType_Spi2Xpi, //!< Switch from SPI to DPI/QPI/OPI mode
kDeviceConfigCmdType_Xpi2Spi, //!< Switch from DPI/QPI/OPI to SPI mode
kDeviceConfigCmdType_Spi2NoCmd, //!< Switch to 0-4-4/0-8-8 mode
kDeviceConfigCmdType_Reset, //!< Reset device command
};
//!@brief FlexSPI Memory Configuration Block
typedef struct _FlexSPIConfig
{
uint32_t tag; //!< [0x000-0x003] Tag, fixed value 0x42464346UL
uint32_t version; //!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix
uint32_t reserved0; //!< [0x008-0x00b] Reserved for future use
uint8_t readSampleClkSrc; //!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3
uint8_t csHoldTime; //!< [0x00d-0x00d] CS hold time, default value: 3
uint8_t csSetupTime; //!< [0x00e-0x00e] CS setup time, default value: 3
uint8_t columnAddressWidth; //!< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For
//! Serial NAND, need to refer to datasheet
uint8_t deviceModeCfgEnable; //!< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable
uint8_t deviceModeType; //!< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch,
//! Generic configuration, etc.
uint16_t waitTimeCfgCommands; //!< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for
//! DPI/QPI/OPI switch or reset command
flexspi_lut_seq_t deviceModeSeq; //!< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt
//! sequence number, [31:16] Reserved
uint32_t deviceModeArg; //!< [0x018-0x01b] Argument/Parameter for device configuration
uint8_t configCmdEnable; //!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable
uint8_t configModeType[3]; //!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe
flexspi_lut_seq_t
configCmdSeqs[3]; //!< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq
uint32_t reserved1; //!< [0x02c-0x02f] Reserved for future use
uint32_t configCmdArgs[3]; //!< [0x030-0x03b] Arguments/Parameters for device Configuration commands
uint32_t reserved2; //!< [0x03c-0x03f] Reserved for future use
uint32_t controllerMiscOption; //!< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more
//! details
uint8_t deviceType; //!< [0x044-0x044] Device Type: See Flash Type Definition for more details
uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal
uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequency, device specific definitions, See System Boot
//! Chapter for more details
uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot
//! be done using 1 LUT sequence, currently, only applicable to HyperFLASH
uint32_t reserved3[2]; //!< [0x048-0x04f] Reserved for future use
uint32_t sflashA1Size; //!< [0x050-0x053] Size of Flash connected to A1
uint32_t sflashA2Size; //!< [0x054-0x057] Size of Flash connected to A2
uint32_t sflashB1Size; //!< [0x058-0x05b] Size of Flash connected to B1
uint32_t sflashB2Size; //!< [0x05c-0x05f] Size of Flash connected to B2
uint32_t csPadSettingOverride; //!< [0x060-0x063] CS pad setting override value
uint32_t sclkPadSettingOverride; //!< [0x064-0x067] SCK pad setting override value
uint32_t dataPadSettingOverride; //!< [0x068-0x06b] data pad setting override value
uint32_t dqsPadSettingOverride; //!< [0x06c-0x06f] DQS pad setting override value
uint32_t timeoutInMs; //!< [0x070-0x073] Timeout threshold for read status command
uint32_t commandInterval; //!< [0x074-0x077] CS deselect interval between two commands
uint16_t dataValidTime[2]; //!< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns
uint16_t busyOffset; //!< [0x07c-0x07d] Busy offset, valid value: 0-31
uint16_t busyBitPolarity; //!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 -
//! busy flag is 0 when flash device is busy
uint32_t lookupTable[64]; //!< [0x080-0x17f] Lookup table holds Flash command sequences
flexspi_lut_seq_t lutCustomSeq[12]; //!< [0x180-0x1af] Customizable LUT Sequences
uint32_t reserved4[4]; //!< [0x1b0-0x1bf] Reserved for future use
} flexspi_mem_config_t;
/* */
#define NOR_CMD_INDEX_READ CMD_INDEX_READ //!< 0
#define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS //!< 1
#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE //!< 2
#define NOR_CMD_INDEX_ERASESECTOR 3 //!< 3
#define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE //!< 4
#define NOR_CMD_INDEX_CHIPERASE 5 //!< 5
#define NOR_CMD_INDEX_DUMMY 6 //!< 6
#define NOR_CMD_INDEX_ERASEBLOCK 7 //!< 7
#define NOR_CMD_LUT_SEQ_IDX_READ CMD_LUT_SEQ_IDX_READ //!< 0 READ LUT sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_READSTATUS \
CMD_LUT_SEQ_IDX_READSTATUS //!< 1 Read Status LUT sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \
2 //!< 2 Read status DPI/QPI/OPI sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE \
CMD_LUT_SEQ_IDX_WRITEENABLE //!< 3 Write Enable sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \
4 //!< 4 Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5 //!< 5 Erase Sector sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8 //!< 8 Erase Block sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM \
CMD_LUT_SEQ_IDX_WRITE //!< 9 Program sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11 //!< 11 Chip Erase sequence in lookupTable id stored in config block
#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13 //!< 13 Read SFDP sequence in lookupTable id stored in config block
#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \
14 //!< 14 Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \
15 //!< 15 Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config blobk
/*
* Serial NOR configuration block
*/
typedef struct _flexspi_nor_config
{
flexspi_mem_config_t memConfig; //!< Common memory configuration info via FlexSPI
uint32_t pageSize; //!< Page size of Serial NOR
uint32_t sectorSize; //!< Sector size of Serial NOR
uint8_t ipcmdSerialClkFreq; //!< Clock frequency for IP command
uint8_t isUniformBlockSize; //!< Sector/Block size is the same
uint8_t reserved0[2]; //!< Reserved for future use
uint8_t serialNorType; //!< Serial NOR Flash type: 0/1/2/3
uint8_t needExitNoCmdMode; //!< Need to exit NoCmd mode before other IP command
uint8_t halfClkForNonReadCmd; //!< Half the Serial Clock for non-read command: true/false
uint8_t needRestoreNoCmdMode; //!< Need to Restore NoCmd mode after IP command execution
uint32_t blockSize; //!< Block size
uint32_t reserve2[11]; //!< Reserved for future use
} flexspi_nor_config_t;
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __cplusplus
}
#endif
#endif /* __EVKMIMXRT1060_FLEXSPI_NOR_CONFIG__ */

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managed_components/espressif__tinyusb/hw/bsp/imxrt/boards/mimxrt1064_evk/board.cmake Normal file
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set(MCU_VARIANT MIMXRT1064)
set(JLINK_DEVICE MIMXRT1064xxx6A)
set(PYOCD_TARGET mimxrt1064)
set(NXPLINK_DEVICE MIMXRT1064xxxxA:EVK-MIMXRT1064)
function(update_board TARGET)
target_sources(${TARGET} PUBLIC
${CMAKE_CURRENT_FUNCTION_LIST_DIR}/evkmimxrt1064_flexspi_nor_config.c
)
target_compile_definitions(${TARGET} PUBLIC
CPU_MIMXRT1064DVL6A
BOARD_TUD_RHPORT=0
BOARD_TUH_RHPORT=1
)
endfunction()

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/*
* The MIT License (MIT)
*
* Copyright (c) 2019, Ha Thach (tinyusb.org)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* This file is part of the TinyUSB stack.
*/
/* metadata:
name: i.MX RT1064 Evaluation Kit
url: https://www.nxp.com/design/design-center/development-boards-and-designs/MIMXRT1064-EVK
*/
#ifndef BOARD_MIMXRT1064_EVKB_H_
#define BOARD_MIMXRT1064_EVKB_H_
// required since iMXRT MCUX-SDK include this file for board size
#define BOARD_FLASH_SIZE (0x400000U)
// LED: IOMUXC_GPIO_AD_B0_09_GPIO1_IO09
#define LED_PORT BOARD_INITPINS_USER_LED_PERIPHERAL
#define LED_PIN BOARD_INITPINS_USER_LED_CHANNEL
#define LED_STATE_ON 0
// SW8 button: IOMUXC_SNVS_WAKEUP_GPIO5_IO00
#define BUTTON_PORT BOARD_INITPINS_USER_BUTTON_PERIPHERAL
#define BUTTON_PIN BOARD_INITPINS_USER_BUTTON_CHANNEL
#define BUTTON_STATE_ACTIVE 0
// UART: IOMUXC_GPIO_AD_B0_13_LPUART1_RX, IOMUXC_GPIO_AD_B0_12_LPUART1_TX
#define UART_PORT LPUART1
#define UART_CLK_ROOT BOARD_BOOTCLOCKRUN_UART_CLK_ROOT
static inline void BOARD_ConfigMPU(void) {
}
#endif

14
managed_components/espressif__tinyusb/hw/bsp/imxrt/boards/mimxrt1064_evk/board.mk Normal file
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CFLAGS += -DCPU_MIMXRT1064DVL6A
MCU_VARIANT = MIMXRT1064
# For flash-jlink target
JLINK_DEVICE = MIMXRT1064xxx6A
# For flash-pyocd target
PYOCD_TARGET = mimxrt1064
BOARD_TUD_RHPORT = 0
BOARD_TUH_RHPORT = 1
# flash using pyocd
flash: flash-pyocd

511
managed_components/espressif__tinyusb/hw/bsp/imxrt/boards/mimxrt1064_evk/board/clock_config.c Normal file
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/*
* How to setup clock using clock driver functions:
*
* 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock.
*
* 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock.
*
* 3. Call CLOCK_SetMux() to configure corresponding clock source for target clock out.
*
* 4. Call CLOCK_SetDiv() to configure corresponding clock divider for target clock out.
*
* 5. Call CLOCK_SetXtalFreq() to set XTAL frequency based on board settings.
*
*/
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!GlobalInfo
product: Clocks v15.0
processor: MIMXRT1064xxxxA
package_id: MIMXRT1064DVL6A
mcu_data: ksdk2_0
processor_version: 24.12.10
board: MIMXRT1064-EVK
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
#include "clock_config.h"
#include "fsl_iomuxc.h"
/*******************************************************************************
* Definitions
******************************************************************************/
/*******************************************************************************
* Variables
******************************************************************************/
/*******************************************************************************
************************ BOARD_InitBootClocks function ************************
******************************************************************************/
void BOARD_InitBootClocks(void)
{
BOARD_BootClockRUN();
}
/*******************************************************************************
********************** Configuration BOARD_BootClockRUN ***********************
******************************************************************************/
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!Configuration
name: BOARD_BootClockRUN
called_from_default_init: true
outputs:
- {id: AHB_CLK_ROOT.outFreq, value: 600 MHz}
- {id: CAN_CLK_ROOT.outFreq, value: 40 MHz}
- {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz}
- {id: CLK_1M.outFreq, value: 1 MHz}
- {id: CLK_24M.outFreq, value: 24 MHz}
- {id: CSI_CLK_ROOT.outFreq, value: 12 MHz}
- {id: ENET2_125M_CLK.outFreq, value: 1.2 MHz}
- {id: ENET_125M_CLK.outFreq, value: 2.4 MHz}
- {id: ENET_25M_REF_CLK.outFreq, value: 1.2 MHz}
- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz}
- {id: FLEXIO2_CLK_ROOT.outFreq, value: 30 MHz}
- {id: FLEXSPI2_CLK_ROOT.outFreq, value: 1440/11 MHz}
- {id: FLEXSPI_CLK_ROOT.outFreq, value: 1440/11 MHz}
- {id: GPT1_ipg_clk_highfreq.outFreq, value: 75 MHz}
- {id: GPT2_ipg_clk_highfreq.outFreq, value: 75 MHz}
- {id: IPG_CLK_ROOT.outFreq, value: 150 MHz}
- {id: LCDIF_CLK_ROOT.outFreq, value: 67.5 MHz}
- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz}
- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz}
- {id: LVDS1_CLK.outFreq, value: 1.2 GHz}
- {id: MQS_MCLK.outFreq, value: 1080/17 MHz}
- {id: PERCLK_CLK_ROOT.outFreq, value: 75 MHz}
- {id: PLL7_MAIN_CLK.outFreq, value: 480 MHz}
- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz}
- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz}
- {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz}
- {id: SAI1_MCLK3.outFreq, value: 30 MHz}
- {id: SAI2_CLK_ROOT.outFreq, value: 1080/17 MHz}
- {id: SAI2_MCLK1.outFreq, value: 1080/17 MHz}
- {id: SAI2_MCLK3.outFreq, value: 30 MHz}
- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz}
- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz}
- {id: SAI3_MCLK3.outFreq, value: 30 MHz}
- {id: SEMC_CLK_ROOT.outFreq, value: 75 MHz}
- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz}
- {id: TRACE_CLK_ROOT.outFreq, value: 132 MHz}
- {id: UART_CLK_ROOT.outFreq, value: 80 MHz}
- {id: USBPHY1_CLK.outFreq, value: 480 MHz}
- {id: USBPHY2_CLK.outFreq, value: 480 MHz}
- {id: USDHC1_CLK_ROOT.outFreq, value: 198 MHz}
- {id: USDHC2_CLK_ROOT.outFreq, value: 198 MHz}
settings:
- {id: CCM.AHB_PODF.scale, value: '1', locked: true}
- {id: CCM.ARM_PODF.scale, value: '2', locked: true}
- {id: CCM.FLEXSPI2_PODF.scale, value: '2', locked: true}
- {id: CCM.FLEXSPI2_SEL.sel, value: CCM_ANALOG.PLL3_PFD0_CLK}
- {id: CCM.FLEXSPI_PODF.scale, value: '2', locked: true}
- {id: CCM.FLEXSPI_SEL.sel, value: CCM_ANALOG.PLL3_PFD0_CLK}
- {id: CCM.LCDIF_PODF.scale, value: '4', locked: true}
- {id: CCM.LCDIF_PRED.scale, value: '2', locked: true}
- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true}
- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true}
- {id: CCM.SEMC_PODF.scale, value: '8'}
- {id: CCM.TRACE_CLK_SEL.sel, value: CCM_ANALOG.PLL2_MAIN_CLK}
- {id: CCM.TRACE_PODF.scale, value: '4', locked: true}
- {id: CCM_ANALOG.PLL1_BYPASS.sel, value: CCM_ANALOG.PLL1}
- {id: CCM_ANALOG.PLL1_PREDIV.scale, value: '1', locked: true}
- {id: CCM_ANALOG.PLL1_VDIV.scale, value: '50', locked: true}
- {id: CCM_ANALOG.PLL2.denom, value: '1', locked: true}
- {id: CCM_ANALOG.PLL2.num, value: '0', locked: true}
- {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK}
- {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0}
- {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1}
- {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2}
- {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3}
- {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3}
- {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0}
- {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '33', locked: true}
- {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true}
- {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1}
- {id: CCM_ANALOG.PLL3_PFD1_DIV.scale, value: '16', locked: true}
- {id: CCM_ANALOG.PLL3_PFD1_MUL.scale, value: '18', locked: true}
- {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2}
- {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3}
- {id: CCM_ANALOG.PLL4.denom, value: '50'}
- {id: CCM_ANALOG.PLL4.div, value: '47'}
- {id: CCM_ANALOG.PLL5.denom, value: '1'}
- {id: CCM_ANALOG.PLL5.div, value: '31', locked: true}
- {id: CCM_ANALOG.PLL5.num, value: '0'}
- {id: CCM_ANALOG.PLL5_BYPASS.sel, value: CCM_ANALOG.PLL5_POST_DIV}
- {id: CCM_ANALOG.PLL5_POST_DIV.scale, value: '2', locked: true}
- {id: CCM_ANALOG.PLL7_BYPASS.sel, value: CCM_ANALOG.PLL7}
- {id: CCM_ANALOG.VIDEO_DIV.scale, value: '4', locked: true}
- {id: CCM_ANALOG_PLL_ENET_POWERDOWN_CFG, value: 'Yes'}
- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_CFG, value: Enabled}
- {id: CCM_ANALOG_PLL_USB1_EN_USB_CLKS_OUT_CFG, value: Enabled}
- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'}
- {id: CCM_ANALOG_PLL_USB2_EN_USB_CLKS_CFG, value: Enabled}
- {id: CCM_ANALOG_PLL_USB2_EN_USB_CLKS_OUT_CFG, value: Enabled}
- {id: CCM_ANALOG_PLL_USB2_POWER_CFG, value: 'Yes'}
- {id: CCM_ANALOG_PLL_VIDEO_POWERDOWN_CFG, value: 'No'}
sources:
- {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/*******************************************************************************
* Variables for BOARD_BootClockRUN configuration
******************************************************************************/
const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN =
{
.loopDivider = 100, /* PLL loop divider, Fout = Fin * 50 */
.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
};
const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN =
{
.loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */
.numerator = 0, /* 30 bit numerator of fractional loop divider */
.denominator = 1, /* 30 bit denominator of fractional loop divider */
.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
};
const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN =
{
.loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */
.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
};
const clock_usb_pll_config_t usb2PllConfig_BOARD_BootClockRUN =
{
.loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */
.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
};
const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN =
{
.loopDivider = 31, /* PLL loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
.postDivider = 8, /* Divider after PLL */
.numerator = 0, /* 30 bit numerator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
.denominator = 1, /* 30 bit denominator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
};
/*******************************************************************************
* Code for BOARD_BootClockRUN configuration
******************************************************************************/
void BOARD_BootClockRUN(void)
{
/* Init RTC OSC clock frequency. */
CLOCK_SetRtcXtalFreq(32768U);
/* Enable 1MHz clock output. */
XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK;
/* Use free 1MHz clock output. */
XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK;
/* Set XTAL 24MHz clock frequency. */
CLOCK_SetXtalFreq(24000000U);
/* Enable XTAL 24MHz clock source. */
CLOCK_InitExternalClk(0);
/* Enable internal RC. */
CLOCK_InitRcOsc24M();
/* Switch clock source to external OSC. */
CLOCK_SwitchOsc(kCLOCK_XtalOsc);
/* Set Oscillator ready counter value. */
CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127);
/* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */
CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */
CLOCK_SetMux(kCLOCK_PeriphMux, 1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */
/* Setting the VDD_SOC to 1.275V. It is necessary to config AHB to 600Mhz. */
DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x13);
/* Waiting for DCDC_STS_DC_OK bit is asserted */
while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0))
{
}
/* Set AHB_PODF. */
CLOCK_SetDiv(kCLOCK_AhbDiv, 0);
/* Disable IPG clock gate. */
CLOCK_DisableClock(kCLOCK_Adc1);
CLOCK_DisableClock(kCLOCK_Adc2);
CLOCK_DisableClock(kCLOCK_Xbar1);
CLOCK_DisableClock(kCLOCK_Xbar2);
CLOCK_DisableClock(kCLOCK_Xbar3);
/* Set IPG_PODF. */
CLOCK_SetDiv(kCLOCK_IpgDiv, 3);
/* Set ARM_PODF. */
CLOCK_SetDiv(kCLOCK_ArmDiv, 1);
/* Set PERIPH_CLK2_PODF. */
CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0);
/* Disable PERCLK clock gate. */
CLOCK_DisableClock(kCLOCK_Gpt1);
CLOCK_DisableClock(kCLOCK_Gpt1S);
CLOCK_DisableClock(kCLOCK_Gpt2);
CLOCK_DisableClock(kCLOCK_Gpt2S);
CLOCK_DisableClock(kCLOCK_Pit);
/* Set PERCLK_PODF. */
CLOCK_SetDiv(kCLOCK_PerclkDiv, 1);
/* Disable USDHC1 clock gate. */
CLOCK_DisableClock(kCLOCK_Usdhc1);
/* Set USDHC1_PODF. */
CLOCK_SetDiv(kCLOCK_Usdhc1Div, 1);
/* Set Usdhc1 clock source. */
CLOCK_SetMux(kCLOCK_Usdhc1Mux, 0);
/* Disable USDHC2 clock gate. */
CLOCK_DisableClock(kCLOCK_Usdhc2);
/* Set USDHC2_PODF. */
CLOCK_SetDiv(kCLOCK_Usdhc2Div, 1);
/* Set Usdhc2 clock source. */
CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0);
/* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
* With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
* Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
#ifndef SKIP_SYSCLK_INIT
/* Disable Semc clock gate. */
CLOCK_DisableClock(kCLOCK_Semc);
/* Set SEMC_PODF. */
CLOCK_SetDiv(kCLOCK_SemcDiv, 7);
/* Set Semc alt clock source. */
CLOCK_SetMux(kCLOCK_SemcAltMux, 0);
/* Set Semc clock source. */
CLOCK_SetMux(kCLOCK_SemcMux, 0);
#endif
/* Disable Flexspi clock gate. */
CLOCK_DisableClock(kCLOCK_FlexSpi);
/* Set FLEXSPI_PODF. */
CLOCK_SetDiv(kCLOCK_FlexspiDiv, 1);
/* Set Flexspi clock source. */
CLOCK_SetMux(kCLOCK_FlexspiMux, 3);
/* In SDK projects, external flash (configured by FLEXSPI2) will be initialized by dcd.
* With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI2 clock source in SDK projects) will be left unchanged.
* Note: If another clock source is selected for FLEXSPI2, user may want to avoid changing that clock as well.*/
#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
/* Disable Flexspi2 clock gate. */
CLOCK_DisableClock(kCLOCK_FlexSpi2);
/* Set FLEXSPI2_PODF. */
CLOCK_SetDiv(kCLOCK_Flexspi2Div, 1);
/* Set Flexspi2 clock source. */
CLOCK_SetMux(kCLOCK_Flexspi2Mux, 1);
#endif
/* Disable CSI clock gate. */
CLOCK_DisableClock(kCLOCK_Csi);
/* Set CSI_PODF. */
CLOCK_SetDiv(kCLOCK_CsiDiv, 1);
/* Set Csi clock source. */
CLOCK_SetMux(kCLOCK_CsiMux, 0);
/* Disable LPSPI clock gate. */
CLOCK_DisableClock(kCLOCK_Lpspi1);
CLOCK_DisableClock(kCLOCK_Lpspi2);
CLOCK_DisableClock(kCLOCK_Lpspi3);
CLOCK_DisableClock(kCLOCK_Lpspi4);
/* Set LPSPI_PODF. */
CLOCK_SetDiv(kCLOCK_LpspiDiv, 4);
/* Set Lpspi clock source. */
CLOCK_SetMux(kCLOCK_LpspiMux, 2);
/* Disable TRACE clock gate. */
CLOCK_DisableClock(kCLOCK_Trace);
/* Set TRACE_PODF. */
CLOCK_SetDiv(kCLOCK_TraceDiv, 3);
/* Set Trace clock source. */
CLOCK_SetMux(kCLOCK_TraceMux, 0);
/* Disable SAI1 clock gate. */
CLOCK_DisableClock(kCLOCK_Sai1);
/* Set SAI1_CLK_PRED. */
CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3);
/* Set SAI1_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_Sai1Div, 1);
/* Set Sai1 clock source. */
CLOCK_SetMux(kCLOCK_Sai1Mux, 0);
/* Disable SAI2 clock gate. */
CLOCK_DisableClock(kCLOCK_Sai2);
/* Set SAI2_CLK_PRED. */
CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3);
/* Set SAI2_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_Sai2Div, 1);
/* Set Sai2 clock source. */
CLOCK_SetMux(kCLOCK_Sai2Mux, 0);
/* Disable SAI3 clock gate. */
CLOCK_DisableClock(kCLOCK_Sai3);
/* Set SAI3_CLK_PRED. */
CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3);
/* Set SAI3_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_Sai3Div, 1);
/* Set Sai3 clock source. */
CLOCK_SetMux(kCLOCK_Sai3Mux, 0);
/* Disable Lpi2c clock gate. */
CLOCK_DisableClock(kCLOCK_Lpi2c1);
CLOCK_DisableClock(kCLOCK_Lpi2c2);
CLOCK_DisableClock(kCLOCK_Lpi2c3);
/* Set LPI2C_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0);
/* Set Lpi2c clock source. */
CLOCK_SetMux(kCLOCK_Lpi2cMux, 0);
/* Disable CAN clock gate. */
CLOCK_DisableClock(kCLOCK_Can1);
CLOCK_DisableClock(kCLOCK_Can2);
CLOCK_DisableClock(kCLOCK_Can3);
CLOCK_DisableClock(kCLOCK_Can1S);
CLOCK_DisableClock(kCLOCK_Can2S);
CLOCK_DisableClock(kCLOCK_Can3S);
/* Set CAN_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_CanDiv, 1);
/* Set Can clock source. */
CLOCK_SetMux(kCLOCK_CanMux, 2);
/* Disable UART clock gate. */
CLOCK_DisableClock(kCLOCK_Lpuart1);
CLOCK_DisableClock(kCLOCK_Lpuart2);
CLOCK_DisableClock(kCLOCK_Lpuart3);
CLOCK_DisableClock(kCLOCK_Lpuart4);
CLOCK_DisableClock(kCLOCK_Lpuart5);
CLOCK_DisableClock(kCLOCK_Lpuart6);
CLOCK_DisableClock(kCLOCK_Lpuart7);
CLOCK_DisableClock(kCLOCK_Lpuart8);
/* Set UART_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_UartDiv, 0);
/* Set Uart clock source. */
CLOCK_SetMux(kCLOCK_UartMux, 0);
/* Disable LCDIF clock gate. */
CLOCK_DisableClock(kCLOCK_LcdPixel);
/* Set LCDIF_PRED. */
CLOCK_SetDiv(kCLOCK_LcdifPreDiv, 1);
/* Set LCDIF_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_LcdifDiv, 3);
/* Set Lcdif pre clock source. */
CLOCK_SetMux(kCLOCK_LcdifPreMux, 5);
/* Disable SPDIF clock gate. */
CLOCK_DisableClock(kCLOCK_Spdif);
/* Set SPDIF0_CLK_PRED. */
CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1);
/* Set SPDIF0_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_Spdif0Div, 7);
/* Set Spdif clock source. */
CLOCK_SetMux(kCLOCK_SpdifMux, 3);
/* Disable Flexio1 clock gate. */
CLOCK_DisableClock(kCLOCK_Flexio1);
/* Set FLEXIO1_CLK_PRED. */
CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1);
/* Set FLEXIO1_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_Flexio1Div, 7);
/* Set Flexio1 clock source. */
CLOCK_SetMux(kCLOCK_Flexio1Mux, 3);
/* Disable Flexio2 clock gate. */
CLOCK_DisableClock(kCLOCK_Flexio2);
/* Set FLEXIO2_CLK_PRED. */
CLOCK_SetDiv(kCLOCK_Flexio2PreDiv, 1);
/* Set FLEXIO2_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_Flexio2Div, 7);
/* Set Flexio2 clock source. */
CLOCK_SetMux(kCLOCK_Flexio2Mux, 3);
/* Set Pll3 sw clock source. */
CLOCK_SetMux(kCLOCK_Pll3SwMux, 0);
/* Init ARM PLL. */
CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN);
/* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
* With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
* Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
#ifndef SKIP_SYSCLK_INIT
#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1)
#warning "SKIP_SYSCLK_INIT should be defined to keep system pll (selected to be SEMC source clock in SDK projects) unchanged."
#endif
/* Init System PLL. */
CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN);
/* Init System pfd0. */
CLOCK_InitSysPfd(kCLOCK_Pfd0, 27);
/* Init System pfd1. */
CLOCK_InitSysPfd(kCLOCK_Pfd1, 16);
/* Init System pfd2. */
CLOCK_InitSysPfd(kCLOCK_Pfd2, 24);
/* Init System pfd3. */
CLOCK_InitSysPfd(kCLOCK_Pfd3, 16);
#endif
/* In SDK projects, external flash (configured by FLEXSPI2) will be initialized by dcd.
* With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI2 clock source in SDK projects) will be left unchanged.
* Note: If another clock source is selected for FLEXSPI2, user may want to avoid changing that clock as well.*/
#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
/* Init Usb1 PLL. */
CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN);
/* Init Usb1 pfd0. */
CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 33);
/* Init Usb1 pfd1. */
CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16);
/* Init Usb1 pfd2. */
CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17);
/* Init Usb1 pfd3. */
CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 19);
#endif
/* DeInit Audio PLL. */
CLOCK_DeinitAudioPll();
/* Bypass Audio PLL. */
CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1);
/* Set divider for Audio PLL. */
CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK;
CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK;
/* Enable Audio PLL output. */
CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK;
/* Init Video PLL. */
uint32_t pllVideo;
/* Disable Video PLL output before initial Video PLL. */
CCM_ANALOG->PLL_VIDEO &= ~CCM_ANALOG_PLL_VIDEO_ENABLE_MASK;
/* Bypass PLL first */
CCM_ANALOG->PLL_VIDEO = (CCM_ANALOG->PLL_VIDEO & (~CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK)) |
CCM_ANALOG_PLL_VIDEO_BYPASS_MASK | CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(0);
CCM_ANALOG->PLL_VIDEO_NUM = CCM_ANALOG_PLL_VIDEO_NUM_A(0);
CCM_ANALOG->PLL_VIDEO_DENOM = CCM_ANALOG_PLL_VIDEO_DENOM_B(1);
pllVideo = (CCM_ANALOG->PLL_VIDEO & (~(CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK | CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK))) |
CCM_ANALOG_PLL_VIDEO_ENABLE_MASK |CCM_ANALOG_PLL_VIDEO_DIV_SELECT(31);
pllVideo |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(1);
CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(3);
CCM_ANALOG->PLL_VIDEO = pllVideo;
while ((CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) == 0)
{
}
/* Disable bypass for Video PLL. */
CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllVideo, 0);
/* DeInit Enet PLL. */
CLOCK_DeinitEnetPll();
/* Bypass Enet PLL. */
CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllEnet, 1);
/* Set Enet output divider. */
CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_DIV_SELECT(1);
/* Enable Enet output. */
CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENABLE_MASK;
/* Set Enet2 output divider. */
CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT(0);
/* Enable Enet2 output. */
CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET2_REF_EN_MASK;
/* Enable Enet25M output. */
CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK;
/* Init Usb2 PLL. */
CLOCK_InitUsb2Pll(&usb2PllConfig_BOARD_BootClockRUN);
/* Set preperiph clock source. */
CLOCK_SetMux(kCLOCK_PrePeriphMux, 3);
/* Set periph clock source. */
CLOCK_SetMux(kCLOCK_PeriphMux, 0);
/* Set periph clock2 clock source. */
CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
/* Set per clock source. */
CLOCK_SetMux(kCLOCK_PerclkMux, 0);
/* Set lvds1 clock source. */
CCM_ANALOG->MISC1 = (CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0);
/* Set clock out1 divider. */
CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0);
/* Set clock out1 source. */
CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1);
/* Set clock out2 divider. */
CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0);
/* Set clock out2 source. */
CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(18);
/* Set clock out1 drives clock out1. */
CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK;
/* Disable clock out1. */
CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK;
/* Disable clock out2. */
CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK;
/* Set SAI1 MCLK1 clock source. */
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0);
/* Set SAI1 MCLK2 clock source. */
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0);
/* Set SAI1 MCLK3 clock source. */
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0);
/* Set SAI2 MCLK3 clock source. */
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0);
/* Set SAI3 MCLK3 clock source. */
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
/* Set MQS configuration. */
IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0);
/* Set ENET Ref clock source. */
IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK;
/* Set ENET2 Ref clock source. */
IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR_MASK;
/* Set GPT1 High frequency reference clock source. */
IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK;
/* Set GPT2 High frequency reference clock source. */
IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK;
/* Set SystemCoreClock variable. */
SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
}

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managed_components/espressif__tinyusb/hw/bsp/imxrt/boards/mimxrt1064_evk/board/clock_config.h Normal file
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#ifndef _CLOCK_CONFIG_H_
#define _CLOCK_CONFIG_H_
#include "fsl_common.h"
/*******************************************************************************
* Definitions
******************************************************************************/
#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */
#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */
/*******************************************************************************
************************ BOARD_InitBootClocks function ************************
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/
/*!
* @brief This function executes default configuration of clocks.
*
*/
void BOARD_InitBootClocks(void);
#if defined(__cplusplus)
}
#endif /* __cplusplus*/
/*******************************************************************************
********************** Configuration BOARD_BootClockRUN ***********************
******************************************************************************/
/*******************************************************************************
* Definitions for BOARD_BootClockRUN configuration
******************************************************************************/
#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 600000000U /*!< Core clock frequency: 600000000Hz */
/* Clock outputs (values are in Hz): */
#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT 600000000UL /* Clock consumers of AHB_CLK_ROOT output : AIPSTZ1, AIPSTZ2, AIPSTZ3, AIPSTZ4, ARM, FLEXIO3, FLEXSPI, FLEXSPI2, GPIO6, GPIO7, GPIO8, GPIO9 */
#define BOARD_BOOTCLOCKRUN_CAN_CLK_ROOT 40000000UL /* Clock consumers of CAN_CLK_ROOT output : CAN1, CAN2, CAN3 */
#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL /* Clock consumers of CKIL_SYNC_CLK_ROOT output : CSU, EWM, GPT1, GPT2, KPP, PIT, RTWDOG, SNVS, SPDIF, TEMPMON, TSC, USB1, USB2, WDOG1, WDOG2 */
#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL /* Clock consumers of CLKO1_CLK output : N/A */
#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL /* Clock consumers of CLKO2_CLK output : N/A */
#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL /* Clock consumers of CLK_1M output : EWM, RTWDOG */
#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL /* Clock consumers of CLK_24M output : GPT1, GPT2 */
#define BOARD_BOOTCLOCKRUN_CSI_CLK_ROOT 12000000UL /* Clock consumers of CSI_CLK_ROOT output : CSI */
#define BOARD_BOOTCLOCKRUN_ENET2_125M_CLK 1200000UL /* Clock consumers of ENET2_125M_CLK output : N/A */
#define BOARD_BOOTCLOCKRUN_ENET2_REF_CLK 0UL /* Clock consumers of ENET2_REF_CLK output : ENET2 */
#define BOARD_BOOTCLOCKRUN_ENET2_TX_CLK 0UL /* Clock consumers of ENET2_TX_CLK output : ENET2 */
#define BOARD_BOOTCLOCKRUN_ENET_125M_CLK 2400000UL /* Clock consumers of ENET_125M_CLK output : N/A */
#define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK 1200000UL /* Clock consumers of ENET_25M_REF_CLK output : ENET, ENET2 */
#define BOARD_BOOTCLOCKRUN_ENET_REF_CLK 0UL /* Clock consumers of ENET_REF_CLK output : ENET */
#define BOARD_BOOTCLOCKRUN_ENET_TX_CLK 0UL /* Clock consumers of ENET_TX_CLK output : ENET */
#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL /* Clock consumers of FLEXIO1_CLK_ROOT output : FLEXIO1 */
#define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT 30000000UL /* Clock consumers of FLEXIO2_CLK_ROOT output : FLEXIO2, FLEXIO3 */
#define BOARD_BOOTCLOCKRUN_FLEXSPI2_CLK_ROOT 130909090UL /* Clock consumers of FLEXSPI2_CLK_ROOT output : FLEXSPI2 */
#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 130909090UL /* Clock consumers of FLEXSPI_CLK_ROOT output : FLEXSPI */
#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 75000000UL /* Clock consumers of GPT1_ipg_clk_highfreq output : GPT1 */
#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 75000000UL /* Clock consumers of GPT2_ipg_clk_highfreq output : GPT2 */
#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 150000000UL /* Clock consumers of IPG_CLK_ROOT output : ADC1, ADC2, ADC_ETC, AOI1, AOI2, ARM, BEE, CAN1, CAN2, CAN3, CCM, CMP1, CMP2, CMP3, CMP4, CSI, CSU, DCDC, DCP, DMA0, DMAMUX, ENC1, ENC2, ENC3, ENC4, ENET, ENET2, EWM, FLEXIO1, FLEXIO2, FLEXIO3, FLEXRAM, FLEXSPI, FLEXSPI2, GPC, GPIO1, GPIO10, GPIO2, GPIO3, GPIO4, GPIO5, IOMUXC, KPP, LCDIF, LPI2C1, LPI2C2, LPI2C3, LPI2C4, LPSPI1, LPSPI2, LPSPI3, LPSPI4, LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8, NVIC, OCOTP, PMU, PWM1, PWM2, PWM3, PWM4, PXP, ROMC, RTWDOG, SAI1, SAI2, SAI3, SNVS, SPDIF, SRC, TEMPMON, TMR1, TMR2, TMR3, TMR4, TRNG, TSC, USB1, USB2, USDHC1, USDHC2, WDOG1, WDOG2, XBARA1, XBARB2, XBARB3 */
#define BOARD_BOOTCLOCKRUN_LCDIF_CLK_ROOT 67500000UL /* Clock consumers of LCDIF_CLK_ROOT output : LCDIF */
#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL /* Clock consumers of LPI2C_CLK_ROOT output : LPI2C1, LPI2C2, LPI2C3, LPI2C4 */
#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL /* Clock consumers of LPSPI_CLK_ROOT output : LPSPI1, LPSPI2, LPSPI3, LPSPI4 */
#define BOARD_BOOTCLOCKRUN_LVDS1_CLK 1200000000UL /* Clock consumers of LVDS1_CLK output : N/A */
#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL /* Clock consumers of MQS_MCLK output : N/A */
#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 75000000UL /* Clock consumers of PERCLK_CLK_ROOT output : GPT1, GPT2, PIT */
#define BOARD_BOOTCLOCKRUN_PLL7_MAIN_CLK 480000000UL /* Clock consumers of PLL7_MAIN_CLK output : N/A */
#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL /* Clock consumers of SAI1_CLK_ROOT output : N/A */
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL /* Clock consumers of SAI1_MCLK1 output : SAI1 */
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL /* Clock consumers of SAI1_MCLK2 output : SAI1 */
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL /* Clock consumers of SAI1_MCLK3 output : SAI1 */
#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 63529411UL /* Clock consumers of SAI2_CLK_ROOT output : N/A */
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 63529411UL /* Clock consumers of SAI2_MCLK1 output : SAI2 */
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL /* Clock consumers of SAI2_MCLK2 output : SAI2 */
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 30000000UL /* Clock consumers of SAI2_MCLK3 output : SAI2 */
#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL /* Clock consumers of SAI3_CLK_ROOT output : N/A */
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL /* Clock consumers of SAI3_MCLK1 output : SAI3 */
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL /* Clock consumers of SAI3_MCLK2 output : SAI3 */
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL /* Clock consumers of SAI3_MCLK3 output : SAI3 */
#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 75000000UL /* Clock consumers of SEMC_CLK_ROOT output : SEMC */
#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL /* Clock consumers of SPDIF0_CLK_ROOT output : SPDIF */
#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL /* Clock consumers of SPDIF0_EXTCLK_OUT output : SPDIF */
#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 132000000UL /* Clock consumers of TRACE_CLK_ROOT output : ARM */
#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL /* Clock consumers of UART_CLK_ROOT output : LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8 */
#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK 480000000UL /* Clock consumers of USBPHY1_CLK output : TEMPMON, USB1 */
#define BOARD_BOOTCLOCKRUN_USBPHY2_CLK 480000000UL /* Clock consumers of USBPHY2_CLK output : USB2 */
#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 198000000UL /* Clock consumers of USDHC1_CLK_ROOT output : USDHC1 */
#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 198000000UL /* Clock consumers of USDHC2_CLK_ROOT output : USDHC2 */
/*! @brief Arm PLL set for BOARD_BootClockRUN configuration.
*/
extern const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN;
/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration.
*/
extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN;
/*! @brief Usb2 PLL set for BOARD_BootClockRUN configuration.
*/
extern const clock_usb_pll_config_t usb2PllConfig_BOARD_BootClockRUN;
/*! @brief Sys PLL for BOARD_BootClockRUN configuration.
*/
extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN;
/*! @brief Video PLL set for BOARD_BootClockRUN configuration.
*/
extern const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN;
/*******************************************************************************
* API for BOARD_BootClockRUN configuration
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/
/*!
* @brief This function executes configuration of clocks.
*
*/
void BOARD_BootClockRUN(void);
#if defined(__cplusplus)
}
#endif /* __cplusplus*/
#endif /* _CLOCK_CONFIG_H_ */

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managed_components/espressif__tinyusb/hw/bsp/imxrt/boards/mimxrt1064_evk/board/pin_mux.c Normal file
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/***********************************************************************************************************************
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
**********************************************************************************************************************/
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!GlobalInfo
product: Pins v17.0
processor: MIMXRT1064xxxxA
package_id: MIMXRT1064DVL6A
mcu_data: ksdk2_0
processor_version: 24.12.10
board: MIMXRT1064-EVK
pin_labels:
- {pin_num: F14, pin_signal: GPIO_AD_B0_09, label: 'JTAG_TDI/J21[5]/ENET_RST/J22[5]', identifier: USER_LED}
- {pin_num: L6, pin_signal: WAKEUP, label: SD_PWREN, identifier: USER_BUTTON}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
#include "fsl_common.h"
#include "fsl_iomuxc.h"
#include "fsl_gpio.h"
#include "pin_mux.h"
/* FUNCTION ************************************************************************************************************
*
* Function Name : BOARD_InitBootPins
* Description : Calls initialization functions.
*
* END ****************************************************************************************************************/
void BOARD_InitBootPins(void) {
BOARD_InitPins();
BOARD_InitDEBUG_UARTPins();
}
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
BOARD_InitPins:
- options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'}
- pin_list:
- {pin_num: F14, peripheral: GPIO1, signal: 'gpio_io, 09', pin_signal: GPIO_AD_B0_09, direction: OUTPUT, pull_keeper_select: Keeper}
- {pin_num: L6, peripheral: GPIO5, signal: 'gpio_io, 00', pin_signal: WAKEUP, direction: INPUT}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
/* FUNCTION ************************************************************************************************************
*
* Function Name : BOARD_InitPins
* Description : Configures pin routing and optionally pin electrical features.
*
* END ****************************************************************************************************************/
void BOARD_InitPins(void) {
CLOCK_EnableClock(kCLOCK_Iomuxc);
CLOCK_EnableClock(kCLOCK_IomuxcSnvs);
/* GPIO configuration of USER_LED on GPIO_AD_B0_09 (pin F14) */
gpio_pin_config_t USER_LED_config = {
.direction = kGPIO_DigitalOutput,
.outputLogic = 0U,
.interruptMode = kGPIO_NoIntmode
};
/* Initialize GPIO functionality on GPIO_AD_B0_09 (pin F14) */
GPIO_PinInit(GPIO1, 9U, &USER_LED_config);
/* GPIO configuration of USER_BUTTON on WAKEUP (pin L6) */
gpio_pin_config_t USER_BUTTON_config = {
.direction = kGPIO_DigitalInput,
.outputLogic = 0U,
.interruptMode = kGPIO_NoIntmode
};
/* Initialize GPIO functionality on WAKEUP (pin L6) */
GPIO_PinInit(GPIO5, 0U, &USER_BUTTON_config);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, 0U);
IOMUXC_GPR->GPR26 = ((IOMUXC_GPR->GPR26 &
(~(BOARD_INITPINS_IOMUXC_GPR_GPR26_GPIO_MUX1_GPIO_SEL_MASK)))
| IOMUXC_GPR_GPR26_GPIO_MUX1_GPIO_SEL(0x00U)
);
IOMUXC_SetPinMux(IOMUXC_SNVS_WAKEUP_GPIO5_IO00, 0U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, 0x50A0U);
}
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
BOARD_InitDEBUG_UARTPins:
- options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'}
- pin_list:
- {pin_num: K14, peripheral: LPUART1, signal: TX, pin_signal: GPIO_AD_B0_12, software_input_on: Disable, hysteresis_enable: Disable, pull_up_down_config: Pull_Down_100K_Ohm,
pull_keeper_select: Keeper, pull_keeper_enable: Enable, open_drain: Disable, speed: MHZ_100, drive_strength: R0_6, slew_rate: Slow}
- {pin_num: L14, peripheral: LPUART1, signal: RX, pin_signal: GPIO_AD_B0_13, software_input_on: Disable, hysteresis_enable: Disable, pull_up_down_config: Pull_Down_100K_Ohm,
pull_keeper_select: Keeper, pull_keeper_enable: Enable, open_drain: Disable, speed: MHZ_100, drive_strength: R0_6, slew_rate: Slow}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
/* FUNCTION ************************************************************************************************************
*
* Function Name : BOARD_InitDEBUG_UARTPins
* Description : Configures pin routing and optionally pin electrical features.
*
* END ****************************************************************************************************************/
void BOARD_InitDEBUG_UARTPins(void) {
CLOCK_EnableClock(kCLOCK_Iomuxc);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_12_LPUART1_TX, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_13_LPUART1_RX, 0U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_12_LPUART1_TX, 0x10B0U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_13_LPUART1_RX, 0x10B0U);
}
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
BOARD_InitSDRAMPins:
- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'}
- pin_list:
- {pin_num: C2, peripheral: SEMC, signal: 'ADDR, 00', pin_signal: GPIO_EMC_09}
- {pin_num: G1, peripheral: SEMC, signal: 'ADDR, 01', pin_signal: GPIO_EMC_10}
- {pin_num: G3, peripheral: SEMC, signal: 'ADDR, 02', pin_signal: GPIO_EMC_11}
- {pin_num: H1, peripheral: SEMC, signal: 'ADDR, 03', pin_signal: GPIO_EMC_12}
- {pin_num: A6, peripheral: SEMC, signal: 'ADDR, 04', pin_signal: GPIO_EMC_13}
- {pin_num: B6, peripheral: SEMC, signal: 'ADDR, 05', pin_signal: GPIO_EMC_14}
- {pin_num: B1, peripheral: SEMC, signal: 'ADDR, 06', pin_signal: GPIO_EMC_15}
- {pin_num: A5, peripheral: SEMC, signal: 'ADDR, 07', pin_signal: GPIO_EMC_16}
- {pin_num: A4, peripheral: SEMC, signal: 'ADDR, 08', pin_signal: GPIO_EMC_17}
- {pin_num: B2, peripheral: SEMC, signal: 'ADDR, 09', pin_signal: GPIO_EMC_18}
- {pin_num: G2, peripheral: SEMC, signal: 'ADDR, 10', pin_signal: GPIO_EMC_23}
- {pin_num: B4, peripheral: SEMC, signal: 'ADDR, 11', pin_signal: GPIO_EMC_19}
- {pin_num: A3, peripheral: SEMC, signal: 'ADDR, 12', pin_signal: GPIO_EMC_20}
- {pin_num: C1, peripheral: SEMC, signal: 'BA, 0', pin_signal: GPIO_EMC_21}
- {pin_num: F1, peripheral: SEMC, signal: 'BA, 1', pin_signal: GPIO_EMC_22}
- {pin_num: D3, peripheral: SEMC, signal: semc_cas, pin_signal: GPIO_EMC_24}
- {pin_num: A2, peripheral: SEMC, signal: semc_cke, pin_signal: GPIO_EMC_27}
- {pin_num: B3, peripheral: SEMC, signal: semc_clk, pin_signal: GPIO_EMC_26}
- {pin_num: E3, peripheral: SEMC, signal: 'DATA, 00', pin_signal: GPIO_EMC_00}
- {pin_num: F3, peripheral: SEMC, signal: 'DATA, 01', pin_signal: GPIO_EMC_01}
- {pin_num: F4, peripheral: SEMC, signal: 'DATA, 02', pin_signal: GPIO_EMC_02}
- {pin_num: G4, peripheral: SEMC, signal: 'DATA, 03', pin_signal: GPIO_EMC_03}
- {pin_num: F2, peripheral: SEMC, signal: 'DATA, 04', pin_signal: GPIO_EMC_04}
- {pin_num: G5, peripheral: SEMC, signal: 'DATA, 05', pin_signal: GPIO_EMC_05}
- {pin_num: H5, peripheral: SEMC, signal: 'DATA, 06', pin_signal: GPIO_EMC_06}
- {pin_num: H4, peripheral: SEMC, signal: 'DATA, 07', pin_signal: GPIO_EMC_07}
- {pin_num: C6, peripheral: SEMC, signal: 'DATA, 08', pin_signal: GPIO_EMC_30}
- {pin_num: C5, peripheral: SEMC, signal: 'DATA, 09', pin_signal: GPIO_EMC_31}
- {pin_num: D5, peripheral: SEMC, signal: 'DATA, 10', pin_signal: GPIO_EMC_32}
- {pin_num: C4, peripheral: SEMC, signal: 'DATA, 11', pin_signal: GPIO_EMC_33}
- {pin_num: D4, peripheral: SEMC, signal: 'DATA, 12', pin_signal: GPIO_EMC_34}
- {pin_num: E5, peripheral: SEMC, signal: 'DATA, 13', pin_signal: GPIO_EMC_35}
- {pin_num: C3, peripheral: SEMC, signal: 'DATA, 14', pin_signal: GPIO_EMC_36}
- {pin_num: E4, peripheral: SEMC, signal: 'DATA, 15', pin_signal: GPIO_EMC_37}
- {pin_num: H3, peripheral: SEMC, signal: 'DM, 0', pin_signal: GPIO_EMC_08}
- {pin_num: D6, peripheral: SEMC, signal: 'DM, 1', pin_signal: GPIO_EMC_38}
- {pin_num: D2, peripheral: SEMC, signal: semc_ras, pin_signal: GPIO_EMC_25}
- {pin_num: D1, peripheral: SEMC, signal: semc_we, pin_signal: GPIO_EMC_28}
- {pin_num: E1, peripheral: SEMC, signal: 'CS, 0', pin_signal: GPIO_EMC_29}
- {pin_num: B7, peripheral: SEMC, signal: semc_dqs, pin_signal: GPIO_EMC_39}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
/* FUNCTION ************************************************************************************************************
*
* Function Name : BOARD_InitSDRAMPins
* Description : Configures pin routing and optionally pin electrical features.
*
* END ****************************************************************************************************************/
void BOARD_InitSDRAMPins(void) {
CLOCK_EnableClock(kCLOCK_Iomuxc);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_00_SEMC_DATA00, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_01_SEMC_DATA01, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_02_SEMC_DATA02, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_03_SEMC_DATA03, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_04_SEMC_DATA04, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_05_SEMC_DATA05, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_06_SEMC_DATA06, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_07_SEMC_DATA07, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_08_SEMC_DM00, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_09_SEMC_ADDR00, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_10_SEMC_ADDR01, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_11_SEMC_ADDR02, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_12_SEMC_ADDR03, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_13_SEMC_ADDR04, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_14_SEMC_ADDR05, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_15_SEMC_ADDR06, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_16_SEMC_ADDR07, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_17_SEMC_ADDR08, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_18_SEMC_ADDR09, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_19_SEMC_ADDR11, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_20_SEMC_ADDR12, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_21_SEMC_BA0, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_22_SEMC_BA1, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_23_SEMC_ADDR10, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_24_SEMC_CAS, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_25_SEMC_RAS, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_26_SEMC_CLK, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_27_SEMC_CKE, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_28_SEMC_WE, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_29_SEMC_CS0, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_30_SEMC_DATA08, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_31_SEMC_DATA09, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_32_SEMC_DATA10, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_33_SEMC_DATA11, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_34_SEMC_DATA12, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_35_SEMC_DATA13, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_36_SEMC_DATA14, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_37_SEMC_DATA15, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_38_SEMC_DM01, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_39_SEMC_DQS, 0U);
}
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
BOARD_InitCSIPins:
- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'}
- pin_list:
- {pin_num: H13, peripheral: CSI, signal: 'csi_data, 09', pin_signal: GPIO_AD_B1_08}
- {pin_num: M13, peripheral: CSI, signal: 'csi_data, 08', pin_signal: GPIO_AD_B1_09}
- {pin_num: L13, peripheral: CSI, signal: 'csi_data, 07', pin_signal: GPIO_AD_B1_10}
- {pin_num: J13, peripheral: CSI, signal: 'csi_data, 06', pin_signal: GPIO_AD_B1_11}
- {pin_num: H12, peripheral: CSI, signal: 'csi_data, 05', pin_signal: GPIO_AD_B1_12}
- {pin_num: H11, peripheral: CSI, signal: 'csi_data, 04', pin_signal: GPIO_AD_B1_13}
- {pin_num: J14, peripheral: CSI, signal: 'csi_data, 02', pin_signal: GPIO_AD_B1_15}
- {pin_num: G12, peripheral: CSI, signal: 'csi_data, 03', pin_signal: GPIO_AD_B1_14}
- {pin_num: L12, peripheral: CSI, signal: csi_pixclk, pin_signal: GPIO_AD_B1_04}
- {pin_num: K12, peripheral: CSI, signal: csi_mclk, pin_signal: GPIO_AD_B1_05}
- {pin_num: J12, peripheral: CSI, signal: csi_vsync, pin_signal: GPIO_AD_B1_06}
- {pin_num: K10, peripheral: CSI, signal: csi_hsync, pin_signal: GPIO_AD_B1_07}
- {pin_num: J11, peripheral: LPI2C1, signal: SCL, pin_signal: GPIO_AD_B1_00, identifier: CSI_I2C_SCL, software_input_on: Disable, hysteresis_enable: Disable, pull_up_down_config: Pull_Up_22K_Ohm,
pull_keeper_select: Keeper, pull_keeper_enable: Enable, open_drain: Enable, speed: MHZ_100, drive_strength: R0_6, slew_rate: Slow}
- {pin_num: K11, peripheral: LPI2C1, signal: SDA, pin_signal: GPIO_AD_B1_01, identifier: CSI_I2C_SDA, software_input_on: Disable, hysteresis_enable: Disable, pull_up_down_config: Pull_Up_22K_Ohm,
pull_keeper_select: Keeper, pull_keeper_enable: Enable, open_drain: Enable, speed: MHZ_100, drive_strength: R0_6, slew_rate: Slow}
- {pin_num: F11, peripheral: GPIO1, signal: 'gpio_io, 04', pin_signal: GPIO_AD_B0_04}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
/* FUNCTION ************************************************************************************************************
*
* Function Name : BOARD_InitCSIPins
* Description : Configures pin routing and optionally pin electrical features.
*
* END ****************************************************************************************************************/
void BOARD_InitCSIPins(void) {
CLOCK_EnableClock(kCLOCK_Iomuxc);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_04_GPIO1_IO04, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_04_CSI_PIXCLK, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_05_CSI_MCLK, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_06_CSI_VSYNC, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_07_CSI_HSYNC, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_08_CSI_DATA09, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_09_CSI_DATA08, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_10_CSI_DATA07, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_11_CSI_DATA06, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_12_CSI_DATA05, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_13_CSI_DATA04, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_14_CSI_DATA03, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_15_CSI_DATA02, 0U);
IOMUXC_GPR->GPR26 = ((IOMUXC_GPR->GPR26 &
(~(BOARD_INITCSIPINS_IOMUXC_GPR_GPR26_GPIO_MUX1_GPIO_SEL_MASK)))
| IOMUXC_GPR_GPR26_GPIO_MUX1_GPIO_SEL(0x00U)
);
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL, 0xD8B0U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA, 0xD8B0U);
}
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
BOARD_InitLCDPins:
- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'}
- pin_list:
- {pin_num: C8, peripheral: LCDIF, signal: 'lcdif_data, 00', pin_signal: GPIO_B0_04, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
- {pin_num: B8, peripheral: LCDIF, signal: 'lcdif_data, 01', pin_signal: GPIO_B0_05, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
- {pin_num: A8, peripheral: LCDIF, signal: 'lcdif_data, 02', pin_signal: GPIO_B0_06, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
- {pin_num: D7, peripheral: LCDIF, signal: lcdif_clk, pin_signal: GPIO_B0_00, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
- {pin_num: A9, peripheral: LCDIF, signal: 'lcdif_data, 03', pin_signal: GPIO_B0_07, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
- {pin_num: B9, peripheral: LCDIF, signal: 'lcdif_data, 04', pin_signal: GPIO_B0_08, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
- {pin_num: C9, peripheral: LCDIF, signal: 'lcdif_data, 05', pin_signal: GPIO_B0_09, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
- {pin_num: D9, peripheral: LCDIF, signal: 'lcdif_data, 06', pin_signal: GPIO_B0_10, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
- {pin_num: A10, peripheral: LCDIF, signal: 'lcdif_data, 07', pin_signal: GPIO_B0_11, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
- {pin_num: C10, peripheral: LCDIF, signal: 'lcdif_data, 08', pin_signal: GPIO_B0_12, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
- {pin_num: D10, peripheral: LCDIF, signal: 'lcdif_data, 09', pin_signal: GPIO_B0_13, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
- {pin_num: E10, peripheral: LCDIF, signal: 'lcdif_data, 10', pin_signal: GPIO_B0_14, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
- {pin_num: E11, peripheral: LCDIF, signal: 'lcdif_data, 11', pin_signal: GPIO_B0_15, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
- {pin_num: A11, peripheral: LCDIF, signal: 'lcdif_data, 12', pin_signal: GPIO_B1_00, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
- {pin_num: B11, peripheral: LCDIF, signal: 'lcdif_data, 13', pin_signal: GPIO_B1_01, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
- {pin_num: C11, peripheral: LCDIF, signal: 'lcdif_data, 14', pin_signal: GPIO_B1_02, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
- {pin_num: D11, peripheral: LCDIF, signal: 'lcdif_data, 15', pin_signal: GPIO_B1_03, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
- {pin_num: E7, peripheral: LCDIF, signal: lcdif_enable, pin_signal: GPIO_B0_01, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
- {pin_num: E8, peripheral: LCDIF, signal: lcdif_hsync, pin_signal: GPIO_B0_02, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
- {pin_num: D8, peripheral: LCDIF, signal: lcdif_vsync, pin_signal: GPIO_B0_03, hysteresis_enable: Enable, pull_up_down_config: Pull_Up_100K_Ohm, pull_keeper_select: Pull}
- {pin_num: B14, peripheral: GPIO2, signal: 'gpio_io, 31', pin_signal: GPIO_B1_15, slew_rate: Slow}
- {pin_num: M11, peripheral: GPIO1, signal: 'gpio_io, 02', pin_signal: GPIO_AD_B0_02}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
/* FUNCTION ************************************************************************************************************
*
* Function Name : BOARD_InitLCDPins
* Description : Configures pin routing and optionally pin electrical features.
*
* END ****************************************************************************************************************/
void BOARD_InitLCDPins(void) {
CLOCK_EnableClock(kCLOCK_Iomuxc);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_02_GPIO1_IO02, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_00_LCD_CLK, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_01_LCD_ENABLE, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_02_LCD_HSYNC, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_03_LCD_VSYNC, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_04_LCD_DATA00, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_05_LCD_DATA01, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_06_LCD_DATA02, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_07_LCD_DATA03, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_08_LCD_DATA04, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_09_LCD_DATA05, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_10_LCD_DATA06, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_11_LCD_DATA07, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_12_LCD_DATA08, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_13_LCD_DATA09, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_14_LCD_DATA10, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B0_15_LCD_DATA11, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_00_LCD_DATA12, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_01_LCD_DATA13, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_02_LCD_DATA14, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_03_LCD_DATA15, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_15_GPIO2_IO31, 0U);
IOMUXC_GPR->GPR26 = ((IOMUXC_GPR->GPR26 &
(~(BOARD_INITLCDPINS_IOMUXC_GPR_GPR26_GPIO_MUX1_GPIO_SEL_MASK)))
| IOMUXC_GPR_GPR26_GPIO_MUX1_GPIO_SEL(0x00U)
);
IOMUXC_GPR->GPR27 = ((IOMUXC_GPR->GPR27 &
(~(BOARD_INITLCDPINS_IOMUXC_GPR_GPR27_GPIO_MUX2_GPIO_SEL_MASK)))
| IOMUXC_GPR_GPR27_GPIO_MUX2_GPIO_SEL(0x00U)
);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_00_LCD_CLK, 0x01B0B0U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_01_LCD_ENABLE, 0x01B0B0U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_02_LCD_HSYNC, 0x01B0B0U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_03_LCD_VSYNC, 0x01B0B0U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_04_LCD_DATA00, 0x01B0B0U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_05_LCD_DATA01, 0x01B0B0U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_06_LCD_DATA02, 0x01B0B0U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_07_LCD_DATA03, 0x01B0B0U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_08_LCD_DATA04, 0x01B0B0U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_09_LCD_DATA05, 0x01B0B0U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_10_LCD_DATA06, 0x01B0B0U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_11_LCD_DATA07, 0x01B0B0U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_12_LCD_DATA08, 0x01B0B0U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_13_LCD_DATA09, 0x01B0B0U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_14_LCD_DATA10, 0x01B0B0U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_15_LCD_DATA11, 0x01B0B0U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_00_LCD_DATA12, 0x01B0B0U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_01_LCD_DATA13, 0x01B0B0U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_02_LCD_DATA14, 0x01B0B0U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_03_LCD_DATA15, 0x01B0B0U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_15_GPIO2_IO31, 0x10B0U);
}
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
BOARD_InitCANPins:
- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'}
- pin_list:
- {pin_num: H14, peripheral: CAN2, signal: TX, pin_signal: GPIO_AD_B0_14}
- {pin_num: L10, peripheral: CAN2, signal: RX, pin_signal: GPIO_AD_B0_15}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
/* FUNCTION ************************************************************************************************************
*
* Function Name : BOARD_InitCANPins
* Description : Configures pin routing and optionally pin electrical features.
*
* END ****************************************************************************************************************/
void BOARD_InitCANPins(void) {
CLOCK_EnableClock(kCLOCK_Iomuxc);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_14_FLEXCAN2_TX, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_15_FLEXCAN2_RX, 0U);
}
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
BOARD_InitENETPins:
- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'}
- pin_list:
- {pin_num: A7, peripheral: ENET, signal: enet_mdc, pin_signal: GPIO_EMC_40}
- {pin_num: C7, peripheral: ENET, signal: enet_mdio, pin_signal: GPIO_EMC_41}
- {pin_num: B13, peripheral: ENET, signal: enet_ref_clk, pin_signal: GPIO_B1_10}
- {pin_num: E12, peripheral: ENET, signal: 'enet_rx_data, 0', pin_signal: GPIO_B1_04}
- {pin_num: D12, peripheral: ENET, signal: 'enet_rx_data, 1', pin_signal: GPIO_B1_05}
- {pin_num: C12, peripheral: ENET, signal: enet_rx_en, pin_signal: GPIO_B1_06}
- {pin_num: C13, peripheral: ENET, signal: enet_rx_er, pin_signal: GPIO_B1_11}
- {pin_num: B12, peripheral: ENET, signal: 'enet_tx_data, 0', pin_signal: GPIO_B1_07}
- {pin_num: A12, peripheral: ENET, signal: 'enet_tx_data, 1', pin_signal: GPIO_B1_08}
- {pin_num: A13, peripheral: ENET, signal: enet_tx_en, pin_signal: GPIO_B1_09}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
/* FUNCTION ************************************************************************************************************
*
* Function Name : BOARD_InitENETPins
* Description : Configures pin routing and optionally pin electrical features.
*
* END ****************************************************************************************************************/
void BOARD_InitENETPins(void) {
CLOCK_EnableClock(kCLOCK_Iomuxc);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_04_ENET_RX_DATA00, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_05_ENET_RX_DATA01, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_06_ENET_RX_EN, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_07_ENET_TX_DATA00, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_08_ENET_TX_DATA01, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_09_ENET_TX_EN, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_10_ENET_REF_CLK, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_11_ENET_RX_ER, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_40_ENET_MDC, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_41_ENET_MDIO, 0U);
}
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
BOARD_InitUSDHCPins:
- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'}
- pin_list:
- {pin_num: J2, peripheral: USDHC1, signal: 'usdhc_data, 3', pin_signal: GPIO_SD_B0_05}
- {pin_num: H2, peripheral: USDHC1, signal: 'usdhc_data, 2', pin_signal: GPIO_SD_B0_04}
- {pin_num: K1, peripheral: USDHC1, signal: 'usdhc_data, 1', pin_signal: GPIO_SD_B0_03}
- {pin_num: J1, peripheral: USDHC1, signal: 'usdhc_data, 0', pin_signal: GPIO_SD_B0_02}
- {pin_num: J4, peripheral: USDHC1, signal: usdhc_cmd, pin_signal: GPIO_SD_B0_00}
- {pin_num: J3, peripheral: USDHC1, signal: usdhc_clk, pin_signal: GPIO_SD_B0_01}
- {pin_num: C14, peripheral: USDHC1, signal: usdhc_vselect, pin_signal: GPIO_B1_14}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
/* FUNCTION ************************************************************************************************************
*
* Function Name : BOARD_InitUSDHCPins
* Description : Configures pin routing and optionally pin electrical features.
*
* END ****************************************************************************************************************/
void BOARD_InitUSDHCPins(void) {
CLOCK_EnableClock(kCLOCK_Iomuxc);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_14_USDHC1_VSELECT, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_00_USDHC1_CMD, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_01_USDHC1_CLK, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3, 0U);
}
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
BOARD_InitQSPIPins:
- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'}
- pin_list:
- {pin_num: P3, peripheral: FLEXSPI, signal: FLEXSPI_A_DATA0, pin_signal: GPIO_SD_B1_08}
- {pin_num: N4, peripheral: FLEXSPI, signal: FLEXSPI_A_DATA1, pin_signal: GPIO_SD_B1_09}
- {pin_num: P4, peripheral: FLEXSPI, signal: FLEXSPI_A_DATA2, pin_signal: GPIO_SD_B1_10}
- {pin_num: P5, peripheral: FLEXSPI, signal: FLEXSPI_A_DATA3, pin_signal: GPIO_SD_B1_11}
- {pin_num: L4, peripheral: FLEXSPI, signal: FLEXSPI_A_SCLK, pin_signal: GPIO_SD_B1_07}
- {pin_num: L3, peripheral: FLEXSPI, signal: FLEXSPI_A_SS0_B, pin_signal: GPIO_SD_B1_06}
- {pin_num: N3, peripheral: FLEXSPI, signal: FLEXSPI_A_DQS, pin_signal: GPIO_SD_B1_05}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
/* FUNCTION ************************************************************************************************************
*
* Function Name : BOARD_InitQSPIPins
* Description : Configures pin routing and optionally pin electrical features.
*
* END ****************************************************************************************************************/
void BOARD_InitQSPIPins(void) {
CLOCK_EnableClock(kCLOCK_Iomuxc);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_05_FLEXSPIA_DQS, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_06_FLEXSPIA_SS0_B, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_07_FLEXSPIA_SCLK, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_08_FLEXSPIA_DATA00, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_09_FLEXSPIA_DATA01, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_10_FLEXSPIA_DATA02, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_11_FLEXSPIA_DATA03, 0U);
}
/***********************************************************************************************************************
* EOF
**********************************************************************************************************************/

745
managed_components/espressif__tinyusb/hw/bsp/imxrt/boards/mimxrt1064_evk/board/pin_mux.h Normal file
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/***********************************************************************************************************************
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
**********************************************************************************************************************/
#ifndef _PIN_MUX_H_
#define _PIN_MUX_H_
/***********************************************************************************************************************
* Definitions
**********************************************************************************************************************/
/*! @brief Direction type */
typedef enum _pin_mux_direction
{
kPIN_MUX_DirectionInput = 0U, /* Input direction */
kPIN_MUX_DirectionOutput = 1U, /* Output direction */
kPIN_MUX_DirectionInputOrOutput = 2U /* Input or output direction */
} pin_mux_direction_t;
/*!
* @addtogroup pin_mux
* @{
*/
/***********************************************************************************************************************
* API
**********************************************************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif
/*!
* @brief Calls initialization functions.
*
*/
void BOARD_InitBootPins(void);
#define BOARD_INITPINS_IOMUXC_GPR_GPR26_GPIO_MUX1_GPIO_SEL_MASK 0x0200U /*!< GPIO1 and GPIO6 share same IO MUX function, GPIO_MUX1 selects one GPIO function: affected bits mask */
/* GPIO_AD_B0_09 (coord F14), JTAG_TDI/J21[5]/ENET_RST/J22[5] */
/* Routed pin properties */
#define BOARD_INITPINS_USER_LED_PERIPHERAL GPIO1 /*!< Peripheral name */
#define BOARD_INITPINS_USER_LED_SIGNAL gpio_io /*!< Signal name */
#define BOARD_INITPINS_USER_LED_CHANNEL 9U /*!< Signal channel */
/* Symbols to be used with GPIO driver */
#define BOARD_INITPINS_USER_LED_GPIO GPIO1 /*!< GPIO peripheral base pointer */
#define BOARD_INITPINS_USER_LED_INIT_GPIO_VALUE 0U /*!< GPIO output initial state */
#define BOARD_INITPINS_USER_LED_GPIO_PIN 9U /*!< GPIO pin number */
#define BOARD_INITPINS_USER_LED_GPIO_PIN_MASK (1U << 9U) /*!< GPIO pin mask */
#define BOARD_INITPINS_USER_LED_PORT GPIO1 /*!< PORT peripheral base pointer */
#define BOARD_INITPINS_USER_LED_PIN 9U /*!< PORT pin number */
#define BOARD_INITPINS_USER_LED_PIN_MASK (1U << 9U) /*!< PORT pin mask */
/* WAKEUP (coord L6), SD_PWREN */
/* Routed pin properties */
#define BOARD_INITPINS_USER_BUTTON_PERIPHERAL GPIO5 /*!< Peripheral name */
#define BOARD_INITPINS_USER_BUTTON_SIGNAL gpio_io /*!< Signal name */
#define BOARD_INITPINS_USER_BUTTON_CHANNEL 0U /*!< Signal channel */
/* Symbols to be used with GPIO driver */
#define BOARD_INITPINS_USER_BUTTON_GPIO GPIO5 /*!< GPIO peripheral base pointer */
#define BOARD_INITPINS_USER_BUTTON_GPIO_PIN 0U /*!< GPIO pin number */
#define BOARD_INITPINS_USER_BUTTON_GPIO_PIN_MASK (1U << 0U) /*!< GPIO pin mask */
#define BOARD_INITPINS_USER_BUTTON_PORT GPIO5 /*!< PORT peripheral base pointer */
#define BOARD_INITPINS_USER_BUTTON_PIN 0U /*!< PORT pin number */
#define BOARD_INITPINS_USER_BUTTON_PIN_MASK (1U << 0U) /*!< PORT pin mask */
/*!
* @brief Configures pin routing and optionally pin electrical features.
*
*/
void BOARD_InitPins(void);
/* GPIO_AD_B0_12 (coord K14), UART1_TXD */
/* Routed pin properties */
#define BOARD_INITDEBUG_UARTPINS_UART1_TXD_PERIPHERAL LPUART1 /*!< Peripheral name */
#define BOARD_INITDEBUG_UARTPINS_UART1_TXD_SIGNAL TX /*!< Signal name */
/* GPIO_AD_B0_13 (coord L14), UART1_RXD */
/* Routed pin properties */
#define BOARD_INITDEBUG_UARTPINS_UART1_RXD_PERIPHERAL LPUART1 /*!< Peripheral name */
#define BOARD_INITDEBUG_UARTPINS_UART1_RXD_SIGNAL RX /*!< Signal name */
/*!
* @brief Configures pin routing and optionally pin electrical features.
*
*/
void BOARD_InitDEBUG_UARTPins(void);
/* GPIO_EMC_09 (coord C2), SEMC_A0 */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_A0_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_A0_SIGNAL ADDR /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_A0_CHANNEL 0U /*!< Signal channel */
/* GPIO_EMC_10 (coord G1), SEMC_A1 */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_A1_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_A1_SIGNAL ADDR /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_A1_CHANNEL 1U /*!< Signal channel */
/* GPIO_EMC_11 (coord G3), SEMC_A2 */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_A2_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_A2_SIGNAL ADDR /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_A2_CHANNEL 2U /*!< Signal channel */
/* GPIO_EMC_12 (coord H1), SEMC_A3 */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_A3_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_A3_SIGNAL ADDR /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_A3_CHANNEL 3U /*!< Signal channel */
/* GPIO_EMC_13 (coord A6), SEMC_A4 */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_A4_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_A4_SIGNAL ADDR /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_A4_CHANNEL 4U /*!< Signal channel */
/* GPIO_EMC_14 (coord B6), SEMC_A5 */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_A5_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_A5_SIGNAL ADDR /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_A5_CHANNEL 5U /*!< Signal channel */
/* GPIO_EMC_15 (coord B1), SEMC_A6 */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_A6_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_A6_SIGNAL ADDR /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_A6_CHANNEL 6U /*!< Signal channel */
/* GPIO_EMC_16 (coord A5), SEMC_A7 */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_A7_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_A7_SIGNAL ADDR /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_A7_CHANNEL 7U /*!< Signal channel */
/* GPIO_EMC_17 (coord A4), SEMC_A8 */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_A8_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_A8_SIGNAL ADDR /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_A8_CHANNEL 8U /*!< Signal channel */
/* GPIO_EMC_18 (coord B2), SEMC_A9 */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_A9_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_A9_SIGNAL ADDR /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_A9_CHANNEL 9U /*!< Signal channel */
/* GPIO_EMC_23 (coord G2), SEMC_A10 */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_A10_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_A10_SIGNAL ADDR /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_A10_CHANNEL 10U /*!< Signal channel */
/* GPIO_EMC_19 (coord B4), SEMC_A11 */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_A11_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_A11_SIGNAL ADDR /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_A11_CHANNEL 11U /*!< Signal channel */
/* GPIO_EMC_20 (coord A3), SEMC_A12 */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_A12_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_A12_SIGNAL ADDR /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_A12_CHANNEL 12U /*!< Signal channel */
/* GPIO_EMC_21 (coord C1), SEMC_BA0 */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_BA0_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_BA0_SIGNAL BA /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_BA0_CHANNEL 0U /*!< Signal channel */
/* GPIO_EMC_22 (coord F1), SEMC_BA1 */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_BA1_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_BA1_SIGNAL BA /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_BA1_CHANNEL 1U /*!< Signal channel */
/* GPIO_EMC_24 (coord D3), SEMC_CAS */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_CAS_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_CAS_SIGNAL semc_cas /*!< Signal name */
/* GPIO_EMC_27 (coord A2), SEMC_CKE */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_CKE_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_CKE_SIGNAL semc_cke /*!< Signal name */
/* GPIO_EMC_26 (coord B3), SEMC_CLK */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_CLK_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_CLK_SIGNAL semc_clk /*!< Signal name */
/* GPIO_EMC_00 (coord E3), SEMC_D0 */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_D0_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_D0_SIGNAL DATA /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_D0_CHANNEL 0U /*!< Signal channel */
/* GPIO_EMC_01 (coord F3), SEMC_D1 */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_D1_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_D1_SIGNAL DATA /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_D1_CHANNEL 1U /*!< Signal channel */
/* GPIO_EMC_02 (coord F4), SEMC_D2 */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_D2_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_D2_SIGNAL DATA /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_D2_CHANNEL 2U /*!< Signal channel */
/* GPIO_EMC_03 (coord G4), SEMC_D3 */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_D3_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_D3_SIGNAL DATA /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_D3_CHANNEL 3U /*!< Signal channel */
/* GPIO_EMC_04 (coord F2), SEMC_D4 */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_D4_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_D4_SIGNAL DATA /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_D4_CHANNEL 4U /*!< Signal channel */
/* GPIO_EMC_05 (coord G5), SEMC_D5 */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_D5_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_D5_SIGNAL DATA /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_D5_CHANNEL 5U /*!< Signal channel */
/* GPIO_EMC_06 (coord H5), SEMC_D6 */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_D6_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_D6_SIGNAL DATA /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_D6_CHANNEL 6U /*!< Signal channel */
/* GPIO_EMC_07 (coord H4), SEMC_D7 */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_D7_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_D7_SIGNAL DATA /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_D7_CHANNEL 7U /*!< Signal channel */
/* GPIO_EMC_30 (coord C6), SEMC_D8 */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_D8_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_D8_SIGNAL DATA /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_D8_CHANNEL 8U /*!< Signal channel */
/* GPIO_EMC_31 (coord C5), SEMC_D9 */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_D9_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_D9_SIGNAL DATA /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_D9_CHANNEL 9U /*!< Signal channel */
/* GPIO_EMC_32 (coord D5), SEMC_D10 */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_D10_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_D10_SIGNAL DATA /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_D10_CHANNEL 10U /*!< Signal channel */
/* GPIO_EMC_33 (coord C4), SEMC_D11 */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_D11_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_D11_SIGNAL DATA /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_D11_CHANNEL 11U /*!< Signal channel */
/* GPIO_EMC_34 (coord D4), SEMC_D12 */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_D12_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_D12_SIGNAL DATA /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_D12_CHANNEL 12U /*!< Signal channel */
/* GPIO_EMC_35 (coord E5), SEMC_D13 */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_D13_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_D13_SIGNAL DATA /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_D13_CHANNEL 13U /*!< Signal channel */
/* GPIO_EMC_36 (coord C3), SEMC_D14 */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_D14_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_D14_SIGNAL DATA /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_D14_CHANNEL 14U /*!< Signal channel */
/* GPIO_EMC_37 (coord E4), SEMC_D15 */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_D15_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_D15_SIGNAL DATA /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_D15_CHANNEL 15U /*!< Signal channel */
/* GPIO_EMC_08 (coord H3), SEMC_DM0 */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_DM0_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_DM0_SIGNAL DM /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_DM0_CHANNEL 0U /*!< Signal channel */
/* GPIO_EMC_38 (coord D6), SEMC_DM1 */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_DM1_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_DM1_SIGNAL DM /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_DM1_CHANNEL 1U /*!< Signal channel */
/* GPIO_EMC_25 (coord D2), SEMC_RAS */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_RAS_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_RAS_SIGNAL semc_ras /*!< Signal name */
/* GPIO_EMC_28 (coord D1), SEMC_WE */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_WE_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_WE_SIGNAL semc_we /*!< Signal name */
/* GPIO_EMC_29 (coord E1), SEMC_CS0 */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_CS0_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_CS0_SIGNAL CS /*!< Signal name */
#define BOARD_INITSDRAMPINS_SEMC_CS0_CHANNEL 0U /*!< Signal channel */
/* GPIO_EMC_39 (coord B7), SEMC_DQS */
/* Routed pin properties */
#define BOARD_INITSDRAMPINS_SEMC_DQS_PERIPHERAL SEMC /*!< Peripheral name */
#define BOARD_INITSDRAMPINS_SEMC_DQS_SIGNAL semc_dqs /*!< Signal name */
/*!
* @brief Configures pin routing and optionally pin electrical features.
*
*/
void BOARD_InitSDRAMPins(void);
#define BOARD_INITCSIPINS_IOMUXC_GPR_GPR26_GPIO_MUX1_GPIO_SEL_MASK 0x10U /*!< GPIO1 and GPIO6 share same IO MUX function, GPIO_MUX1 selects one GPIO function: affected bits mask */
/* GPIO_AD_B1_08 (coord H13), AUD_INT/CSI_D9//J35[13]/J22[4] */
/* Routed pin properties */
#define BOARD_INITCSIPINS_CSI_D9_PERIPHERAL CSI /*!< Peripheral name */
#define BOARD_INITCSIPINS_CSI_D9_SIGNAL csi_data /*!< Signal name */
#define BOARD_INITCSIPINS_CSI_D9_CHANNEL 9U /*!< Signal channel */
/* GPIO_AD_B1_09 (coord M13), SAI1_MCLK/CSI_D8/J35[11] */
/* Routed pin properties */
#define BOARD_INITCSIPINS_CSI_D8_PERIPHERAL CSI /*!< Peripheral name */
#define BOARD_INITCSIPINS_CSI_D8_SIGNAL csi_data /*!< Signal name */
#define BOARD_INITCSIPINS_CSI_D8_CHANNEL 8U /*!< Signal channel */
/* GPIO_AD_B1_10 (coord L13), SAI1_RX_SYNC/CSI_D7/J35[9]/J23[1] */
/* Routed pin properties */
#define BOARD_INITCSIPINS_CSI_D7_PERIPHERAL CSI /*!< Peripheral name */
#define BOARD_INITCSIPINS_CSI_D7_SIGNAL csi_data /*!< Signal name */
#define BOARD_INITCSIPINS_CSI_D7_CHANNEL 7U /*!< Signal channel */
/* GPIO_AD_B1_11 (coord J13), SAI1_RX_BCLK/CSI_D6/J35[7]/J23[2] */
/* Routed pin properties */
#define BOARD_INITCSIPINS_CSI_D6_PERIPHERAL CSI /*!< Peripheral name */
#define BOARD_INITCSIPINS_CSI_D6_SIGNAL csi_data /*!< Signal name */
#define BOARD_INITCSIPINS_CSI_D6_CHANNEL 6U /*!< Signal channel */
/* GPIO_AD_B1_12 (coord H12), SAI1_RXD/CSI_D5/J35[5]/U13[16] */
/* Routed pin properties */
#define BOARD_INITCSIPINS_CSI_D5_PERIPHERAL CSI /*!< Peripheral name */
#define BOARD_INITCSIPINS_CSI_D5_SIGNAL csi_data /*!< Signal name */
#define BOARD_INITCSIPINS_CSI_D5_CHANNEL 5U /*!< Signal channel */
/* GPIO_AD_B1_13 (coord H11), SAI1_TXD/CSI_D4/J35[3]/U13[14] */
/* Routed pin properties */
#define BOARD_INITCSIPINS_CSI_D4_PERIPHERAL CSI /*!< Peripheral name */
#define BOARD_INITCSIPINS_CSI_D4_SIGNAL csi_data /*!< Signal name */
#define BOARD_INITCSIPINS_CSI_D4_CHANNEL 4U /*!< Signal channel */
/* GPIO_AD_B1_15 (coord J14), SAI1_TX_SYNC/CSI_D2/J35[6]/U13[13] */
/* Routed pin properties */
#define BOARD_INITCSIPINS_CSI_D2_PERIPHERAL CSI /*!< Peripheral name */
#define BOARD_INITCSIPINS_CSI_D2_SIGNAL csi_data /*!< Signal name */
#define BOARD_INITCSIPINS_CSI_D2_CHANNEL 2U /*!< Signal channel */
/* GPIO_AD_B1_14 (coord G12), SAI1_TX_BCLK/CSI_D3/J35[4]/U13[12] */
/* Routed pin properties */
#define BOARD_INITCSIPINS_CSI_D3_PERIPHERAL CSI /*!< Peripheral name */
#define BOARD_INITCSIPINS_CSI_D3_SIGNAL csi_data /*!< Signal name */
#define BOARD_INITCSIPINS_CSI_D3_CHANNEL 3U /*!< Signal channel */
/* GPIO_AD_B1_04 (coord L12), CSI_PIXCLK/J35[8]/J23[3] */
/* Routed pin properties */
#define BOARD_INITCSIPINS_CSI_PIXCLK_PERIPHERAL CSI /*!< Peripheral name */
#define BOARD_INITCSIPINS_CSI_PIXCLK_SIGNAL csi_pixclk /*!< Signal name */
/* GPIO_AD_B1_05 (coord K12), CSI_MCLK/J35[12]/J23[4] */
/* Routed pin properties */
#define BOARD_INITCSIPINS_CSI_MCLK_PERIPHERAL CSI /*!< Peripheral name */
#define BOARD_INITCSIPINS_CSI_MCLK_SIGNAL csi_mclk /*!< Signal name */
/* GPIO_AD_B1_06 (coord J12), CSI_VSYNC/J35[18]/J22[2]/UART_TX */
/* Routed pin properties */
#define BOARD_INITCSIPINS_CSI_VSYNC_PERIPHERAL CSI /*!< Peripheral name */
#define BOARD_INITCSIPINS_CSI_VSYNC_SIGNAL csi_vsync /*!< Signal name */
/* GPIO_AD_B1_07 (coord K10), CSI_HSYNC/J35[16]/J22[1]/UART_RX */
/* Routed pin properties */
#define BOARD_INITCSIPINS_CSI_HSYNC_PERIPHERAL CSI /*!< Peripheral name */
#define BOARD_INITCSIPINS_CSI_HSYNC_SIGNAL csi_hsync /*!< Signal name */
/* GPIO_AD_B1_00 (coord J11), I2C1_SCL/CSI_I2C_SCL/J35[20]/J23[6]/U13[17]/U32[4] */
/* Routed pin properties */
#define BOARD_INITCSIPINS_CSI_I2C_SCL_PERIPHERAL LPI2C1 /*!< Peripheral name */
#define BOARD_INITCSIPINS_CSI_I2C_SCL_SIGNAL SCL /*!< Signal name */
/* GPIO_AD_B1_01 (coord K11), I2C1_SDA/CSI_I2C_SDA/J35[22]/J23[5]/U13[18]/U32[6] */
/* Routed pin properties */
#define BOARD_INITCSIPINS_CSI_I2C_SDA_PERIPHERAL LPI2C1 /*!< Peripheral name */
#define BOARD_INITCSIPINS_CSI_I2C_SDA_SIGNAL SDA /*!< Signal name */
/* GPIO_AD_B0_04 (coord F11), CSI_PWDN/J35[17]/BOOT_MODE[0] */
/* Routed pin properties */
#define BOARD_INITCSIPINS_CSI_PWDN_PERIPHERAL GPIO1 /*!< Peripheral name */
#define BOARD_INITCSIPINS_CSI_PWDN_SIGNAL gpio_io /*!< Signal name */
#define BOARD_INITCSIPINS_CSI_PWDN_CHANNEL 4U /*!< Signal channel */
/* Symbols to be used with GPIO driver */
#define BOARD_INITCSIPINS_CSI_PWDN_GPIO GPIO1 /*!< GPIO peripheral base pointer */
#define BOARD_INITCSIPINS_CSI_PWDN_GPIO_PIN 4U /*!< GPIO pin number */
#define BOARD_INITCSIPINS_CSI_PWDN_GPIO_PIN_MASK (1U << 4U) /*!< GPIO pin mask */
#define BOARD_INITCSIPINS_CSI_PWDN_PORT GPIO1 /*!< PORT peripheral base pointer */
#define BOARD_INITCSIPINS_CSI_PWDN_PIN 4U /*!< PORT pin number */
#define BOARD_INITCSIPINS_CSI_PWDN_PIN_MASK (1U << 4U) /*!< PORT pin mask */
/*!
* @brief Configures pin routing and optionally pin electrical features.
*
*/
void BOARD_InitCSIPins(void);
#define BOARD_INITLCDPINS_IOMUXC_GPR_GPR26_GPIO_MUX1_GPIO_SEL_MASK 0x04U /*!< GPIO1 and GPIO6 share same IO MUX function, GPIO_MUX1 selects one GPIO function: affected bits mask */
#define BOARD_INITLCDPINS_IOMUXC_GPR_GPR27_GPIO_MUX2_GPIO_SEL_MASK 0x80000000U /*!< GPIO2 and GPIO7 share same IO MUX function, GPIO_MUX2 selects one GPIO function: affected bits mask */
/* GPIO_B0_04 (coord C8), LCDIF_D0/BT_CFG[0] */
/* Routed pin properties */
#define BOARD_INITLCDPINS_LCDIF_D0_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITLCDPINS_LCDIF_D0_SIGNAL lcdif_data /*!< Signal name */
#define BOARD_INITLCDPINS_LCDIF_D0_CHANNEL 0U /*!< Signal channel */
/* GPIO_B0_05 (coord B8), LCDIF_D1/BT_CFG[1] */
/* Routed pin properties */
#define BOARD_INITLCDPINS_LCDIF_D1_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITLCDPINS_LCDIF_D1_SIGNAL lcdif_data /*!< Signal name */
#define BOARD_INITLCDPINS_LCDIF_D1_CHANNEL 1U /*!< Signal channel */
/* GPIO_B0_06 (coord A8), LCDIF_D2/BT_CFG[2] */
/* Routed pin properties */
#define BOARD_INITLCDPINS_LCDIF_D2_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITLCDPINS_LCDIF_D2_SIGNAL lcdif_data /*!< Signal name */
#define BOARD_INITLCDPINS_LCDIF_D2_CHANNEL 2U /*!< Signal channel */
/* GPIO_B0_00 (coord D7), LCDIF_CLK */
/* Routed pin properties */
#define BOARD_INITLCDPINS_LCDIF_CLK_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITLCDPINS_LCDIF_CLK_SIGNAL lcdif_clk /*!< Signal name */
/* GPIO_B0_07 (coord A9), LCDIF_D3/BT_CFG[3] */
/* Routed pin properties */
#define BOARD_INITLCDPINS_LCDIF_D3_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITLCDPINS_LCDIF_D3_SIGNAL lcdif_data /*!< Signal name */
#define BOARD_INITLCDPINS_LCDIF_D3_CHANNEL 3U /*!< Signal channel */
/* GPIO_B0_08 (coord B9), LCDIF_D4/BT_CFG[4] */
/* Routed pin properties */
#define BOARD_INITLCDPINS_LCDIF_D4_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITLCDPINS_LCDIF_D4_SIGNAL lcdif_data /*!< Signal name */
#define BOARD_INITLCDPINS_LCDIF_D4_CHANNEL 4U /*!< Signal channel */
/* GPIO_B0_09 (coord C9), LCDIF_D5/BT_CFG[5] */
/* Routed pin properties */
#define BOARD_INITLCDPINS_LCDIF_D5_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITLCDPINS_LCDIF_D5_SIGNAL lcdif_data /*!< Signal name */
#define BOARD_INITLCDPINS_LCDIF_D5_CHANNEL 5U /*!< Signal channel */
/* GPIO_B0_10 (coord D9), LCDIF_D6/BT_CFG[6] */
/* Routed pin properties */
#define BOARD_INITLCDPINS_LCDIF_D6_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITLCDPINS_LCDIF_D6_SIGNAL lcdif_data /*!< Signal name */
#define BOARD_INITLCDPINS_LCDIF_D6_CHANNEL 6U /*!< Signal channel */
/* GPIO_B0_11 (coord A10), LCDIF_D7/BT_CFG[7] */
/* Routed pin properties */
#define BOARD_INITLCDPINS_LCDIF_D7_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITLCDPINS_LCDIF_D7_SIGNAL lcdif_data /*!< Signal name */
#define BOARD_INITLCDPINS_LCDIF_D7_CHANNEL 7U /*!< Signal channel */
/* GPIO_B0_12 (coord C10), LCDIF_D8/BT_CFG[8] */
/* Routed pin properties */
#define BOARD_INITLCDPINS_LCDIF_D8_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITLCDPINS_LCDIF_D8_SIGNAL lcdif_data /*!< Signal name */
#define BOARD_INITLCDPINS_LCDIF_D8_CHANNEL 8U /*!< Signal channel */
/* GPIO_B0_13 (coord D10), LCDIF_D9/BT_CFG[9] */
/* Routed pin properties */
#define BOARD_INITLCDPINS_LCDIF_D9_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITLCDPINS_LCDIF_D9_SIGNAL lcdif_data /*!< Signal name */
#define BOARD_INITLCDPINS_LCDIF_D9_CHANNEL 9U /*!< Signal channel */
/* GPIO_B0_14 (coord E10), LCDIF_D10/BT_CFG[10] */
/* Routed pin properties */
#define BOARD_INITLCDPINS_LCDIF_D10_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITLCDPINS_LCDIF_D10_SIGNAL lcdif_data /*!< Signal name */
#define BOARD_INITLCDPINS_LCDIF_D10_CHANNEL 10U /*!< Signal channel */
/* GPIO_B0_15 (coord E11), LCDIF_D11/BT_CFG[11] */
/* Routed pin properties */
#define BOARD_INITLCDPINS_LCDIF_D11_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITLCDPINS_LCDIF_D11_SIGNAL lcdif_data /*!< Signal name */
#define BOARD_INITLCDPINS_LCDIF_D11_CHANNEL 11U /*!< Signal channel */
/* GPIO_B1_00 (coord A11), LCDIF_D12 */
/* Routed pin properties */
#define BOARD_INITLCDPINS_LCDIF_D12_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITLCDPINS_LCDIF_D12_SIGNAL lcdif_data /*!< Signal name */
#define BOARD_INITLCDPINS_LCDIF_D12_CHANNEL 12U /*!< Signal channel */
/* GPIO_B1_01 (coord B11), LCDIF_D13 */
/* Routed pin properties */
#define BOARD_INITLCDPINS_LCDIF_D13_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITLCDPINS_LCDIF_D13_SIGNAL lcdif_data /*!< Signal name */
#define BOARD_INITLCDPINS_LCDIF_D13_CHANNEL 13U /*!< Signal channel */
/* GPIO_B1_02 (coord C11), LCDIF_D14 */
/* Routed pin properties */
#define BOARD_INITLCDPINS_LCDIF_D14_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITLCDPINS_LCDIF_D14_SIGNAL lcdif_data /*!< Signal name */
#define BOARD_INITLCDPINS_LCDIF_D14_CHANNEL 14U /*!< Signal channel */
/* GPIO_B1_03 (coord D11), LCDIF_D15 */
/* Routed pin properties */
#define BOARD_INITLCDPINS_LCDIF_D15_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITLCDPINS_LCDIF_D15_SIGNAL lcdif_data /*!< Signal name */
#define BOARD_INITLCDPINS_LCDIF_D15_CHANNEL 15U /*!< Signal channel */
/* GPIO_B0_01 (coord E7), LCDIF_ENABLE */
/* Routed pin properties */
#define BOARD_INITLCDPINS_LCDIF_ENABLE_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITLCDPINS_LCDIF_ENABLE_SIGNAL lcdif_enable /*!< Signal name */
/* GPIO_B0_02 (coord E8), LCDIF_HSYNC */
/* Routed pin properties */
#define BOARD_INITLCDPINS_LCDIF_HSYNC_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITLCDPINS_LCDIF_HSYNC_SIGNAL lcdif_hsync /*!< Signal name */
/* GPIO_B0_03 (coord D8), LCDIF_VSYNC */
/* Routed pin properties */
#define BOARD_INITLCDPINS_LCDIF_VSYNC_PERIPHERAL LCDIF /*!< Peripheral name */
#define BOARD_INITLCDPINS_LCDIF_VSYNC_SIGNAL lcdif_vsync /*!< Signal name */
/* GPIO_B1_15 (coord B14), USB_HOST_PWR/BACKLIGHT_CTL */
/* Routed pin properties */
#define BOARD_INITLCDPINS_BACKLIGHT_CTL_PERIPHERAL GPIO2 /*!< Peripheral name */
#define BOARD_INITLCDPINS_BACKLIGHT_CTL_SIGNAL gpio_io /*!< Signal name */
#define BOARD_INITLCDPINS_BACKLIGHT_CTL_CHANNEL 31U /*!< Signal channel */
/* Symbols to be used with GPIO driver */
#define BOARD_INITLCDPINS_BACKLIGHT_CTL_GPIO GPIO2 /*!< GPIO peripheral base pointer */
#define BOARD_INITLCDPINS_BACKLIGHT_CTL_GPIO_PIN 31U /*!< GPIO pin number */
#define BOARD_INITLCDPINS_BACKLIGHT_CTL_GPIO_PIN_MASK (1U << 31U) /*!< GPIO pin mask */
#define BOARD_INITLCDPINS_BACKLIGHT_CTL_PORT GPIO2 /*!< PORT peripheral base pointer */
#define BOARD_INITLCDPINS_BACKLIGHT_CTL_PIN 31U /*!< PORT pin number */
#define BOARD_INITLCDPINS_BACKLIGHT_CTL_PIN_MASK (1U << 31U) /*!< PORT pin mask */
/*!
* @brief Configures pin routing and optionally pin electrical features.
*
*/
void BOARD_InitLCDPins(void);
/* GPIO_AD_B0_14 (coord H14), CAN2_TX/U12[1] */
/* Routed pin properties */
#define BOARD_INITCANPINS_CAN2_TX_PERIPHERAL CAN2 /*!< Peripheral name */
#define BOARD_INITCANPINS_CAN2_TX_SIGNAL TX /*!< Signal name */
/* GPIO_AD_B0_15 (coord L10), CAN2_RX/U12[4] */
/* Routed pin properties */
#define BOARD_INITCANPINS_CAN2_RX_PERIPHERAL CAN2 /*!< Peripheral name */
#define BOARD_INITCANPINS_CAN2_RX_SIGNAL RX /*!< Signal name */
/*!
* @brief Configures pin routing and optionally pin electrical features.
*
*/
void BOARD_InitCANPins(void);
/* GPIO_EMC_40 (coord A7), ENET_MDC */
/* Routed pin properties */
#define BOARD_INITENETPINS_ENET_MDC_PERIPHERAL ENET /*!< Peripheral name */
#define BOARD_INITENETPINS_ENET_MDC_SIGNAL enet_mdc /*!< Signal name */
/* GPIO_EMC_41 (coord C7), ENET_MDIO */
/* Routed pin properties */
#define BOARD_INITENETPINS_ENET_MDIO_PERIPHERAL ENET /*!< Peripheral name */
#define BOARD_INITENETPINS_ENET_MDIO_SIGNAL enet_mdio /*!< Signal name */
/* GPIO_B1_10 (coord B13), ENET_TX_CLK */
/* Routed pin properties */
#define BOARD_INITENETPINS_ENET_TX_CLK_PERIPHERAL ENET /*!< Peripheral name */
#define BOARD_INITENETPINS_ENET_TX_CLK_SIGNAL enet_ref_clk /*!< Signal name */
/* GPIO_B1_04 (coord E12), ENET_RXD0 */
/* Routed pin properties */
#define BOARD_INITENETPINS_ENET_RXD0_PERIPHERAL ENET /*!< Peripheral name */
#define BOARD_INITENETPINS_ENET_RXD0_SIGNAL enet_rx_data /*!< Signal name */
#define BOARD_INITENETPINS_ENET_RXD0_CHANNEL 0U /*!< Signal channel */
/* GPIO_B1_05 (coord D12), ENET_RXD1 */
/* Routed pin properties */
#define BOARD_INITENETPINS_ENET_RXD1_PERIPHERAL ENET /*!< Peripheral name */
#define BOARD_INITENETPINS_ENET_RXD1_SIGNAL enet_rx_data /*!< Signal name */
#define BOARD_INITENETPINS_ENET_RXD1_CHANNEL 1U /*!< Signal channel */
/* GPIO_B1_06 (coord C12), ENET_CRS_DV */
/* Routed pin properties */
#define BOARD_INITENETPINS_ENET_CRS_DV_PERIPHERAL ENET /*!< Peripheral name */
#define BOARD_INITENETPINS_ENET_CRS_DV_SIGNAL enet_rx_en /*!< Signal name */
/* GPIO_B1_11 (coord C13), ENET_RXER */
/* Routed pin properties */
#define BOARD_INITENETPINS_ENET_RXER_PERIPHERAL ENET /*!< Peripheral name */
#define BOARD_INITENETPINS_ENET_RXER_SIGNAL enet_rx_er /*!< Signal name */
/* GPIO_B1_07 (coord B12), ENET_TXD0 */
/* Routed pin properties */
#define BOARD_INITENETPINS_ENET_TXD0_PERIPHERAL ENET /*!< Peripheral name */
#define BOARD_INITENETPINS_ENET_TXD0_SIGNAL enet_tx_data /*!< Signal name */
#define BOARD_INITENETPINS_ENET_TXD0_CHANNEL 0U /*!< Signal channel */
/* GPIO_B1_08 (coord A12), ENET_TXD1 */
/* Routed pin properties */
#define BOARD_INITENETPINS_ENET_TXD1_PERIPHERAL ENET /*!< Peripheral name */
#define BOARD_INITENETPINS_ENET_TXD1_SIGNAL enet_tx_data /*!< Signal name */
#define BOARD_INITENETPINS_ENET_TXD1_CHANNEL 1U /*!< Signal channel */
/* GPIO_B1_09 (coord A13), ENET_TXEN */
/* Routed pin properties */
#define BOARD_INITENETPINS_ENET_TXEN_PERIPHERAL ENET /*!< Peripheral name */
#define BOARD_INITENETPINS_ENET_TXEN_SIGNAL enet_tx_en /*!< Signal name */
/*!
* @brief Configures pin routing and optionally pin electrical features.
*
*/
void BOARD_InitENETPins(void);
/* GPIO_SD_B0_05 (coord J2), SD1_D3 */
/* Routed pin properties */
#define BOARD_INITUSDHCPINS_SD1_D3_PERIPHERAL USDHC1 /*!< Peripheral name */
#define BOARD_INITUSDHCPINS_SD1_D3_SIGNAL usdhc_data /*!< Signal name */
#define BOARD_INITUSDHCPINS_SD1_D3_CHANNEL 3U /*!< Signal channel */
/* GPIO_SD_B0_04 (coord H2), SD1_D2 */
/* Routed pin properties */
#define BOARD_INITUSDHCPINS_SD1_D2_PERIPHERAL USDHC1 /*!< Peripheral name */
#define BOARD_INITUSDHCPINS_SD1_D2_SIGNAL usdhc_data /*!< Signal name */
#define BOARD_INITUSDHCPINS_SD1_D2_CHANNEL 2U /*!< Signal channel */
/* GPIO_SD_B0_03 (coord K1), SD1_D1/J24[5]/SPI_MISO */
/* Routed pin properties */
#define BOARD_INITUSDHCPINS_SD1_D1_PERIPHERAL USDHC1 /*!< Peripheral name */
#define BOARD_INITUSDHCPINS_SD1_D1_SIGNAL usdhc_data /*!< Signal name */
#define BOARD_INITUSDHCPINS_SD1_D1_CHANNEL 1U /*!< Signal channel */
/* GPIO_SD_B0_02 (coord J1), SD1_D0/J24[4]/SPI_MOSI/PWM */
/* Routed pin properties */
#define BOARD_INITUSDHCPINS_SD1_D0_PERIPHERAL USDHC1 /*!< Peripheral name */
#define BOARD_INITUSDHCPINS_SD1_D0_SIGNAL usdhc_data /*!< Signal name */
#define BOARD_INITUSDHCPINS_SD1_D0_CHANNEL 0U /*!< Signal channel */
/* GPIO_SD_B0_00 (coord J4), SD1_CMD/J24[6] */
/* Routed pin properties */
#define BOARD_INITUSDHCPINS_SD1_CMD_PERIPHERAL USDHC1 /*!< Peripheral name */
#define BOARD_INITUSDHCPINS_SD1_CMD_SIGNAL usdhc_cmd /*!< Signal name */
/* GPIO_SD_B0_01 (coord J3), SD1_CLK/J24[3] */
/* Routed pin properties */
#define BOARD_INITUSDHCPINS_SD1_CLK_PERIPHERAL USDHC1 /*!< Peripheral name */
#define BOARD_INITUSDHCPINS_SD1_CLK_SIGNAL usdhc_clk /*!< Signal name */
/* GPIO_B1_14 (coord C14), SD0_VSELECT */
/* Routed pin properties */
#define BOARD_INITUSDHCPINS_SD0_VSELECT_PERIPHERAL USDHC1 /*!< Peripheral name */
#define BOARD_INITUSDHCPINS_SD0_VSELECT_SIGNAL usdhc_vselect /*!< Signal name */
/*!
* @brief Configures pin routing and optionally pin electrical features.
*
*/
void BOARD_InitUSDHCPins(void);
/* GPIO_SD_B1_08 (coord P3), FlexSPI_D0_A */
/* Routed pin properties */
#define BOARD_INITQSPIPINS_FlexSPI_D0_A_PERIPHERAL FLEXSPI /*!< Peripheral name */
#define BOARD_INITQSPIPINS_FlexSPI_D0_A_SIGNAL FLEXSPI_A_DATA0 /*!< Signal name */
/* GPIO_SD_B1_09 (coord N4), FlexSPI_D1_A */
/* Routed pin properties */
#define BOARD_INITQSPIPINS_FlexSPI_D1_A_PERIPHERAL FLEXSPI /*!< Peripheral name */
#define BOARD_INITQSPIPINS_FlexSPI_D1_A_SIGNAL FLEXSPI_A_DATA1 /*!< Signal name */
/* GPIO_SD_B1_10 (coord P4), FlexSPI_D2_A */
/* Routed pin properties */
#define BOARD_INITQSPIPINS_FlexSPI_D2_A_PERIPHERAL FLEXSPI /*!< Peripheral name */
#define BOARD_INITQSPIPINS_FlexSPI_D2_A_SIGNAL FLEXSPI_A_DATA2 /*!< Signal name */
/* GPIO_SD_B1_11 (coord P5), FlexSPI_D3_A */
/* Routed pin properties */
#define BOARD_INITQSPIPINS_FlexSPI_D3_A_PERIPHERAL FLEXSPI /*!< Peripheral name */
#define BOARD_INITQSPIPINS_FlexSPI_D3_A_SIGNAL FLEXSPI_A_DATA3 /*!< Signal name */
/* GPIO_SD_B1_07 (coord L4), FlexSPI_CLK */
/* Routed pin properties */
#define BOARD_INITQSPIPINS_FlexSPI_CLK_PERIPHERAL FLEXSPI /*!< Peripheral name */
#define BOARD_INITQSPIPINS_FlexSPI_CLK_SIGNAL FLEXSPI_A_SCLK /*!< Signal name */
/* GPIO_SD_B1_06 (coord L3), FlexSPI_SS0 */
/* Routed pin properties */
#define BOARD_INITQSPIPINS_FlexSPI_SS0_PERIPHERAL FLEXSPI /*!< Peripheral name */
#define BOARD_INITQSPIPINS_FlexSPI_SS0_SIGNAL FLEXSPI_A_SS0_B /*!< Signal name */
/* GPIO_SD_B1_05 (coord N3), FlexSPI_DQS */
/* Routed pin properties */
#define BOARD_INITQSPIPINS_FlexSPI_DQS_PERIPHERAL FLEXSPI /*!< Peripheral name */
#define BOARD_INITQSPIPINS_FlexSPI_DQS_SIGNAL FLEXSPI_A_DQS /*!< Signal name */
/*!
* @brief Configures pin routing and optionally pin electrical features.
*
*/
void BOARD_InitQSPIPins(void);
#if defined(__cplusplus)
}
#endif
/*!
* @}
*/
#endif /* _PIN_MUX_H_ */
/***********************************************************************************************************************
* EOF
**********************************************************************************************************************/

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managed_components/espressif__tinyusb/hw/bsp/imxrt/boards/mimxrt1064_evk/evkmimxrt1064_flexspi_nor_config.c Normal file
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/*
* Copyright 2018 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "evkmimxrt1064_flexspi_nor_config.h"
/* Component ID definition, used by tools. */
#ifndef FSL_COMPONENT_ID
#define FSL_COMPONENT_ID "platform.drivers.xip_board"
#endif
/*******************************************************************************
* Code
******************************************************************************/
#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
__attribute__((section(".boot_hdr.conf"), used))
#elif defined(__ICCARM__)
#pragma location = ".boot_hdr.conf"
#endif
const flexspi_nor_config_t qspiflash_config = {
.memConfig =
{
.tag = FLEXSPI_CFG_BLK_TAG,
.version = FLEXSPI_CFG_BLK_VERSION,
.readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad,
.csHoldTime = 3u,
.csSetupTime = 3u,
// Enable DDR mode, Wordaddassable, Safe configuration, Differential clock
.sflashPadType = kSerialFlash_4Pads,
.serialClkFreq = kFlexSpiSerialClk_100MHz,
.sflashA1Size = 8u * 1024u * 1024u,
.lookupTable =
{
// Read LUTs
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18),
FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04),
},
},
.pageSize = 256u,
.sectorSize = 4u * 1024u,
.blockSize = 256u * 1024u,
.isUniformBlockSize = false,
};
#endif /* XIP_BOOT_HEADER_ENABLE */

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/*
* Copyright 2018 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __EVKMIMXRT1064_FLEXSPI_NOR_CONFIG__
#define __EVKMIMXRT1064_FLEXSPI_NOR_CONFIG__
#include <stdint.h>
#include <stdbool.h>
#include "fsl_common.h"
/*! @name Driver version */
/*@{*/
/*! @brief XIP_BOARD driver version 2.0.0. */
#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
/*@}*/
/* FLEXSPI memory config block related definitions */
#define FLEXSPI_CFG_BLK_TAG (0x42464346UL) // ascii "FCFB" Big Endian
#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0
#define FLEXSPI_CFG_BLK_SIZE (512)
/* FLEXSPI Feature related definitions */
#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1
/* Lookup table related definitions */
#define CMD_INDEX_READ 0
#define CMD_INDEX_READSTATUS 1
#define CMD_INDEX_WRITEENABLE 2
#define CMD_INDEX_WRITE 4
#define CMD_LUT_SEQ_IDX_READ 0
#define CMD_LUT_SEQ_IDX_READSTATUS 1
#define CMD_LUT_SEQ_IDX_WRITEENABLE 3
#define CMD_LUT_SEQ_IDX_WRITE 9
#define CMD_SDR 0x01
#define CMD_DDR 0x21
#define RADDR_SDR 0x02
#define RADDR_DDR 0x22
#define CADDR_SDR 0x03
#define CADDR_DDR 0x23
#define MODE1_SDR 0x04
#define MODE1_DDR 0x24
#define MODE2_SDR 0x05
#define MODE2_DDR 0x25
#define MODE4_SDR 0x06
#define MODE4_DDR 0x26
#define MODE8_SDR 0x07
#define MODE8_DDR 0x27
#define WRITE_SDR 0x08
#define WRITE_DDR 0x28
#define READ_SDR 0x09
#define READ_DDR 0x29
#define LEARN_SDR 0x0A
#define LEARN_DDR 0x2A
#define DATSZ_SDR 0x0B
#define DATSZ_DDR 0x2B
#define DUMMY_SDR 0x0C
#define DUMMY_DDR 0x2C
#define DUMMY_RWDS_SDR 0x0D
#define DUMMY_RWDS_DDR 0x2D
#define JMP_ON_CS 0x1F
#define STOP 0
#define FLEXSPI_1PAD 0
#define FLEXSPI_2PAD 1
#define FLEXSPI_4PAD 2
#define FLEXSPI_8PAD 3
#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \
(FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \
FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))
//!@brief Definitions for FlexSPI Serial Clock Frequency
typedef enum _FlexSpiSerialClockFreq
{
kFlexSpiSerialClk_30MHz = 1,
kFlexSpiSerialClk_50MHz = 2,
kFlexSpiSerialClk_60MHz = 3,
kFlexSpiSerialClk_75MHz = 4,
kFlexSpiSerialClk_80MHz = 5,
kFlexSpiSerialClk_100MHz = 6,
kFlexSpiSerialClk_120MHz = 7,
kFlexSpiSerialClk_133MHz = 8,
kFlexSpiSerialClk_166MHz = 9,
} flexspi_serial_clk_freq_t;
//!@brief FlexSPI clock configuration type
enum
{
kFlexSpiClk_SDR, //!< Clock configure for SDR mode
kFlexSpiClk_DDR, //!< Clock configurat for DDR mode
};
//!@brief FlexSPI Read Sample Clock Source definition
typedef enum _FlashReadSampleClkSource
{
kFlexSPIReadSampleClk_LoopbackInternally = 0,
kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1,
kFlexSPIReadSampleClk_LoopbackFromSckPad = 2,
kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3,
} flexspi_read_sample_clk_t;
//!@brief Misc feature bit definitions
enum
{
kFlexSpiMiscOffset_DiffClkEnable = 0, //!< Bit for Differential clock enable
kFlexSpiMiscOffset_Ck2Enable = 1, //!< Bit for CK2 enable
kFlexSpiMiscOffset_ParallelEnable = 2, //!< Bit for Parallel mode enable
kFlexSpiMiscOffset_WordAddressableEnable = 3, //!< Bit for Word Addressable enable
kFlexSpiMiscOffset_SafeConfigFreqEnable = 4, //!< Bit for Safe Configuration Frequency enable
kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, //!< Bit for Pad setting override enable
kFlexSpiMiscOffset_DdrModeEnable = 6, //!< Bit for DDR clock confiuration indication.
};
//!@brief Flash Type Definition
enum
{
kFlexSpiDeviceType_SerialNOR = 1, //!< Flash devices are Serial NOR
kFlexSpiDeviceType_SerialNAND = 2, //!< Flash devices are Serial NAND
kFlexSpiDeviceType_SerialRAM = 3, //!< Flash devices are Serial RAM/HyperFLASH
kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND
kFlexSpiDeviceType_MCP_NOR_RAM = 0x13, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial RAMs
};
//!@brief Flash Pad Definitions
enum
{
kSerialFlash_1Pad = 1,
kSerialFlash_2Pads = 2,
kSerialFlash_4Pads = 4,
kSerialFlash_8Pads = 8,
};
//!@brief FlexSPI LUT Sequence structure
typedef struct _lut_sequence
{
uint8_t seqNum; //!< Sequence Number, valid number: 1-16
uint8_t seqId; //!< Sequence Index, valid number: 0-15
uint16_t reserved;
} flexspi_lut_seq_t;
//!@brief Flash Configuration Command Type
enum
{
kDeviceConfigCmdType_Generic, //!< Generic command, for example: configure dummy cycles, drive strength, etc
kDeviceConfigCmdType_QuadEnable, //!< Quad Enable command
kDeviceConfigCmdType_Spi2Xpi, //!< Switch from SPI to DPI/QPI/OPI mode
kDeviceConfigCmdType_Xpi2Spi, //!< Switch from DPI/QPI/OPI to SPI mode
kDeviceConfigCmdType_Spi2NoCmd, //!< Switch to 0-4-4/0-8-8 mode
kDeviceConfigCmdType_Reset, //!< Reset device command
};
//!@brief FlexSPI Memory Configuration Block
typedef struct _FlexSPIConfig
{
uint32_t tag; //!< [0x000-0x003] Tag, fixed value 0x42464346UL
uint32_t version; //!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix
uint32_t reserved0; //!< [0x008-0x00b] Reserved for future use
uint8_t readSampleClkSrc; //!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3
uint8_t csHoldTime; //!< [0x00d-0x00d] CS hold time, default value: 3
uint8_t csSetupTime; //!< [0x00e-0x00e] CS setup time, default value: 3
uint8_t columnAddressWidth; //!< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For
//! Serial NAND, need to refer to datasheet
uint8_t deviceModeCfgEnable; //!< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable
uint8_t deviceModeType; //!< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch,
//! Generic configuration, etc.
uint16_t waitTimeCfgCommands; //!< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for
//! DPI/QPI/OPI switch or reset command
flexspi_lut_seq_t deviceModeSeq; //!< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt
//! sequence number, [31:16] Reserved
uint32_t deviceModeArg; //!< [0x018-0x01b] Argument/Parameter for device configuration
uint8_t configCmdEnable; //!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable
uint8_t configModeType[3]; //!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe
flexspi_lut_seq_t
configCmdSeqs[3]; //!< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq
uint32_t reserved1; //!< [0x02c-0x02f] Reserved for future use
uint32_t configCmdArgs[3]; //!< [0x030-0x03b] Arguments/Parameters for device Configuration commands
uint32_t reserved2; //!< [0x03c-0x03f] Reserved for future use
uint32_t controllerMiscOption; //!< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more
//! details
uint8_t deviceType; //!< [0x044-0x044] Device Type: See Flash Type Definition for more details
uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal
uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequency, device specific definitions, See System Boot
//! Chapter for more details
uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot
//! be done using 1 LUT sequence, currently, only applicable to HyperFLASH
uint32_t reserved3[2]; //!< [0x048-0x04f] Reserved for future use
uint32_t sflashA1Size; //!< [0x050-0x053] Size of Flash connected to A1
uint32_t sflashA2Size; //!< [0x054-0x057] Size of Flash connected to A2
uint32_t sflashB1Size; //!< [0x058-0x05b] Size of Flash connected to B1
uint32_t sflashB2Size; //!< [0x05c-0x05f] Size of Flash connected to B2
uint32_t csPadSettingOverride; //!< [0x060-0x063] CS pad setting override value
uint32_t sclkPadSettingOverride; //!< [0x064-0x067] SCK pad setting override value
uint32_t dataPadSettingOverride; //!< [0x068-0x06b] data pad setting override value
uint32_t dqsPadSettingOverride; //!< [0x06c-0x06f] DQS pad setting override value
uint32_t timeoutInMs; //!< [0x070-0x073] Timeout threshold for read status command
uint32_t commandInterval; //!< [0x074-0x077] CS deselect interval between two commands
uint16_t dataValidTime[2]; //!< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns
uint16_t busyOffset; //!< [0x07c-0x07d] Busy offset, valid value: 0-31
uint16_t busyBitPolarity; //!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 -
//! busy flag is 0 when flash device is busy
uint32_t lookupTable[64]; //!< [0x080-0x17f] Lookup table holds Flash command sequences
flexspi_lut_seq_t lutCustomSeq[12]; //!< [0x180-0x1af] Customizable LUT Sequences
uint32_t reserved4[4]; //!< [0x1b0-0x1bf] Reserved for future use
} flexspi_mem_config_t;
/* */
#define NOR_CMD_INDEX_READ CMD_INDEX_READ //!< 0
#define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS //!< 1
#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE //!< 2
#define NOR_CMD_INDEX_ERASESECTOR 3 //!< 3
#define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE //!< 4
#define NOR_CMD_INDEX_CHIPERASE 5 //!< 5
#define NOR_CMD_INDEX_DUMMY 6 //!< 6
#define NOR_CMD_INDEX_ERASEBLOCK 7 //!< 7
#define NOR_CMD_LUT_SEQ_IDX_READ CMD_LUT_SEQ_IDX_READ //!< 0 READ LUT sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_READSTATUS \
CMD_LUT_SEQ_IDX_READSTATUS //!< 1 Read Status LUT sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \
2 //!< 2 Read status DPI/QPI/OPI sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE \
CMD_LUT_SEQ_IDX_WRITEENABLE //!< 3 Write Enable sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \
4 //!< 4 Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5 //!< 5 Erase Sector sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8 //!< 8 Erase Block sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM \
CMD_LUT_SEQ_IDX_WRITE //!< 9 Program sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11 //!< 11 Chip Erase sequence in lookupTable id stored in config block
#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13 //!< 13 Read SFDP sequence in lookupTable id stored in config block
#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \
14 //!< 14 Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block
#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \
15 //!< 15 Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config blobk
/*
* Serial NOR configuration block
*/
typedef struct _flexspi_nor_config
{
flexspi_mem_config_t memConfig; //!< Common memory configuration info via FlexSPI
uint32_t pageSize; //!< Page size of Serial NOR
uint32_t sectorSize; //!< Sector size of Serial NOR
uint8_t ipcmdSerialClkFreq; //!< Clock frequency for IP command
uint8_t isUniformBlockSize; //!< Sector/Block size is the same
uint8_t reserved0[2]; //!< Reserved for future use
uint8_t serialNorType; //!< Serial NOR Flash type: 0/1/2/3
uint8_t needExitNoCmdMode; //!< Need to exit NoCmd mode before other IP command
uint8_t halfClkForNonReadCmd; //!< Half the Serial Clock for non-read command: true/false
uint8_t needRestoreNoCmdMode; //!< Need to Restore NoCmd mode after IP command execution
uint32_t blockSize; //!< Block size
uint32_t reserve2[11]; //!< Reserved for future use
} flexspi_nor_config_t;
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __cplusplus
}
#endif
#endif /* __EVKMIMXRT1064_FLEXSPI_NOR_CONFIG__ */

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managed_components/espressif__tinyusb/hw/bsp/imxrt/boards/mimxrt1064_evk/mimxrt1064_evk.mex Normal file
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26
managed_components/espressif__tinyusb/hw/bsp/imxrt/boards/mimxrt1170_evkb/board.cmake Normal file
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@@ -0,0 +1,26 @@
set(MCU_VARIANT MIMXRT1176)
if (M4 STREQUAL "1")
set(MCU_CORE _cm4)
set(JLINK_CORE _M4)
set(LD_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/${MCU_VARIANT}xxxxx${MCU_CORE}_ram.ld)
set(CMAKE_SYSTEM_CPU cortex-m4 CACHE INTERNAL "System Processor")
else ()
set(MCU_CORE _cm7)
set(JLINK_CORE _M7)
endif()
set(JLINK_DEVICE MIMXRT1176xxxA${JLINK_CORE})
set(PYOCD_TARGET mimxrt1170${MCU_CORE})
set(NXPLINK_DEVICE MIMXRT1176xxxxx:MIMXRT1170-EVK)
function(update_board TARGET)
target_sources(${TARGET} PUBLIC
${CMAKE_CURRENT_FUNCTION_LIST_DIR}/evkbmimxrt1170_flexspi_nor_config.c
)
target_compile_definitions(${TARGET} PUBLIC
CPU_MIMXRT1176DVMAA${MCU_CORE}
BOARD_TUD_RHPORT=0
BOARD_TUH_RHPORT=1
)
endfunction()

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managed_components/espressif__tinyusb/hw/bsp/imxrt/boards/mimxrt1170_evkb/board.h Normal file
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@@ -0,0 +1,435 @@
/*
* The MIT License (MIT)
*
* Copyright (c) 2019, Ha Thach (tinyusb.org)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* This file is part of the TinyUSB stack.
*/
/* metadata:
name: i.MX RT1070 Evaluation Kit
url: https://www.nxp.com/design/design-center/development-boards-and-designs/i-mx-evaluation-and-development-boards/i-mx-rt1170-evaluation-kit:MIMXRT1170-EVKB
*/
#ifndef BOARD_MIMXRT1170_EVKB_H_
#define BOARD_MIMXRT1170_EVKB_H_
// required since iMXRT MCUX-SDK include this file for board size
#define BOARD_FLASH_SIZE (0x1000000U)
// LED: IOMUXC_GPIO_AD_04_GPIO9_IO03
#define LED_PORT BOARD_INITPINS_USER_LED_PERIPHERAL
#define LED_PIN BOARD_INITPINS_USER_LED_CHANNEL
#define LED_STATE_ON 0
// SW8 button: IOMUXC_WAKEUP_DIG_GPIO13_IO00
#define BUTTON_PORT BOARD_INITPINS_USER_BUTTON_PERIPHERAL
#define BUTTON_PIN BOARD_INITPINS_USER_BUTTON_CHANNEL
#define BUTTON_STATE_ACTIVE 0
// UART: IOMUXC_GPIO_AD_B0_13_LPUART1_RX, IOMUXC_GPIO_AD_B0_12_LPUART1_TX
#define UART_PORT LPUART1
#define UART_CLK_ROOT BOARD_BOOTCLOCKRUN_LPUART10_CLK_ROOT
//--------------------------------------------------------------------
// MPU configuration
//--------------------------------------------------------------------
#if __CORTEX_M == 7
static inline void BOARD_ConfigMPU(void) {
#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
extern uint32_t Image$$RW_m_ncache$$Base[];
/* RW_m_ncache_unused is a auxiliary region which is used to get the whole size of noncache section */
extern uint32_t Image$$RW_m_ncache_unused$$Base[];
extern uint32_t Image$$RW_m_ncache_unused$$ZI$$Limit[];
uint32_t nonCacheStart = (uint32_t) Image$$RW_m_ncache$$Base;
uint32_t size = ((uint32_t) Image$$RW_m_ncache_unused$$Base == nonCacheStart) ? 0 : ((uint32_t) Image$$RW_m_ncache_unused$$ZI$$Limit - nonCacheStart);
#elif defined(__MCUXPRESSO)
#if defined(__USE_SHMEM)
extern uint32_t __base_rpmsg_sh_mem;
extern uint32_t __top_rpmsg_sh_mem;
uint32_t nonCacheStart = (uint32_t) (&__base_rpmsg_sh_mem);
uint32_t size = (uint32_t) (&__top_rpmsg_sh_mem) - nonCacheStart;
#else
extern uint32_t __base_NCACHE_REGION;
extern uint32_t __top_NCACHE_REGION;
uint32_t nonCacheStart = (uint32_t) (&__base_NCACHE_REGION);
uint32_t size = (uint32_t) (&__top_NCACHE_REGION) - nonCacheStart;
#endif
#elif defined(__ICCARM__) || defined(__GNUC__)
extern uint32_t __NCACHE_REGION_START[];
extern uint32_t __NCACHE_REGION_SIZE[];
uint32_t nonCacheStart = (uint32_t) __NCACHE_REGION_START;
uint32_t size = (uint32_t) __NCACHE_REGION_SIZE;
#endif
volatile uint32_t i = 0;
#if defined(__ICACHE_PRESENT) && __ICACHE_PRESENT
/* Disable I cache and D cache */
if (SCB_CCR_IC_Msk == (SCB_CCR_IC_Msk & SCB->CCR)) {
SCB_DisableICache();
}
#endif
#if defined(__DCACHE_PRESENT) && __DCACHE_PRESENT
if (SCB_CCR_DC_Msk == (SCB_CCR_DC_Msk & SCB->CCR)) {
SCB_DisableDCache();
}
#endif
/* Disable MPU */
ARM_MPU_Disable();
/* MPU configure:
* Use ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable,
* SubRegionDisable, Size)
* API in mpu_armv7.h.
* param DisableExec Instruction access (XN) disable bit,0=instruction fetches enabled, 1=instruction fetches
* disabled.
* param AccessPermission Data access permissions, allows you to configure read/write access for User and
* Privileged mode.
* Use MACROS defined in mpu_armv7.h:
* ARM_MPU_AP_NONE/ARM_MPU_AP_PRIV/ARM_MPU_AP_URO/ARM_MPU_AP_FULL/ARM_MPU_AP_PRO/ARM_MPU_AP_RO
* Combine TypeExtField/IsShareable/IsCacheable/IsBufferable to configure MPU memory access attributes.
* TypeExtField IsShareable IsCacheable IsBufferable Memory Attribute Shareability Cache
* 0 x 0 0 Strongly Ordered shareable
* 0 x 0 1 Device shareable
* 0 0 1 0 Normal not shareable Outer and inner write
* through no write allocate
* 0 0 1 1 Normal not shareable Outer and inner write
* back no write allocate
* 0 1 1 0 Normal shareable Outer and inner write
* through no write allocate
* 0 1 1 1 Normal shareable Outer and inner write
* back no write allocate
* 1 0 0 0 Normal not shareable outer and inner
* noncache
* 1 1 0 0 Normal shareable outer and inner
* noncache
* 1 0 1 1 Normal not shareable outer and inner write
* back write/read acllocate
* 1 1 1 1 Normal shareable outer and inner write
* back write/read acllocate
* 2 x 0 0 Device not shareable
* Above are normal use settings, if your want to see more details or want to config different inner/outer cache
* policy.
* please refer to Table 4-55 /4-56 in arm cortex-M7 generic user guide <dui0646b_cortex_m7_dgug.pdf>
* param SubRegionDisable Sub-region disable field. 0=sub-region is enabled, 1=sub-region is disabled.
* param Size Region size of the region to be configured. use ARM_MPU_REGION_SIZE_xxx MACRO in
* mpu_armv7.h.
*/
/*
* Add default region to deny access to whole address space to workaround speculative prefetch.
* Refer to Arm errata 1013783-B for more details.
*
*/
/* Region 0 setting: Instruction access disabled, No data access permission. */
MPU->RBAR = ARM_MPU_RBAR(0, 0x00000000U);
MPU->RASR = ARM_MPU_RASR(1, ARM_MPU_AP_NONE, 0, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_4GB);
/* Region 1 setting: Memory with Device type, not shareable, non-cacheable. */
MPU->RBAR = ARM_MPU_RBAR(1, 0x80000000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
/* Region 2 setting: Memory with Device type, not shareable, non-cacheable. */
MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
/* Region 3 setting: Memory with Device type, not shareable, non-cacheable. */
MPU->RBAR = ARM_MPU_RBAR(3, 0x00000000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB);
/* Region 4 setting: Memory with Normal type, not shareable, outer/inner write back */
MPU->RBAR = ARM_MPU_RBAR(4, 0x00000000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB);
/* Region 5 setting: Memory with Normal type, not shareable, outer/inner write back */
MPU->RBAR = ARM_MPU_RBAR(5, 0x20000000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB);
#if defined(CACHE_MODE_WRITE_THROUGH) && CACHE_MODE_WRITE_THROUGH
/* Region 6 setting: Memory with Normal type, not shareable, write through */
MPU->RBAR = ARM_MPU_RBAR(6, 0x20200000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 0, 0, ARM_MPU_REGION_SIZE_1MB);
/* Region 7 setting: Memory with Normal type, not shareable, write through */
MPU->RBAR = ARM_MPU_RBAR(7, 0x20300000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 0, 0, ARM_MPU_REGION_SIZE_512KB);
#else
/* Region 6 setting: Memory with Normal type, not shareable, outer/inner write back */
MPU->RBAR = ARM_MPU_RBAR(6, 0x20200000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_1MB);
/* Region 7 setting: Memory with Normal type, not shareable, outer/inner write back */
MPU->RBAR = ARM_MPU_RBAR(7, 0x20300000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_512KB);
#endif
#if defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)
/* Region 8 setting: Memory with Normal type, not shareable, outer/inner write back. */
MPU->RBAR = ARM_MPU_RBAR(8, 0x30000000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_RO, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_16MB);
#endif
#ifdef USE_SDRAM
#if defined(CACHE_MODE_WRITE_THROUGH) && CACHE_MODE_WRITE_THROUGH
/* Region 9 setting: Memory with Normal type, not shareable, write through */
MPU->RBAR = ARM_MPU_RBAR(9, 0x80000000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 0, 0, ARM_MPU_REGION_SIZE_64MB);
#else
/* Region 9 setting: Memory with Normal type, not shareable, outer/inner write back */
MPU->RBAR = ARM_MPU_RBAR(9, 0x80000000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_64MB);
#endif
#endif
while ((size >> i) > 0x1U) {
i++;
}
if (i != 0) {
/* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
assert(!(nonCacheStart % size));
assert(size == (uint32_t) (1 << i));
assert(i >= 5);
/* Region 10 setting: Memory with Normal type, not shareable, non-cacheable */
MPU->RBAR = ARM_MPU_RBAR(10, nonCacheStart);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 0, 0, 0, 0, i - 1);
}
/* Region 11 setting: Memory with Device type, not shareable, non-cacheable */
MPU->RBAR = ARM_MPU_RBAR(11, 0x40000000);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_16MB);
/* Region 12 setting: Memory with Device type, not shareable, non-cacheable */
MPU->RBAR = ARM_MPU_RBAR(12, 0x41000000);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_2MB);
/* Region 13 setting: Memory with Device type, not shareable, non-cacheable */
MPU->RBAR = ARM_MPU_RBAR(13, 0x41400000);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1MB);
/* Region 14 setting: Memory with Device type, not shareable, non-cacheable */
MPU->RBAR = ARM_MPU_RBAR(14, 0x41800000);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_2MB);
/* Region 15 setting: Memory with Device type, not shareable, non-cacheable */
MPU->RBAR = ARM_MPU_RBAR(15, 0x42000000);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1MB);
/* Enable MPU */
ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk | MPU_CTRL_HFNMIENA_Msk);
/* Enable I cache and D cache */
#if defined(__DCACHE_PRESENT) && __DCACHE_PRESENT
SCB_EnableDCache();
#endif
#if defined(__ICACHE_PRESENT) && __ICACHE_PRESENT
SCB_EnableICache();
#endif
}
#elif __CORTEX_M == 4
static void BOARD_ConfigMPU(void) {
#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
extern uint32_t Image$$RW_m_ncache$$Base[];
/* RW_m_ncache_unused is a auxiliary region which is used to get the whole size of noncache section */
extern uint32_t Image$$RW_m_ncache_unused$$Base[];
extern uint32_t Image$$RW_m_ncache_unused$$ZI$$Limit[];
uint32_t nonCacheStart = (uint32_t) Image$$RW_m_ncache$$Base;
uint32_t nonCacheSize = ((uint32_t) Image$$RW_m_ncache_unused$$Base == nonCacheStart) ? 0 : ((uint32_t) Image$$RW_m_ncache_unused$$ZI$$Limit - nonCacheStart);
#elif defined(__MCUXPRESSO)
extern uint32_t __base_NCACHE_REGION;
extern uint32_t __top_NCACHE_REGION;
uint32_t nonCacheStart = (uint32_t) (&__base_NCACHE_REGION);
uint32_t nonCacheSize = (uint32_t) (&__top_NCACHE_REGION) - nonCacheStart;
#elif defined(__ICCARM__) || defined(__GNUC__)
extern uint32_t __NCACHE_REGION_START[];
extern uint32_t __NCACHE_REGION_SIZE[];
uint32_t nonCacheStart = (uint32_t) __NCACHE_REGION_START;
uint32_t nonCacheSize = (uint32_t) __NCACHE_REGION_SIZE;
#endif
#if defined(__USE_SHMEM)
#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
extern uint32_t Image$$RPMSG_SH_MEM$$Base[];
/* RPMSG_SH_MEM_unused is a auxiliary region which is used to get the whole size of RPMSG_SH_MEM section */
extern uint32_t Image$$RPMSG_SH_MEM_unused$$Base[];
extern uint32_t Image$$RPMSG_SH_MEM_unused$$ZI$$Limit[];
uint32_t rpmsgShmemStart = (uint32_t) Image$$RPMSG_SH_MEM$$Base;
uint32_t rpmsgShmemSize = (uint32_t) Image$$RPMSG_SH_MEM_unused$$ZI$$Limit - rpmsgShmemStart;
#elif defined(__MCUXPRESSO)
extern uint32_t __base_rpmsg_sh_mem;
extern uint32_t __top_rpmsg_sh_mem;
uint32_t rpmsgShmemStart = (uint32_t) (&__base_rpmsg_sh_mem);
uint32_t rpmsgShmemSize = (uint32_t) (&__top_rpmsg_sh_mem) - rpmsgShmemStart;
#elif defined(__ICCARM__) || defined(__GNUC__)
extern uint32_t __RPMSG_SH_MEM_START[];
extern uint32_t __RPMSG_SH_MEM_SIZE[];
uint32_t rpmsgShmemStart = (uint32_t) __RPMSG_SH_MEM_START;
uint32_t rpmsgShmemSize = (uint32_t) __RPMSG_SH_MEM_SIZE;
#endif
#endif
uint32_t i = 0;
/* Only config non-cacheable region on system bus */
assert(nonCacheStart >= 0x20000000);
/* Disable code bus cache */
if (LMEM_PCCCR_ENCACHE_MASK == (LMEM_PCCCR_ENCACHE_MASK & LMEM->PCCCR)) {
/* Enable the processor code bus to push all modified lines. */
LMEM->PCCCR |= LMEM_PCCCR_PUSHW0_MASK | LMEM_PCCCR_PUSHW1_MASK | LMEM_PCCCR_GO_MASK;
/* Wait until the cache command completes. */
while ((LMEM->PCCCR & LMEM_PCCCR_GO_MASK) != 0U) {
}
/* As a precaution clear the bits to avoid inadvertently re-running this command. */
LMEM->PCCCR &= ~(LMEM_PCCCR_PUSHW0_MASK | LMEM_PCCCR_PUSHW1_MASK);
/* Now disable the cache. */
LMEM->PCCCR &= ~LMEM_PCCCR_ENCACHE_MASK;
}
/* Disable system bus cache */
if (LMEM_PSCCR_ENCACHE_MASK == (LMEM_PSCCR_ENCACHE_MASK & LMEM->PSCCR)) {
/* Enable the processor system bus to push all modified lines. */
LMEM->PSCCR |= LMEM_PSCCR_PUSHW0_MASK | LMEM_PSCCR_PUSHW1_MASK | LMEM_PSCCR_GO_MASK;
/* Wait until the cache command completes. */
while ((LMEM->PSCCR & LMEM_PSCCR_GO_MASK) != 0U) {
}
/* As a precaution clear the bits to avoid inadvertently re-running this command. */
LMEM->PSCCR &= ~(LMEM_PSCCR_PUSHW0_MASK | LMEM_PSCCR_PUSHW1_MASK);
/* Now disable the cache. */
LMEM->PSCCR &= ~LMEM_PSCCR_ENCACHE_MASK;
}
/* Disable MPU */
ARM_MPU_Disable();
#if defined(CACHE_MODE_WRITE_THROUGH) && CACHE_MODE_WRITE_THROUGH
/* Region 0 setting: Memory with Normal type, not shareable, write through */
MPU->RBAR = ARM_MPU_RBAR(0, 0x20200000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 0, 0, ARM_MPU_REGION_SIZE_1MB);
/* Region 1 setting: Memory with Normal type, not shareable, write through */
MPU->RBAR = ARM_MPU_RBAR(1, 0x20300000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 0, 0, ARM_MPU_REGION_SIZE_512KB);
/* Region 2 setting: Memory with Normal type, not shareable, write through */
MPU->RBAR = ARM_MPU_RBAR(2, 0x80000000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 0, 0, ARM_MPU_REGION_SIZE_64MB);
while ((nonCacheSize >> i) > 0x1U) {
i++;
}
if (i != 0) {
/* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
assert(!(nonCacheStart % nonCacheSize));
assert(nonCacheSize == (uint32_t) (1 << i));
assert(i >= 5);
/* Region 3 setting: Memory with device type, not shareable, non-cacheable */
MPU->RBAR = ARM_MPU_RBAR(3, nonCacheStart);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, i - 1);
}
#if defined(__USE_SHMEM)
i = 0;
while ((rpmsgShmemSize >> i) > 0x1U) {
i++;
}
if (i != 0) {
/* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
assert(!(rpmsgShmemStart % rpmsgShmemSize));
assert(rpmsgShmemSize == (uint32_t) (1 << i));
assert(i >= 5);
/* Region 4 setting: Memory with device type, not shareable, non-cacheable */
MPU->RBAR = ARM_MPU_RBAR(4, rpmsgShmemStart);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, i - 1);
}
#endif
#else
while ((nonCacheSize >> i) > 0x1U) {
i++;
}
if (i != 0) {
/* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
assert(!(nonCacheStart % nonCacheSize));
assert(nonCacheSize == (uint32_t) (1 << i));
assert(i >= 5);
/* Region 0 setting: Memory with device type, not shareable, non-cacheable */
MPU->RBAR = ARM_MPU_RBAR(0, nonCacheStart);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, i - 1);
}
#if defined(__USE_SHMEM)
i = 0;
while ((rpmsgShmemSize >> i) > 0x1U) {
i++;
}
if (i != 0) {
/* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
assert(!(rpmsgShmemStart % rpmsgShmemSize));
assert(rpmsgShmemSize == (uint32_t) (1 << i));
assert(i >= 5);
/* Region 1 setting: Memory with device type, not shareable, non-cacheable */
MPU->RBAR = ARM_MPU_RBAR(1, rpmsgShmemStart);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, i - 1);
}
#endif
#endif
/* Enable MPU */
ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk | MPU_CTRL_HFNMIENA_Msk);
/* Enables the processor system bus to invalidate all lines in both ways.
and Initiate the processor system bus cache command. */
LMEM->PSCCR |= LMEM_PSCCR_INVW0_MASK | LMEM_PSCCR_INVW1_MASK | LMEM_PSCCR_GO_MASK;
/* Wait until the cache command completes */
while ((LMEM->PSCCR & LMEM_PSCCR_GO_MASK) != 0U) {
}
/* As a precaution clear the bits to avoid inadvertently re-running this command. */
LMEM->PSCCR &= ~(LMEM_PSCCR_INVW0_MASK | LMEM_PSCCR_INVW1_MASK);
/* Now enable the system bus cache. */
LMEM->PSCCR |= LMEM_PSCCR_ENCACHE_MASK;
/* Enables the processor code bus to invalidate all lines in both ways.
and Initiate the processor code bus code cache command. */
LMEM->PCCCR |= LMEM_PCCCR_INVW0_MASK | LMEM_PCCCR_INVW1_MASK | LMEM_PCCCR_GO_MASK;
/* Wait until the cache command completes. */
while ((LMEM->PCCCR & LMEM_PCCCR_GO_MASK) != 0U) {
}
/* As a precaution clear the bits to avoid inadvertently re-running this command. */
LMEM->PCCCR &= ~(LMEM_PCCCR_INVW0_MASK | LMEM_PCCCR_INVW1_MASK);
/* Now enable the code bus cache. */
LMEM->PCCCR |= LMEM_PCCCR_ENCACHE_MASK;
}
#endif
#endif

25
managed_components/espressif__tinyusb/hw/bsp/imxrt/boards/mimxrt1170_evkb/board.mk Normal file
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@@ -0,0 +1,25 @@
MCU_VARIANT = MIMXRT1176
ifeq ($(M4), 1)
MCU_CORE = _cm4
JLINK_CORE = _M4
CPU_CORE = cortex-m4
LD_FILE ?= $(MCU_DIR)/gcc/$(MCU_VARIANT)xxxxx${MCU_CORE}_ram.ld
else
MCU_CORE = _cm7
JLINK_CORE = _M7
endif
CFLAGS += -DCPU_MIMXRT1176DVMAA$(MCU_CORE)
# For flash-jlink target
JLINK_DEVICE = MIMXRT1176xxxA$(JLINK_CORE)
# For flash-pyocd target
PYOCD_TARGET = mimxrt1170$(MCU_CORE)
BOARD_TUD_RHPORT = 0
BOARD_TUH_RHPORT = 1
# flash using pyocd
flash: flash-pyocd

885
managed_components/espressif__tinyusb/hw/bsp/imxrt/boards/mimxrt1170_evkb/board/clock_config.c Normal file
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@@ -0,0 +1,885 @@
/*
* How to setup clock using clock driver functions:
*
* 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock.
*
* 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock.
*
* 3. Call CLOCK_SetRootClock() to configure corresponding module clock source and divider.
*
*/
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!GlobalInfo
product: Clocks v15.0
processor: MIMXRT1176xxxxx
package_id: MIMXRT1176DVMAA
mcu_data: ksdk2_0
processor_version: 24.12.10
board: MIMXRT1170-EVKB
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
#include "clock_config.h"
#include "fsl_iomuxc.h"
#include "fsl_dcdc.h"
#include "fsl_pmu.h"
#include "fsl_clock.h"
/*******************************************************************************
* Definitions
******************************************************************************/
/*******************************************************************************
* Variables
******************************************************************************/
/*******************************************************************************
************************ BOARD_InitBootClocks function ************************
******************************************************************************/
void BOARD_InitBootClocks(void)
{
BOARD_BootClockRUN();
}
#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1)
/* This function should not run from SDRAM since it will change SEMC configuration. */
AT_QUICKACCESS_SECTION_CODE(void UpdateSemcClock(void));
void UpdateSemcClock(void)
{
/* Enable self-refresh mode and update semc clock root to 200MHz. */
SEMC->IPCMD = 0xA55A000D;
while ((SEMC->INTR & 0x3) == 0)
;
SEMC->INTR = 0x3;
SEMC->DCCR = 0x0B;
/*
* Currently we are using SEMC parameter which fit both 166MHz and 200MHz, only
* need to change the SEMC clock root here. If customer is using their own DCD and
* want to switch from 166MHz to 200MHz, extra SEMC configuration might need to be
* adjusted here to fine tune the SDRAM performance
*/
CCM->CLOCK_ROOT[kCLOCK_Root_Semc].CONTROL = 0x602;
}
#endif
#endif
/*******************************************************************************
********************** Configuration BOARD_BootClockRUN ***********************
******************************************************************************/
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!Configuration
name: BOARD_BootClockRUN
called_from_default_init: true
outputs:
- {id: ACMP_CLK_ROOT.outFreq, value: 24 MHz}
- {id: ADC1_CLK_ROOT.outFreq, value: 24 MHz}
- {id: ADC2_CLK_ROOT.outFreq, value: 24 MHz}
- {id: ARM_PLL_CLK.outFreq, value: 996 MHz}
- {id: ASRC_CLK_ROOT.outFreq, value: 24 MHz}
- {id: AXI_CLK_ROOT.outFreq, value: 996 MHz}
- {id: BUS_CLK_ROOT.outFreq, value: 240 MHz}
- {id: BUS_LPSR_CLK_ROOT.outFreq, value: 160 MHz}
- {id: CAN1_CLK_ROOT.outFreq, value: 24 MHz}
- {id: CAN2_CLK_ROOT.outFreq, value: 24 MHz}
- {id: CAN3_CLK_ROOT.outFreq, value: 24 MHz}
- {id: CCM_CLKO1_CLK_ROOT.outFreq, value: 24 MHz}
- {id: CCM_CLKO2_CLK_ROOT.outFreq, value: 24 MHz}
- {id: CLK_1M.outFreq, value: 1 MHz}
- {id: CSI2_CLK_ROOT.outFreq, value: 24 MHz}
- {id: CSI2_ESC_CLK_ROOT.outFreq, value: 24 MHz}
- {id: CSI2_UI_CLK_ROOT.outFreq, value: 24 MHz}
- {id: CSI_CLK_ROOT.outFreq, value: 24 MHz}
- {id: CSSYS_CLK_ROOT.outFreq, value: 24 MHz}
- {id: CSTRACE_CLK_ROOT.outFreq, value: 132 MHz}
- {id: ELCDIF_CLK_ROOT.outFreq, value: 24 MHz}
- {id: EMV1_CLK_ROOT.outFreq, value: 24 MHz}
- {id: EMV2_CLK_ROOT.outFreq, value: 24 MHz}
- {id: ENET1_CLK_ROOT.outFreq, value: 24 MHz}
- {id: ENET2_CLK_ROOT.outFreq, value: 24 MHz}
- {id: ENET_1G_TX_CLK.outFreq, value: 24 MHz}
- {id: ENET_25M_CLK_ROOT.outFreq, value: 24 MHz}
- {id: ENET_QOS_CLK_ROOT.outFreq, value: 24 MHz}
- {id: ENET_TIMER1_CLK_ROOT.outFreq, value: 24 MHz}
- {id: ENET_TIMER2_CLK_ROOT.outFreq, value: 24 MHz}
- {id: ENET_TIMER3_CLK_ROOT.outFreq, value: 24 MHz}
- {id: FLEXIO1_CLK_ROOT.outFreq, value: 24 MHz}
- {id: FLEXIO2_CLK_ROOT.outFreq, value: 24 MHz}
- {id: FLEXSPI1_CLK_ROOT.outFreq, value: 24 MHz}
- {id: FLEXSPI2_CLK_ROOT.outFreq, value: 24 MHz}
- {id: GC355_CLK_ROOT.outFreq, value: 492.0000125 MHz}
- {id: GPT1_CLK_ROOT.outFreq, value: 24 MHz}
- {id: GPT1_ipg_clk_highfreq.outFreq, value: 24 MHz}
- {id: GPT2_CLK_ROOT.outFreq, value: 24 MHz}
- {id: GPT2_ipg_clk_highfreq.outFreq, value: 24 MHz}
- {id: GPT3_CLK_ROOT.outFreq, value: 24 MHz}
- {id: GPT3_ipg_clk_highfreq.outFreq, value: 24 MHz}
- {id: GPT4_CLK_ROOT.outFreq, value: 24 MHz}
- {id: GPT4_ipg_clk_highfreq.outFreq, value: 24 MHz}
- {id: GPT5_CLK_ROOT.outFreq, value: 24 MHz}
- {id: GPT5_ipg_clk_highfreq.outFreq, value: 24 MHz}
- {id: GPT6_CLK_ROOT.outFreq, value: 24 MHz}
- {id: GPT6_ipg_clk_highfreq.outFreq, value: 24 MHz}
- {id: LCDIFV2_CLK_ROOT.outFreq, value: 24 MHz}
- {id: LPI2C1_CLK_ROOT.outFreq, value: 24 MHz}
- {id: LPI2C2_CLK_ROOT.outFreq, value: 24 MHz}
- {id: LPI2C3_CLK_ROOT.outFreq, value: 24 MHz}
- {id: LPI2C4_CLK_ROOT.outFreq, value: 24 MHz}
- {id: LPI2C5_CLK_ROOT.outFreq, value: 24 MHz}
- {id: LPI2C6_CLK_ROOT.outFreq, value: 24 MHz}
- {id: LPSPI1_CLK_ROOT.outFreq, value: 24 MHz}
- {id: LPSPI2_CLK_ROOT.outFreq, value: 24 MHz}
- {id: LPSPI3_CLK_ROOT.outFreq, value: 24 MHz}
- {id: LPSPI4_CLK_ROOT.outFreq, value: 24 MHz}
- {id: LPSPI5_CLK_ROOT.outFreq, value: 24 MHz}
- {id: LPSPI6_CLK_ROOT.outFreq, value: 24 MHz}
- {id: LPUART10_CLK_ROOT.outFreq, value: 24 MHz}
- {id: LPUART11_CLK_ROOT.outFreq, value: 24 MHz}
- {id: LPUART12_CLK_ROOT.outFreq, value: 24 MHz}
- {id: LPUART1_CLK_ROOT.outFreq, value: 24 MHz}
- {id: LPUART2_CLK_ROOT.outFreq, value: 24 MHz}
- {id: LPUART3_CLK_ROOT.outFreq, value: 24 MHz}
- {id: LPUART4_CLK_ROOT.outFreq, value: 24 MHz}
- {id: LPUART5_CLK_ROOT.outFreq, value: 24 MHz}
- {id: LPUART6_CLK_ROOT.outFreq, value: 24 MHz}
- {id: LPUART7_CLK_ROOT.outFreq, value: 24 MHz}
- {id: LPUART8_CLK_ROOT.outFreq, value: 24 MHz}
- {id: LPUART9_CLK_ROOT.outFreq, value: 24 MHz}
- {id: M4_CLK_ROOT.outFreq, value: 4320/11 MHz}
- {id: M4_SYSTICK_CLK_ROOT.outFreq, value: 24 MHz}
- {id: M7_CLK_ROOT.outFreq, value: 996 MHz}
- {id: M7_SYSTICK_CLK_ROOT.outFreq, value: 100 kHz}
- {id: MIC_CLK_ROOT.outFreq, value: 24 MHz}
- {id: MIPI_DSI_TX_CLK_ESC_ROOT.outFreq, value: 24 MHz}
- {id: MIPI_ESC_CLK_ROOT.outFreq, value: 24 MHz}
- {id: MIPI_REF_CLK_ROOT.outFreq, value: 24 MHz}
- {id: MQS_CLK_ROOT.outFreq, value: 24 MHz}
- {id: MQS_MCLK.outFreq, value: 24 MHz}
- {id: OSC_24M.outFreq, value: 24 MHz}
- {id: OSC_32K.outFreq, value: 32.768 kHz}
- {id: OSC_RC_16M.outFreq, value: 16 MHz}
- {id: OSC_RC_400M.outFreq, value: 400 MHz}
- {id: OSC_RC_48M.outFreq, value: 48 MHz}
- {id: OSC_RC_48M_DIV2.outFreq, value: 24 MHz}
- {id: PLL_VIDEO_CLK.outFreq, value: 984.000025 MHz}
- {id: SAI1_CLK_ROOT.outFreq, value: 24 MHz}
- {id: SAI1_MCLK1.outFreq, value: 24 MHz}
- {id: SAI1_MCLK3.outFreq, value: 24 MHz}
- {id: SAI2_CLK_ROOT.outFreq, value: 24 MHz}
- {id: SAI2_MCLK1.outFreq, value: 24 MHz}
- {id: SAI2_MCLK3.outFreq, value: 24 MHz}
- {id: SAI3_CLK_ROOT.outFreq, value: 24 MHz}
- {id: SAI3_MCLK1.outFreq, value: 24 MHz}
- {id: SAI3_MCLK3.outFreq, value: 24 MHz}
- {id: SAI4_CLK_ROOT.outFreq, value: 24 MHz}
- {id: SAI4_MCLK1.outFreq, value: 24 MHz}
- {id: SEMC_CLK_ROOT.outFreq, value: 198 MHz}
- {id: SPDIF_CLK_ROOT.outFreq, value: 24 MHz}
- {id: SYS_PLL2_CLK.outFreq, value: 528 MHz}
- {id: SYS_PLL2_PFD0_CLK.outFreq, value: 352 MHz}
- {id: SYS_PLL2_PFD1_CLK.outFreq, value: 594 MHz}
- {id: SYS_PLL2_PFD2_CLK.outFreq, value: 396 MHz}
- {id: SYS_PLL2_PFD3_CLK.outFreq, value: 297 MHz}
- {id: SYS_PLL3_CLK.outFreq, value: 480 MHz}
- {id: SYS_PLL3_DIV2_CLK.outFreq, value: 240 MHz}
- {id: SYS_PLL3_PFD0_CLK.outFreq, value: 8640/13 MHz}
- {id: SYS_PLL3_PFD1_CLK.outFreq, value: 8640/17 MHz}
- {id: SYS_PLL3_PFD2_CLK.outFreq, value: 270 MHz}
- {id: SYS_PLL3_PFD3_CLK.outFreq, value: 4320/11 MHz}
- {id: USDHC1_CLK_ROOT.outFreq, value: 24 MHz}
- {id: USDHC2_CLK_ROOT.outFreq, value: 24 MHz}
settings:
- {id: CoreBusClockRootsInitializationConfig, value: selectedCore}
- {id: SOCDomainVoltage, value: OD}
- {id: ANADIG_OSC_OSC_24M_CTRL_LP_EN_CFG, value: Low}
- {id: ANADIG_OSC_OSC_24M_CTRL_OSC_EN_CFG, value: Enabled}
- {id: ANADIG_PLL.PLL_AUDIO_BYPASS.sel, value: ANADIG_OSC.OSC_24M}
- {id: ANADIG_PLL.PLL_VIDEO.denom, value: '960000'}
- {id: ANADIG_PLL.PLL_VIDEO.div, value: '41'}
- {id: ANADIG_PLL.PLL_VIDEO.num, value: '1'}
- {id: ANADIG_PLL.SYS_PLL1_BYPASS.sel, value: ANADIG_OSC.OSC_24M}
- {id: ANADIG_PLL.SYS_PLL2.denom, value: '268435455'}
- {id: ANADIG_PLL.SYS_PLL2.div, value: '22'}
- {id: ANADIG_PLL.SYS_PLL2.num, value: '0'}
- {id: ANADIG_PLL.SYS_PLL2_SS_DIV.scale, value: '268435455'}
- {id: ANADIG_PLL.SYS_PLL3_PFD3_DIV.scale, value: '22', locked: true}
- {id: ANADIG_PLL.SYS_PLL3_PFD3_MUL.scale, value: '18', locked: true}
- {id: ANADIG_PLL_ARM_PLL_CTRL_POWERUP_CFG, value: Enabled}
- {id: ANADIG_PLL_PLL_AUDIO_CTRL_GATE_CFG, value: Disabled}
- {id: ANADIG_PLL_PLL_VIDEO_CTRL0_POWERUP_CFG, value: Enabled}
- {id: ANADIG_PLL_SYS_PLL1_CTRL0_POWERUP_CFG, value: Disabled}
- {id: ANADIG_PLL_SYS_PLL1_CTRL_GATE_CFG, value: Disabled}
- {id: ANADIG_PLL_SYS_PLL2_CTRL_POWERUP_CFG, value: Enabled}
- {id: ANADIG_PLL_SYS_PLL3_CTRL_POWERUP_CFG, value: Enabled}
- {id: ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_CFG, value: Enabled}
- {id: CCM.CLOCK_ROOT0.MUX.sel, value: ANADIG_PLL.ARM_PLL_CLK}
- {id: CCM.CLOCK_ROOT1.MUX.sel, value: ANADIG_PLL.SYS_PLL3_PFD3_CLK}
- {id: CCM.CLOCK_ROOT2.DIV.scale, value: '2'}
- {id: CCM.CLOCK_ROOT2.MUX.sel, value: ANADIG_PLL.SYS_PLL3_CLK}
- {id: CCM.CLOCK_ROOT25.DIV.scale, value: '22'}
- {id: CCM.CLOCK_ROOT25.MUX.sel, value: ANADIG_PLL.SYS_PLL2_CLK}
- {id: CCM.CLOCK_ROOT26.DIV.scale, value: '22'}
- {id: CCM.CLOCK_ROOT26.MUX.sel, value: ANADIG_PLL.SYS_PLL2_CLK}
- {id: CCM.CLOCK_ROOT3.DIV.scale, value: '3'}
- {id: CCM.CLOCK_ROOT3.MUX.sel, value: ANADIG_PLL.SYS_PLL3_CLK}
- {id: CCM.CLOCK_ROOT4.DIV.scale, value: '3'}
- {id: CCM.CLOCK_ROOT4.MUX.sel, value: ANADIG_PLL.SYS_PLL2_PFD1_CLK}
- {id: CCM.CLOCK_ROOT6.DIV.scale, value: '4'}
- {id: CCM.CLOCK_ROOT6.MUX.sel, value: ANADIG_PLL.SYS_PLL2_CLK}
- {id: CCM.CLOCK_ROOT68.DIV.scale, value: '2'}
- {id: CCM.CLOCK_ROOT68.MUX.sel, value: ANADIG_PLL.PLL_VIDEO_CLK}
- {id: CCM.CLOCK_ROOT8.DIV.scale, value: '240'}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/*******************************************************************************
* Variables for BOARD_BootClockRUN configuration
******************************************************************************/
#ifndef SKIP_POWER_ADJUSTMENT
#if __CORTEX_M == 7
#define BYPASS_LDO_LPSR 1
#define SKIP_LDO_ADJUSTMENT 1
#elif __CORTEX_M == 4
#define SKIP_DCDC_ADJUSTMENT 1
#define SKIP_FBB_ENABLE 1
#endif
#endif
const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN =
{
.postDivider = kCLOCK_PllPostDiv2, /* Post divider, 0 - DIV by 2, 1 - DIV by 4, 2 - DIV by 8, 3 - DIV by 1 */
.loopDivider = 166, /* PLL Loop divider, Fout = Fin * ( loopDivider / ( 2 * postDivider ) ) */
};
const clock_sys_pll2_config_t sysPll2Config_BOARD_BootClockRUN =
{
.mfd = 268435455, /* Denominator of spread spectrum */
.ss = NULL, /* Spread spectrum parameter */
.ssEnable = false, /* Enable spread spectrum or not */
};
const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN =
{
.loopDivider = 41, /* PLL Loop divider, valid range for DIV_SELECT divider value: 27 ~ 54. */
.postDivider = 0, /* Divider after PLL, should only be 1, 2, 4, 8, 16, 32 */
.numerator = 1, /* 30 bit numerator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
.denominator = 960000, /* 30 bit denominator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
.ss = NULL, /* Spread spectrum parameter */
.ssEnable = false, /* Enable spread spectrum or not */
};
/*******************************************************************************
* Code for BOARD_BootClockRUN configuration
******************************************************************************/
void BOARD_BootClockRUN(void)
{
clock_root_config_t rootCfg = {0};
#if !defined(SKIP_DCDC_CONFIGURATION) || (!SKIP_DCDC_CONFIGURATION)
/* Set DCDC to DCM mode to improve the efficiency for light loading in run mode and transient performance with a big loading step. */
DCDC_BootIntoDCM(DCDC);
#if !defined(SKIP_DCDC_ADJUSTMENT) || (!SKIP_DCDC_ADJUSTMENT)
if((OCOTP->FUSEN[16].FUSE == 0x57AC5969U) && ((OCOTP->FUSEN[17].FUSE & 0xFFU) == 0x0BU))
{
DCDC_SetVDD1P0BuckModeTargetVoltage(DCDC, kDCDC_1P0BuckTarget1P15V);
}
else
{
/* Set 1.125V for production samples to align with data sheet requirement */
DCDC_SetVDD1P0BuckModeTargetVoltage(DCDC, kDCDC_1P0BuckTarget1P125V);
}
#endif /* SKIP_DCDC_ADJUSTMENT */
#endif /* SKIP_DCDC_CONFIGURATION */
#if !defined(SKIP_FBB_ENABLE) || (!SKIP_FBB_ENABLE)
/* Check if FBB need to be enabled in OverDrive(OD) mode */
if(((OCOTP->FUSEN[7].FUSE & 0x10U) >> 4U) != 1)
{
PMU_EnableBodyBias(ANADIG_PMU, kPMU_FBB_CM7, true);
}
else
{
PMU_EnableBodyBias(ANADIG_PMU, kPMU_FBB_CM7, false);
}
#endif
#if defined(BYPASS_LDO_LPSR) && BYPASS_LDO_LPSR
PMU_StaticEnableLpsrAnaLdoBypassMode(ANADIG_LDO_SNVS, true);
PMU_StaticEnableLpsrDigLdoBypassMode(ANADIG_LDO_SNVS, true);
#endif
#if !defined(SKIP_LDO_ADJUSTMENT) || (!SKIP_LDO_ADJUSTMENT)
pmu_static_lpsr_ana_ldo_config_t lpsrAnaConfig;
pmu_static_lpsr_dig_config_t lpsrDigConfig;
if((ANADIG_LDO_SNVS->PMU_LDO_LPSR_ANA & ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BYPASS_MODE_EN_MASK) == 0UL)
{
PMU_StaticGetLpsrAnaLdoDefaultConfig(&lpsrAnaConfig);
PMU_StaticLpsrAnaLdoInit(ANADIG_LDO_SNVS, &lpsrAnaConfig);
}
if((ANADIG_LDO_SNVS->PMU_LDO_LPSR_DIG & ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_BYPASS_MODE_MASK) == 0UL)
{
PMU_StaticGetLpsrDigLdoDefaultConfig(&lpsrDigConfig);
lpsrDigConfig.targetVoltage = kPMU_LpsrDigTargetStableVoltage1P117V;
PMU_StaticLpsrDigLdoInit(ANADIG_LDO_SNVS, &lpsrDigConfig);
}
#endif
/* Config CLK_1M */
CLOCK_OSC_Set1MHzOutputBehavior(kCLOCK_1MHzOutEnableFreeRunning1Mhz);
/* Init OSC RC 16M */
ANADIG_OSC->OSC_16M_CTRL |= ANADIG_OSC_OSC_16M_CTRL_EN_IRC4M16M_MASK;
/* Init OSC RC 400M */
CLOCK_OSC_EnableOscRc400M();
/* Init OSC RC 48M */
CLOCK_OSC_EnableOsc48M(true);
CLOCK_OSC_EnableOsc48MDiv2(true);
/* Config OSC 24M */
ANADIG_OSC->OSC_24M_CTRL |= ANADIG_OSC_OSC_24M_CTRL_OSC_EN(1) | ANADIG_OSC_OSC_24M_CTRL_BYPASS_EN(0) | ANADIG_OSC_OSC_24M_CTRL_BYPASS_CLK(0) | ANADIG_OSC_OSC_24M_CTRL_LP_EN(1) | ANADIG_OSC_OSC_24M_CTRL_OSC_24M_GATE(0);
/* Wait for 24M OSC to be stable. */
while (ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_MASK !=
(ANADIG_OSC->OSC_24M_CTRL & ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_MASK))
{
}
/* Switch core M7 clock root to OscRC48MDiv2 first */
#if __CORTEX_M == 7
rootCfg.mux = kCLOCK_M7_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_M7, &rootCfg);
#endif
/* Switch core M7 systick clock root to OscRC48MDiv2 first */
#if __CORTEX_M == 7
rootCfg.mux = kCLOCK_M7_SYSTICK_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_M7_Systick, &rootCfg);
#endif
/* Switch core M4 clock root to OscRC48MDiv2 first */
#if __CORTEX_M == 4
rootCfg.mux = kCLOCK_M4_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_M4, &rootCfg);
#endif
/* Switch the Bus_Lpsr clock root to OscRC48MDiv2 first */
#if __CORTEX_M == 4
rootCfg.mux = kCLOCK_BUS_LPSR_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Bus_Lpsr, &rootCfg);
#endif
/*
* if DCD is used, please make sure the clock source of SEMC is not changed in the following PLL/PFD configuration code.
*/
/* Init Arm Pll. */
CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN);
/* Bypass Sys Pll1. */
CLOCK_SetPllBypass(kCLOCK_PllSys1, true);
/* DeInit Sys Pll1. */
CLOCK_DeinitSysPll1();
/* Init Sys Pll2. */
CLOCK_InitSysPll2(&sysPll2Config_BOARD_BootClockRUN);
/* Init System Pll2 pfd0. */
CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd0, 27);
/* Init System Pll2 pfd1. */
CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd1, 16);
/* Init System Pll2 pfd2. */
CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd2, 24);
/* Init System Pll2 pfd3. */
CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd3, 32);
/* Init Sys Pll3. */
CLOCK_InitSysPll3();
/* Init System Pll3 pfd0. */
CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd0, 13);
/* Init System Pll3 pfd1. */
CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd1, 17);
/* Init System Pll3 pfd2. */
CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd2, 32);
/* Init System Pll3 pfd3. */
CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd3, 22);
/* Bypass Audio Pll. */
CLOCK_SetPllBypass(kCLOCK_PllAudio, true);
/* DeInit Audio Pll. */
CLOCK_DeinitAudioPll();
/* Init Video Pll. */
CLOCK_InitVideoPll(&videoPllConfig_BOARD_BootClockRUN);
/* Module clock root configurations. */
/* Configure M7 using ARM_PLL_CLK */
#if __CORTEX_M == 7
rootCfg.mux = kCLOCK_M7_ClockRoot_MuxArmPllOut;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_M7, &rootCfg);
#endif
/* Configure M4 using SYS_PLL3_PFD3_CLK */
#if __CORTEX_M == 4
rootCfg.mux = kCLOCK_M4_ClockRoot_MuxSysPll3Pfd3;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_M4, &rootCfg);
#endif
/* Configure BUS using SYS_PLL3_CLK */
rootCfg.mux = kCLOCK_BUS_ClockRoot_MuxSysPll3Out;
rootCfg.div = 2;
CLOCK_SetRootClock(kCLOCK_Root_Bus, &rootCfg);
/* Configure BUS_LPSR using SYS_PLL3_CLK */
rootCfg.mux = kCLOCK_BUS_LPSR_ClockRoot_MuxSysPll3Out;
rootCfg.div = 3;
CLOCK_SetRootClock(kCLOCK_Root_Bus_Lpsr, &rootCfg);
/* Configure SEMC using SYS_PLL2_PFD1_CLK */
#ifndef SKIP_SEMC_INIT
rootCfg.mux = kCLOCK_SEMC_ClockRoot_MuxSysPll2Pfd1;
rootCfg.div = 3;
CLOCK_SetRootClock(kCLOCK_Root_Semc, &rootCfg);
#endif
#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1)
UpdateSemcClock();
#endif
#endif
/* Configure CSSYS using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_CSSYS_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Cssys, &rootCfg);
/* Configure CSTRACE using SYS_PLL2_CLK */
rootCfg.mux = kCLOCK_CSTRACE_ClockRoot_MuxSysPll2Out;
rootCfg.div = 4;
CLOCK_SetRootClock(kCLOCK_Root_Cstrace, &rootCfg);
/* Configure M4_SYSTICK using OSC_RC_48M_DIV2 */
#if __CORTEX_M == 4
rootCfg.mux = kCLOCK_M4_SYSTICK_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_M4_Systick, &rootCfg);
#endif
/* Configure M7_SYSTICK using OSC_RC_48M_DIV2 */
#if __CORTEX_M == 7
rootCfg.mux = kCLOCK_M7_SYSTICK_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 240;
CLOCK_SetRootClock(kCLOCK_Root_M7_Systick, &rootCfg);
#endif
/* Configure ADC1 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_ADC1_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Adc1, &rootCfg);
/* Configure ADC2 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_ADC2_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Adc2, &rootCfg);
/* Configure ACMP using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_ACMP_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Acmp, &rootCfg);
/* Configure FLEXIO1 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_FLEXIO1_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Flexio1, &rootCfg);
/* Configure FLEXIO2 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_FLEXIO2_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Flexio2, &rootCfg);
/* Configure GPT1 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_GPT1_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Gpt1, &rootCfg);
/* Configure GPT2 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_GPT2_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Gpt2, &rootCfg);
/* Configure GPT3 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_GPT3_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Gpt3, &rootCfg);
/* Configure GPT4 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_GPT4_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Gpt4, &rootCfg);
/* Configure GPT5 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_GPT5_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Gpt5, &rootCfg);
/* Configure GPT6 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_GPT6_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Gpt6, &rootCfg);
/* Configure FLEXSPI1 using OSC_RC_48M_DIV2 */
#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1) || defined(FLEXSPI_IN_USE))
rootCfg.mux = kCLOCK_FLEXSPI1_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Flexspi1, &rootCfg);
#endif
/* Configure FLEXSPI2 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_FLEXSPI2_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Flexspi2, &rootCfg);
/* Configure CAN1 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_CAN1_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Can1, &rootCfg);
/* Configure CAN2 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_CAN2_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Can2, &rootCfg);
/* Configure CAN3 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_CAN3_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Can3, &rootCfg);
/* Configure LPUART1 using SYS_PLL2_CLK */
rootCfg.mux = kCLOCK_LPUART1_ClockRoot_MuxSysPll2Out;
rootCfg.div = 22;
CLOCK_SetRootClock(kCLOCK_Root_Lpuart1, &rootCfg);
/* Configure LPUART2 using SYS_PLL2_CLK */
rootCfg.mux = kCLOCK_LPUART2_ClockRoot_MuxSysPll2Out;
rootCfg.div = 22;
CLOCK_SetRootClock(kCLOCK_Root_Lpuart2, &rootCfg);
/* Configure LPUART3 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_LPUART3_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Lpuart3, &rootCfg);
/* Configure LPUART4 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_LPUART4_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Lpuart4, &rootCfg);
/* Configure LPUART5 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_LPUART5_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Lpuart5, &rootCfg);
/* Configure LPUART6 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_LPUART6_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Lpuart6, &rootCfg);
/* Configure LPUART7 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_LPUART7_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Lpuart7, &rootCfg);
/* Configure LPUART8 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_LPUART8_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Lpuart8, &rootCfg);
/* Configure LPUART9 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_LPUART9_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Lpuart9, &rootCfg);
/* Configure LPUART10 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_LPUART10_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Lpuart10, &rootCfg);
/* Configure LPUART11 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_LPUART11_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Lpuart11, &rootCfg);
/* Configure LPUART12 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_LPUART12_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Lpuart12, &rootCfg);
/* Configure LPI2C1 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_LPI2C1_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Lpi2c1, &rootCfg);
/* Configure LPI2C2 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_LPI2C2_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Lpi2c2, &rootCfg);
/* Configure LPI2C3 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_LPI2C3_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Lpi2c3, &rootCfg);
/* Configure LPI2C4 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_LPI2C4_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Lpi2c4, &rootCfg);
/* Configure LPI2C5 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_LPI2C5_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Lpi2c5, &rootCfg);
/* Configure LPI2C6 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_LPI2C6_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Lpi2c6, &rootCfg);
/* Configure LPSPI1 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_LPSPI1_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Lpspi1, &rootCfg);
/* Configure LPSPI2 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_LPSPI2_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Lpspi2, &rootCfg);
/* Configure LPSPI3 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_LPSPI3_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Lpspi3, &rootCfg);
/* Configure LPSPI4 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_LPSPI4_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Lpspi4, &rootCfg);
/* Configure LPSPI5 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_LPSPI5_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Lpspi5, &rootCfg);
/* Configure LPSPI6 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_LPSPI6_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Lpspi6, &rootCfg);
/* Configure EMV1 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_EMV1_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Emv1, &rootCfg);
/* Configure EMV2 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_EMV2_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Emv2, &rootCfg);
/* Configure ENET1 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_ENET1_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Enet1, &rootCfg);
/* Configure ENET2 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_ENET2_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Enet2, &rootCfg);
/* Configure ENET_QOS using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_ENET_QOS_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Enet_Qos, &rootCfg);
/* Configure ENET_25M using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_ENET_25M_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Enet_25m, &rootCfg);
/* Configure ENET_TIMER1 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_ENET_TIMER1_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Enet_Timer1, &rootCfg);
/* Configure ENET_TIMER2 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_ENET_TIMER2_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Enet_Timer2, &rootCfg);
/* Configure ENET_TIMER3 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_ENET_TIMER3_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Enet_Timer3, &rootCfg);
/* Configure USDHC1 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_USDHC1_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Usdhc1, &rootCfg);
/* Configure USDHC2 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_USDHC2_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Usdhc2, &rootCfg);
/* Configure ASRC using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_ASRC_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Asrc, &rootCfg);
/* Configure MQS using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_MQS_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Mqs, &rootCfg);
/* Configure MIC using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_MIC_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Mic, &rootCfg);
/* Configure SPDIF using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_SPDIF_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Spdif, &rootCfg);
/* Configure SAI1 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_SAI1_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Sai1, &rootCfg);
/* Configure SAI2 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_SAI2_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Sai2, &rootCfg);
/* Configure SAI3 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_SAI3_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Sai3, &rootCfg);
/* Configure SAI4 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_SAI4_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Sai4, &rootCfg);
/* Configure GC355 using PLL_VIDEO_CLK */
rootCfg.mux = kCLOCK_GC355_ClockRoot_MuxVideoPllOut;
rootCfg.div = 2;
CLOCK_SetRootClock(kCLOCK_Root_Gc355, &rootCfg);
/* Configure LCDIF using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_LCDIF_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Lcdif, &rootCfg);
/* Configure LCDIFV2 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_LCDIFV2_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Lcdifv2, &rootCfg);
/* Configure MIPI_REF using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_MIPI_REF_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Mipi_Ref, &rootCfg);
/* Configure MIPI_ESC using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_MIPI_ESC_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Mipi_Esc, &rootCfg);
/* Configure CSI2 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_CSI2_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Csi2, &rootCfg);
/* Configure CSI2_ESC using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_CSI2_ESC_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Csi2_Esc, &rootCfg);
/* Configure CSI2_UI using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_CSI2_UI_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Csi2_Ui, &rootCfg);
/* Configure CSI using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_CSI_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Csi, &rootCfg);
/* Configure CKO1 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_CKO1_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Cko1, &rootCfg);
/* Configure CKO2 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_CKO2_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Cko2, &rootCfg);
/* Set SAI1 MCLK1 clock source. */
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0);
/* Set SAI1 MCLK2 clock source. */
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 3);
/* Set SAI1 MCLK3 clock source. */
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0);
/* Set SAI2 MCLK3 clock source. */
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0);
/* Set SAI3 MCLK3 clock source. */
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
/* Set MQS configuration. */
IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0);
/* Set ENET Ref clock source. */
IOMUXC_GPR->GPR4 &= ~IOMUXC_GPR_GPR4_ENET_REF_CLK_DIR_MASK;
/* Set ENET_1G Tx clock source. */
IOMUXC_GPR->GPR5 = ((IOMUXC_GPR->GPR5 & ~IOMUXC_GPR_GPR5_ENET1G_TX_CLK_SEL_MASK) | IOMUXC_GPR_GPR5_ENET1G_RGMII_EN_MASK);
/* Set ENET_1G Ref clock source. */
IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_ENET1G_REF_CLK_DIR_MASK;
/* Set ENET_QOS Tx clock source. */
IOMUXC_GPR->GPR6 &= ~IOMUXC_GPR_GPR6_ENET_QOS_RGMII_EN_MASK;
/* Set ENET_QOS Ref clock source. */
IOMUXC_GPR->GPR6 &= ~IOMUXC_GPR_GPR6_ENET_QOS_REF_CLK_DIR_MASK;
/* Set GPT1 High frequency reference clock source. */
IOMUXC_GPR->GPR22 &= ~IOMUXC_GPR_GPR22_REF_1M_CLK_GPT1_MASK;
/* Set GPT2 High frequency reference clock source. */
IOMUXC_GPR->GPR23 &= ~IOMUXC_GPR_GPR23_REF_1M_CLK_GPT2_MASK;
/* Set GPT3 High frequency reference clock source. */
IOMUXC_GPR->GPR24 &= ~IOMUXC_GPR_GPR24_REF_1M_CLK_GPT3_MASK;
/* Set GPT4 High frequency reference clock source. */
IOMUXC_GPR->GPR25 &= ~IOMUXC_GPR_GPR25_REF_1M_CLK_GPT4_MASK;
/* Set GPT5 High frequency reference clock source. */
IOMUXC_GPR->GPR26 &= ~IOMUXC_GPR_GPR26_REF_1M_CLK_GPT5_MASK;
/* Set GPT6 High frequency reference clock source. */
IOMUXC_GPR->GPR27 &= ~IOMUXC_GPR_GPR27_REF_1M_CLK_GPT6_MASK;
#if __CORTEX_M == 7
SystemCoreClock = CLOCK_GetRootClockFreq(kCLOCK_Root_M7);
#else
SystemCoreClock = CLOCK_GetRootClockFreq(kCLOCK_Root_M4);
#endif
}

202
managed_components/espressif__tinyusb/hw/bsp/imxrt/boards/mimxrt1170_evkb/board/clock_config.h Normal file
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#ifndef _CLOCK_CONFIG_H_
#define _CLOCK_CONFIG_H_
#include "fsl_common.h"
/*******************************************************************************
* Definitions
******************************************************************************/
#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */
#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */
/*******************************************************************************
************************ BOARD_InitBootClocks function ************************
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/
/*!
* @brief This function executes default configuration of clocks.
*
*/
void BOARD_InitBootClocks(void);
#if defined(__cplusplus)
}
#endif /* __cplusplus*/
/*******************************************************************************
********************** Configuration BOARD_BootClockRUN ***********************
******************************************************************************/
/*******************************************************************************
* Definitions for BOARD_BootClockRUN configuration
******************************************************************************/
#if __CORTEX_M == 7
#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 996000000UL /*!< CM7 Core clock frequency: 996000000Hz */
#else
#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 392727272UL /*!< CM4 Core clock frequency: 392727272Hz */
#endif
/* Clock outputs (values are in Hz): */
#define BOARD_BOOTCLOCKRUN_ACMP_CLK_ROOT 24000000UL /* Clock consumers of ACMP_CLK_ROOT output : CMP1, CMP2, CMP3, CMP4 */
#define BOARD_BOOTCLOCKRUN_ADC1_CLK_ROOT 24000000UL /* Clock consumers of ADC1_CLK_ROOT output : LPADC1 */
#define BOARD_BOOTCLOCKRUN_ADC2_CLK_ROOT 24000000UL /* Clock consumers of ADC2_CLK_ROOT output : LPADC2 */
#define BOARD_BOOTCLOCKRUN_ARM_PLL_CLK 996000000UL /* Clock consumers of ARM_PLL_CLK output : N/A */
#define BOARD_BOOTCLOCKRUN_ASRC_CLK_ROOT 24000000UL /* Clock consumers of ASRC_CLK_ROOT output : ASRC */
#define BOARD_BOOTCLOCKRUN_AXI_CLK_ROOT 996000000UL /* Clock consumers of AXI_CLK_ROOT output : FLEXRAM */
#define BOARD_BOOTCLOCKRUN_BUS_CLK_ROOT 240000000UL /* Clock consumers of BUS_CLK_ROOT output : ADC_ETC, AOI1, AOI2, CAAM, CAN1, CAN2, CM7_GPIO2, CM7_GPIO3, CMP1, CMP2, CMP3, CMP4, CSI, DAC, DMA0, DMAMUX0, DSI_HOST, EMVSIM1, EMVSIM2, ENC1, ENC2, ENC3, ENC4, ENET, ENET_1G, ENET_QOS, EWM, FLEXIO1, FLEXIO2, FLEXSPI1, FLEXSPI2, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO6, IEE_APC, IEE__IEE_RT1170, IOMUXC, IOMUXC_GPR, KPP, LCDIF, LCDIFV2, LPADC1, LPADC2, LPI2C1, LPI2C2, LPI2C3, LPI2C4, LPSPI1, LPSPI2, LPSPI3, LPSPI4, LPUART1, LPUART10, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8, LPUART9, MECC1, MECC2, MIPI_CSI2RX, PIT1, PWM1, PWM2, PWM3, PWM4, PXP, RTWDOG3, SAI1, SAI2, SAI3, SPDIF, TMR1, TMR2, TMR3, TMR4, USBPHY1, USBPHY2, USB_OTG1, USB_OTG2, USDHC1, USDHC2, WDOG1, WDOG2, XBARA1, XBARB2, XBARB3, XECC_FLEXSPI1, XECC_FLEXSPI2, XECC_SEMC, XRDC2_D0, XRDC2_D1 */
#define BOARD_BOOTCLOCKRUN_BUS_LPSR_CLK_ROOT 160000000UL /* Clock consumers of BUS_LPSR_CLK_ROOT output : CAN3, GPIO10, GPIO11, GPIO12, GPIO7, GPIO8, GPIO9, IOMUXC_LPSR, LPI2C5, LPI2C6, LPSPI5, LPSPI6, LPUART11, LPUART12, MUA, MUB, PDM, PIT2, RDC, RTWDOG4, SAI4, SNVS, XRDC2_D0, XRDC2_D1 */
#define BOARD_BOOTCLOCKRUN_CAN1_CLK_ROOT 24000000UL /* Clock consumers of CAN1_CLK_ROOT output : CAN1 */
#define BOARD_BOOTCLOCKRUN_CAN2_CLK_ROOT 24000000UL /* Clock consumers of CAN2_CLK_ROOT output : CAN2 */
#define BOARD_BOOTCLOCKRUN_CAN3_CLK_ROOT 24000000UL /* Clock consumers of CAN3_CLK_ROOT output : CAN3 */
#define BOARD_BOOTCLOCKRUN_CCM_CLKO1_CLK_ROOT 24000000UL /* Clock consumers of CCM_CLKO1_CLK_ROOT output : N/A */
#define BOARD_BOOTCLOCKRUN_CCM_CLKO2_CLK_ROOT 24000000UL /* Clock consumers of CCM_CLKO2_CLK_ROOT output : N/A */
#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL /* Clock consumers of CLK_1M output : EWM, RTWDOG3, RTWDOG4 */
#define BOARD_BOOTCLOCKRUN_CSI2_CLK_ROOT 24000000UL /* Clock consumers of CSI2_CLK_ROOT output : MIPI_CSI2RX */
#define BOARD_BOOTCLOCKRUN_CSI2_ESC_CLK_ROOT 24000000UL /* Clock consumers of CSI2_ESC_CLK_ROOT output : MIPI_CSI2RX */
#define BOARD_BOOTCLOCKRUN_CSI2_UI_CLK_ROOT 24000000UL /* Clock consumers of CSI2_UI_CLK_ROOT output : MIPI_CSI2RX */
#define BOARD_BOOTCLOCKRUN_CSI_CLK_ROOT 24000000UL /* Clock consumers of CSI_CLK_ROOT output : N/A */
#define BOARD_BOOTCLOCKRUN_CSSYS_CLK_ROOT 24000000UL /* Clock consumers of CSSYS_CLK_ROOT output : ARM */
#define BOARD_BOOTCLOCKRUN_CSTRACE_CLK_ROOT 132000000UL /* Clock consumers of CSTRACE_CLK_ROOT output : ARM */
#define BOARD_BOOTCLOCKRUN_ELCDIF_CLK_ROOT 24000000UL /* Clock consumers of ELCDIF_CLK_ROOT output : LCDIF */
#define BOARD_BOOTCLOCKRUN_EMV1_CLK_ROOT 24000000UL /* Clock consumers of EMV1_CLK_ROOT output : EMVSIM1 */
#define BOARD_BOOTCLOCKRUN_EMV2_CLK_ROOT 24000000UL /* Clock consumers of EMV2_CLK_ROOT output : EMVSIM2 */
#define BOARD_BOOTCLOCKRUN_ENET1_CLK_ROOT 24000000UL /* Clock consumers of ENET1_CLK_ROOT output : N/A */
#define BOARD_BOOTCLOCKRUN_ENET2_CLK_ROOT 24000000UL /* Clock consumers of ENET2_CLK_ROOT output : N/A */
#define BOARD_BOOTCLOCKRUN_ENET_1G_REF_CLK 0UL /* Clock consumers of ENET_1G_REF_CLK output : ENET_1G */
#define BOARD_BOOTCLOCKRUN_ENET_1G_TX_CLK 24000000UL /* Clock consumers of ENET_1G_TX_CLK output : ENET_1G */
#define BOARD_BOOTCLOCKRUN_ENET_25M_CLK_ROOT 24000000UL /* Clock consumers of ENET_25M_CLK_ROOT output : N/A */
#define BOARD_BOOTCLOCKRUN_ENET_QOS_CLK_ROOT 24000000UL /* Clock consumers of ENET_QOS_CLK_ROOT output : N/A */
#define BOARD_BOOTCLOCKRUN_ENET_QOS_REF_CLK 0UL /* Clock consumers of ENET_QOS_REF_CLK output : ENET_QOS */
#define BOARD_BOOTCLOCKRUN_ENET_QOS_TX_CLK 0UL /* Clock consumers of ENET_QOS_TX_CLK output : ENET_QOS */
#define BOARD_BOOTCLOCKRUN_ENET_REF_CLK 0UL /* Clock consumers of ENET_REF_CLK output : ENET */
#define BOARD_BOOTCLOCKRUN_ENET_TIMER1_CLK_ROOT 24000000UL /* Clock consumers of ENET_TIMER1_CLK_ROOT output : ENET */
#define BOARD_BOOTCLOCKRUN_ENET_TIMER2_CLK_ROOT 24000000UL /* Clock consumers of ENET_TIMER2_CLK_ROOT output : ENET_1G */
#define BOARD_BOOTCLOCKRUN_ENET_TIMER3_CLK_ROOT 24000000UL /* Clock consumers of ENET_TIMER3_CLK_ROOT output : ENET_QOS */
#define BOARD_BOOTCLOCKRUN_ENET_TX_CLK 0UL /* Clock consumers of ENET_TX_CLK output : ENET */
#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 24000000UL /* Clock consumers of FLEXIO1_CLK_ROOT output : FLEXIO1 */
#define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT 24000000UL /* Clock consumers of FLEXIO2_CLK_ROOT output : FLEXIO2 */
#define BOARD_BOOTCLOCKRUN_FLEXSPI1_CLK_ROOT 24000000UL /* Clock consumers of FLEXSPI1_CLK_ROOT output : FLEXSPI1 */
#define BOARD_BOOTCLOCKRUN_FLEXSPI2_CLK_ROOT 24000000UL /* Clock consumers of FLEXSPI2_CLK_ROOT output : FLEXSPI2 */
#define BOARD_BOOTCLOCKRUN_GC355_CLK_ROOT 492000012UL /* Clock consumers of GC355_CLK_ROOT output : N/A */
#define BOARD_BOOTCLOCKRUN_GPT1_CLK_ROOT 24000000UL /* Clock consumers of GPT1_CLK_ROOT output : GPT1 */
#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 24000000UL /* Clock consumers of GPT1_ipg_clk_highfreq output : N/A */
#define BOARD_BOOTCLOCKRUN_GPT2_CLK_ROOT 24000000UL /* Clock consumers of GPT2_CLK_ROOT output : GPT2 */
#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 24000000UL /* Clock consumers of GPT2_ipg_clk_highfreq output : N/A */
#define BOARD_BOOTCLOCKRUN_GPT3_CLK_ROOT 24000000UL /* Clock consumers of GPT3_CLK_ROOT output : GPT3 */
#define BOARD_BOOTCLOCKRUN_GPT3_IPG_CLK_HIGHFREQ 24000000UL /* Clock consumers of GPT3_ipg_clk_highfreq output : N/A */
#define BOARD_BOOTCLOCKRUN_GPT4_CLK_ROOT 24000000UL /* Clock consumers of GPT4_CLK_ROOT output : GPT4 */
#define BOARD_BOOTCLOCKRUN_GPT4_IPG_CLK_HIGHFREQ 24000000UL /* Clock consumers of GPT4_ipg_clk_highfreq output : N/A */
#define BOARD_BOOTCLOCKRUN_GPT5_CLK_ROOT 24000000UL /* Clock consumers of GPT5_CLK_ROOT output : GPT5 */
#define BOARD_BOOTCLOCKRUN_GPT5_IPG_CLK_HIGHFREQ 24000000UL /* Clock consumers of GPT5_ipg_clk_highfreq output : N/A */
#define BOARD_BOOTCLOCKRUN_GPT6_CLK_ROOT 24000000UL /* Clock consumers of GPT6_CLK_ROOT output : GPT6 */
#define BOARD_BOOTCLOCKRUN_GPT6_IPG_CLK_HIGHFREQ 24000000UL /* Clock consumers of GPT6_ipg_clk_highfreq output : N/A */
#define BOARD_BOOTCLOCKRUN_LCDIFV2_CLK_ROOT 24000000UL /* Clock consumers of LCDIFV2_CLK_ROOT output : LCDIFV2 */
#define BOARD_BOOTCLOCKRUN_LPI2C1_CLK_ROOT 24000000UL /* Clock consumers of LPI2C1_CLK_ROOT output : LPI2C1 */
#define BOARD_BOOTCLOCKRUN_LPI2C2_CLK_ROOT 24000000UL /* Clock consumers of LPI2C2_CLK_ROOT output : LPI2C2 */
#define BOARD_BOOTCLOCKRUN_LPI2C3_CLK_ROOT 24000000UL /* Clock consumers of LPI2C3_CLK_ROOT output : LPI2C3 */
#define BOARD_BOOTCLOCKRUN_LPI2C4_CLK_ROOT 24000000UL /* Clock consumers of LPI2C4_CLK_ROOT output : LPI2C4 */
#define BOARD_BOOTCLOCKRUN_LPI2C5_CLK_ROOT 24000000UL /* Clock consumers of LPI2C5_CLK_ROOT output : LPI2C5 */
#define BOARD_BOOTCLOCKRUN_LPI2C6_CLK_ROOT 24000000UL /* Clock consumers of LPI2C6_CLK_ROOT output : LPI2C6 */
#define BOARD_BOOTCLOCKRUN_LPSPI1_CLK_ROOT 24000000UL /* Clock consumers of LPSPI1_CLK_ROOT output : LPSPI1 */
#define BOARD_BOOTCLOCKRUN_LPSPI2_CLK_ROOT 24000000UL /* Clock consumers of LPSPI2_CLK_ROOT output : LPSPI2 */
#define BOARD_BOOTCLOCKRUN_LPSPI3_CLK_ROOT 24000000UL /* Clock consumers of LPSPI3_CLK_ROOT output : LPSPI3 */
#define BOARD_BOOTCLOCKRUN_LPSPI4_CLK_ROOT 24000000UL /* Clock consumers of LPSPI4_CLK_ROOT output : LPSPI4 */
#define BOARD_BOOTCLOCKRUN_LPSPI5_CLK_ROOT 24000000UL /* Clock consumers of LPSPI5_CLK_ROOT output : LPSPI5 */
#define BOARD_BOOTCLOCKRUN_LPSPI6_CLK_ROOT 24000000UL /* Clock consumers of LPSPI6_CLK_ROOT output : LPSPI6 */
#define BOARD_BOOTCLOCKRUN_LPUART10_CLK_ROOT 24000000UL /* Clock consumers of LPUART10_CLK_ROOT output : LPUART10 */
#define BOARD_BOOTCLOCKRUN_LPUART11_CLK_ROOT 24000000UL /* Clock consumers of LPUART11_CLK_ROOT output : LPUART11 */
#define BOARD_BOOTCLOCKRUN_LPUART12_CLK_ROOT 24000000UL /* Clock consumers of LPUART12_CLK_ROOT output : LPUART12 */
#define BOARD_BOOTCLOCKRUN_LPUART1_CLK_ROOT 24000000UL /* Clock consumers of LPUART1_CLK_ROOT output : LPUART1 */
#define BOARD_BOOTCLOCKRUN_LPUART2_CLK_ROOT 24000000UL /* Clock consumers of LPUART2_CLK_ROOT output : LPUART2 */
#define BOARD_BOOTCLOCKRUN_LPUART3_CLK_ROOT 24000000UL /* Clock consumers of LPUART3_CLK_ROOT output : LPUART3 */
#define BOARD_BOOTCLOCKRUN_LPUART4_CLK_ROOT 24000000UL /* Clock consumers of LPUART4_CLK_ROOT output : LPUART4 */
#define BOARD_BOOTCLOCKRUN_LPUART5_CLK_ROOT 24000000UL /* Clock consumers of LPUART5_CLK_ROOT output : LPUART5 */
#define BOARD_BOOTCLOCKRUN_LPUART6_CLK_ROOT 24000000UL /* Clock consumers of LPUART6_CLK_ROOT output : LPUART6 */
#define BOARD_BOOTCLOCKRUN_LPUART7_CLK_ROOT 24000000UL /* Clock consumers of LPUART7_CLK_ROOT output : LPUART7 */
#define BOARD_BOOTCLOCKRUN_LPUART8_CLK_ROOT 24000000UL /* Clock consumers of LPUART8_CLK_ROOT output : LPUART8 */
#define BOARD_BOOTCLOCKRUN_LPUART9_CLK_ROOT 24000000UL /* Clock consumers of LPUART9_CLK_ROOT output : LPUART9 */
#define BOARD_BOOTCLOCKRUN_M4_CLK_ROOT 392727272UL /* Clock consumers of M4_CLK_ROOT output : ARM, DMA1, DMAMUX1, SSARC_HP, SSARC_LP, XRDC2_D0, XRDC2_D1 */
#define BOARD_BOOTCLOCKRUN_M4_SYSTICK_CLK_ROOT 24000000UL /* Clock consumers of M4_SYSTICK_CLK_ROOT output : N/A */
#define BOARD_BOOTCLOCKRUN_M7_CLK_ROOT 996000000UL /* Clock consumers of M7_CLK_ROOT output : ARM */
#define BOARD_BOOTCLOCKRUN_M7_SYSTICK_CLK_ROOT 100000UL /* Clock consumers of M7_SYSTICK_CLK_ROOT output : N/A */
#define BOARD_BOOTCLOCKRUN_MIC_CLK_ROOT 24000000UL /* Clock consumers of MIC_CLK_ROOT output : ASRC, PDM, SPDIF */
#define BOARD_BOOTCLOCKRUN_MIPI_DSI_TX_CLK_ESC_ROOT 24000000UL /* Clock consumers of MIPI_DSI_TX_CLK_ESC_ROOT output : N/A */
#define BOARD_BOOTCLOCKRUN_MIPI_ESC_CLK_ROOT 24000000UL /* Clock consumers of MIPI_ESC_CLK_ROOT output : DSI_HOST */
#define BOARD_BOOTCLOCKRUN_MIPI_REF_CLK_ROOT 24000000UL /* Clock consumers of MIPI_REF_CLK_ROOT output : DSI_HOST */
#define BOARD_BOOTCLOCKRUN_MQS_CLK_ROOT 24000000UL /* Clock consumers of MQS_CLK_ROOT output : ASRC */
#define BOARD_BOOTCLOCKRUN_MQS_MCLK 24000000UL /* Clock consumers of MQS_MCLK output : N/A */
#define BOARD_BOOTCLOCKRUN_OSC_24M 24000000UL /* Clock consumers of OSC_24M output : SPDIF, TMPSNS, USBPHY1, USBPHY2 */
#define BOARD_BOOTCLOCKRUN_OSC_32K 32768UL /* Clock consumers of OSC_32K output : GPIO13, RTWDOG3, RTWDOG4 */
#define BOARD_BOOTCLOCKRUN_OSC_RC_16M 16000000UL /* Clock consumers of OSC_RC_16M output : CCM, DCDC, EWM, GPT1, GPT2, GPT3, GPT4, GPT5, GPT6, SSARC_LP */
#define BOARD_BOOTCLOCKRUN_OSC_RC_400M 400000000UL /* Clock consumers of OSC_RC_400M output : N/A */
#define BOARD_BOOTCLOCKRUN_OSC_RC_48M 48000000UL /* Clock consumers of OSC_RC_48M output : N/A */
#define BOARD_BOOTCLOCKRUN_OSC_RC_48M_DIV2 24000000UL /* Clock consumers of OSC_RC_48M_DIV2 output : N/A */
#define BOARD_BOOTCLOCKRUN_PLL_AUDIO_CLK 0UL /* Clock consumers of PLL_AUDIO_CLK output : N/A */
#define BOARD_BOOTCLOCKRUN_PLL_AUDIO_SS_MODULATION 0UL /* Clock consumers of PLL_AUDIO_SS_MODULATION output : N/A */
#define BOARD_BOOTCLOCKRUN_PLL_AUDIO_SS_RANGE 0UL /* Clock consumers of PLL_AUDIO_SS_RANGE output : N/A */
#define BOARD_BOOTCLOCKRUN_PLL_VIDEO_CLK 984000025UL /* Clock consumers of PLL_VIDEO_CLK output : N/A */
#define BOARD_BOOTCLOCKRUN_PLL_VIDEO_SS_MODULATION 0UL /* Clock consumers of PLL_VIDEO_SS_MODULATION output : N/A */
#define BOARD_BOOTCLOCKRUN_PLL_VIDEO_SS_RANGE 0UL /* Clock consumers of PLL_VIDEO_SS_RANGE output : N/A */
#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 24000000UL /* Clock consumers of SAI1_CLK_ROOT output : SPDIF */
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 24000000UL /* Clock consumers of SAI1_MCLK1 output : SAI1 */
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 0UL /* Clock consumers of SAI1_MCLK2 output : SAI1 */
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 24000000UL /* Clock consumers of SAI1_MCLK3 output : SAI1 */
#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 24000000UL /* Clock consumers of SAI2_CLK_ROOT output : ASRC */
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 24000000UL /* Clock consumers of SAI2_MCLK1 output : SAI2 */
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL /* Clock consumers of SAI2_MCLK2 output : SAI2 */
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 24000000UL /* Clock consumers of SAI2_MCLK3 output : SAI2 */
#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 24000000UL /* Clock consumers of SAI3_CLK_ROOT output : ASRC, SPDIF */
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 24000000UL /* Clock consumers of SAI3_MCLK1 output : SAI3 */
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL /* Clock consumers of SAI3_MCLK2 output : SAI3 */
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 24000000UL /* Clock consumers of SAI3_MCLK3 output : SAI3 */
#define BOARD_BOOTCLOCKRUN_SAI4_CLK_ROOT 24000000UL /* Clock consumers of SAI4_CLK_ROOT output : ASRC, SPDIF */
#define BOARD_BOOTCLOCKRUN_SAI4_MCLK1 24000000UL /* Clock consumers of SAI4_MCLK1 output : SAI4 */
#define BOARD_BOOTCLOCKRUN_SAI4_MCLK2 0UL /* Clock consumers of SAI4_MCLK2 output : SAI4 */
#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 198000000UL /* Clock consumers of SEMC_CLK_ROOT output : SEMC, XECC_FLEXSPI1, XECC_FLEXSPI2, XECC_SEMC, XRDC2_D0, XRDC2_D1 */
#define BOARD_BOOTCLOCKRUN_SPDIF_CLK_ROOT 24000000UL /* Clock consumers of SPDIF_CLK_ROOT output : SPDIF */
#define BOARD_BOOTCLOCKRUN_SPDIF_EXTCLK_OUT 0UL /* Clock consumers of SPDIF_EXTCLK_OUT output : N/A */
#define BOARD_BOOTCLOCKRUN_SYS_PLL1_CLK 0UL /* Clock consumers of SYS_PLL1_CLK output : N/A */
#define BOARD_BOOTCLOCKRUN_SYS_PLL1_DIV2_CLK 0UL /* Clock consumers of SYS_PLL1_DIV2_CLK output : N/A */
#define BOARD_BOOTCLOCKRUN_SYS_PLL1_DIV5_CLK 0UL /* Clock consumers of SYS_PLL1_DIV5_CLK output : N/A */
#define BOARD_BOOTCLOCKRUN_SYS_PLL1_SS_MODULATION 0UL /* Clock consumers of SYS_PLL1_SS_MODULATION output : N/A */
#define BOARD_BOOTCLOCKRUN_SYS_PLL1_SS_RANGE 0UL /* Clock consumers of SYS_PLL1_SS_RANGE output : N/A */
#define BOARD_BOOTCLOCKRUN_SYS_PLL2_CLK 528000000UL /* Clock consumers of SYS_PLL2_CLK output : N/A */
#define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD0_CLK 352000000UL /* Clock consumers of SYS_PLL2_PFD0_CLK output : N/A */
#define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD1_CLK 594000000UL /* Clock consumers of SYS_PLL2_PFD1_CLK output : N/A */
#define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD2_CLK 396000000UL /* Clock consumers of SYS_PLL2_PFD2_CLK output : N/A */
#define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD3_CLK 297000000UL /* Clock consumers of SYS_PLL2_PFD3_CLK output : N/A */
#define BOARD_BOOTCLOCKRUN_SYS_PLL2_SS_MODULATION 0UL /* Clock consumers of SYS_PLL2_SS_MODULATION output : N/A */
#define BOARD_BOOTCLOCKRUN_SYS_PLL2_SS_RANGE 0UL /* Clock consumers of SYS_PLL2_SS_RANGE output : N/A */
#define BOARD_BOOTCLOCKRUN_SYS_PLL3_CLK 480000000UL /* Clock consumers of SYS_PLL3_CLK output : N/A */
#define BOARD_BOOTCLOCKRUN_SYS_PLL3_DIV2_CLK 240000000UL /* Clock consumers of SYS_PLL3_DIV2_CLK output : N/A */
#define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD0_CLK 664615384UL /* Clock consumers of SYS_PLL3_PFD0_CLK output : N/A */
#define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD1_CLK 508235294UL /* Clock consumers of SYS_PLL3_PFD1_CLK output : N/A */
#define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD2_CLK 270000000UL /* Clock consumers of SYS_PLL3_PFD2_CLK output : N/A */
#define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD3_CLK 392727272UL /* Clock consumers of SYS_PLL3_PFD3_CLK output : N/A */
#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 24000000UL /* Clock consumers of USDHC1_CLK_ROOT output : USDHC1 */
#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 24000000UL /* Clock consumers of USDHC2_CLK_ROOT output : USDHC2 */
/*******************************************************************************
* API for BOARD_BootClockRUN configuration
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/
/*!
* @brief This function executes configuration of clocks.
*
*/
void BOARD_BootClockRUN(void);
#if defined(__cplusplus)
}
#endif /* __cplusplus*/
#endif /* _CLOCK_CONFIG_H_ */

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managed_components/espressif__tinyusb/hw/bsp/imxrt/boards/mimxrt1170_evkb/board/pin_mux.c Normal file
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/***********************************************************************************************************************
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
**********************************************************************************************************************/
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!GlobalInfo
product: Pins v17.0
processor: MIMXRT1176xxxxx
package_id: MIMXRT1176DVMAA
mcu_data: ksdk2_0
processor_version: 24.12.10
board: MIMXRT1170-EVKB
external_user_signals: {}
pin_labels:
- {pin_num: M13, pin_signal: GPIO_AD_04, label: 'SIM1_PD/J44[C8]/USER_LED_CTL1/J9[8]/J25[7]', identifier: SIM1_PD;LED;USER_LED}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
#include "fsl_common.h"
#include "fsl_iomuxc.h"
#include "fsl_gpio.h"
#include "pin_mux.h"
/* FUNCTION ************************************************************************************************************
*
* Function Name : BOARD_InitBootPins
* Description : Calls initialization functions.
*
* END ****************************************************************************************************************/
void BOARD_InitBootPins(void) {
BOARD_InitPins();
BOARD_InitDEBUG_UARTPins();
}
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
BOARD_InitPins:
- options: {callFromInitBoot: 'true', coreID: cm7, enableClock: 'true'}
- pin_list:
- {pin_num: M13, peripheral: GPIO9, signal: 'gpio_io, 03', pin_signal: GPIO_AD_04, identifier: USER_LED, direction: OUTPUT, pull_up_down_config: Pull_Down, pull_keeper_select: Keeper}
- {pin_num: T8, peripheral: GPIO13, signal: 'gpio_io, 00', pin_signal: WAKEUP, direction: INPUT, pull_up_down_config: Pull_Up}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
/* FUNCTION ************************************************************************************************************
*
* Function Name : BOARD_InitPins, assigned for the Cortex-M7F core.
* Description : Configures pin routing and optionally pin electrical features.
*
* END ****************************************************************************************************************/
void BOARD_InitPins(void) {
CLOCK_EnableClock(kCLOCK_Iomuxc); /* LPCG on: LPCG is ON. */
/* GPIO configuration of USER_LED on GPIO_AD_04 (pin M13) */
gpio_pin_config_t USER_LED_config = {
.direction = kGPIO_DigitalOutput,
.outputLogic = 0U,
.interruptMode = kGPIO_NoIntmode
};
/* Initialize GPIO functionality on GPIO_AD_04 (pin M13) */
GPIO_PinInit(GPIO9, 3U, &USER_LED_config);
/* GPIO configuration of USER_BUTTON on WAKEUP_DIG (pin T8) */
gpio_pin_config_t USER_BUTTON_config = {
.direction = kGPIO_DigitalInput,
.outputLogic = 0U,
.interruptMode = kGPIO_NoIntmode
};
/* Initialize GPIO functionality on WAKEUP_DIG (pin T8) */
GPIO_PinInit(GPIO13, 0U, &USER_BUTTON_config);
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_04_GPIO9_IO03, /* GPIO_AD_04 is configured as GPIO9_IO03 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_WAKEUP_DIG_GPIO13_IO00, /* WAKEUP_DIG is configured as GPIO13_IO00 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_AD_04_GPIO9_IO03, /* GPIO_AD_04 PAD functional properties : */
0x02U); /* Slew Rate Field: Slow Slew Rate
Drive Strength Field: high drive strength
Pull / Keep Select Field: Pull Disable
Pull Up / Down Config. Field: Weak pull down
Open Drain Field: Disabled
Domain write protection: Both cores are allowed
Domain write protection lock: Neither of DWP bits is locked */
IOMUXC_SetPinConfig(
IOMUXC_WAKEUP_DIG_GPIO13_IO00, /* WAKEUP_DIG PAD functional properties : */
0x0EU); /* Pull / Keep Select Field: Pull Enable
Pull Up / Down Config. Field: Weak pull up
Open Drain SNVS Field: Disabled
Domain write protection: Both cores are allowed
Domain write protection lock: Neither of DWP bits is locked */
}
/*
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
BOARD_InitDEBUG_UARTPins:
- options: {callFromInitBoot: 'true', coreID: cm7, enableClock: 'true'}
- pin_list:
- {pin_num: L13, peripheral: LPUART1, signal: TXD, pin_signal: GPIO_AD_24, pull_keeper_select: Keeper, slew_rate: Slow}
- {pin_num: M15, peripheral: LPUART1, signal: RXD, pin_signal: GPIO_AD_25, pull_keeper_select: Keeper, slew_rate: Slow}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
/* FUNCTION ************************************************************************************************************
*
* Function Name : BOARD_InitDEBUG_UARTPins, assigned for the Cortex-M7F core.
* Description : Configures pin routing and optionally pin electrical features.
*
* END ****************************************************************************************************************/
void BOARD_InitDEBUG_UARTPins(void) {
CLOCK_EnableClock(kCLOCK_Iomuxc); /* LPCG on: LPCG is ON. */
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_24_LPUART1_TXD, /* GPIO_AD_24 is configured as LPUART1_TXD */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_25_LPUART1_RXD, /* GPIO_AD_25 is configured as LPUART1_RXD */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_AD_24_LPUART1_TXD, /* GPIO_AD_24 PAD functional properties : */
0x02U); /* Slew Rate Field: Slow Slew Rate
Drive Strength Field: high drive strength
Pull / Keep Select Field: Pull Disable
Pull Up / Down Config. Field: Weak pull down
Open Drain Field: Disabled
Domain write protection: Both cores are allowed
Domain write protection lock: Neither of DWP bits is locked */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_AD_25_LPUART1_RXD, /* GPIO_AD_25 PAD functional properties : */
0x02U); /* Slew Rate Field: Slow Slew Rate
Drive Strength Field: high drive strength
Pull / Keep Select Field: Pull Disable
Pull Up / Down Config. Field: Weak pull down
Open Drain Field: Disabled
Domain write protection: Both cores are allowed
Domain write protection lock: Neither of DWP bits is locked */
}
/***********************************************************************************************************************
* EOF
**********************************************************************************************************************/

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