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chore: sync local state

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tcomlab
2025-12-16 09:12:17 +02:00
parent 7f7195a213
commit 05193dda35
1250 changed files with 45860 additions and 36013 deletions
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2303
build/bootloader/config/kconfig_menus.json
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build/bootloader/config/sdkconfig.cmake
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396
build/bootloader/config/sdkconfig.h
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@@ -3,26 +3,32 @@
* Espressif IoT Development Framework (ESP-IDF) 5.2.1 Configuration Header
*/
#pragma once
#define CONFIG_SOC_MPU_MIN_REGION_SIZE 0x20000000
#define CONFIG_SOC_MPU_REGIONS_MAX_NUM 8
#define CONFIG_SOC_ADC_SUPPORTED 1
#define CONFIG_SOC_DAC_SUPPORTED 1
#define CONFIG_SOC_UART_SUPPORTED 1
#define CONFIG_SOC_TWAI_SUPPORTED 1
#define CONFIG_SOC_CP_DMA_SUPPORTED 1
#define CONFIG_SOC_DEDICATED_GPIO_SUPPORTED 1
#define CONFIG_SOC_GPTIMER_SUPPORTED 1
#define CONFIG_SOC_SUPPORTS_SECURE_DL_MODE 1
#define CONFIG_SOC_ULP_FSM_SUPPORTED 1
#define CONFIG_SOC_RISCV_COPROC_SUPPORTED 1
#define CONFIG_SOC_USB_OTG_SUPPORTED 1
#define CONFIG_SOC_PCNT_SUPPORTED 1
#define CONFIG_SOC_WIFI_SUPPORTED 1
#define CONFIG_SOC_TWAI_SUPPORTED 1
#define CONFIG_SOC_GDMA_SUPPORTED 1
#define CONFIG_SOC_AHB_GDMA_SUPPORTED 1
#define CONFIG_SOC_GPTIMER_SUPPORTED 1
#define CONFIG_SOC_LCDCAM_SUPPORTED 1
#define CONFIG_SOC_MCPWM_SUPPORTED 1
#define CONFIG_SOC_DEDICATED_GPIO_SUPPORTED 1
#define CONFIG_SOC_CACHE_SUPPORT_WRAP 1
#define CONFIG_SOC_ULP_SUPPORTED 1
#define CONFIG_SOC_ULP_FSM_SUPPORTED 1
#define CONFIG_SOC_RISCV_COPROC_SUPPORTED 1
#define CONFIG_SOC_BT_SUPPORTED 1
#define CONFIG_SOC_USB_OTG_SUPPORTED 1
#define CONFIG_SOC_USB_SERIAL_JTAG_SUPPORTED 1
#define CONFIG_SOC_CCOMP_TIMER_SUPPORTED 1
#define CONFIG_SOC_ASYNC_MEMCPY_SUPPORTED 1
#define CONFIG_SOC_SUPPORTS_SECURE_DL_MODE 1
#define CONFIG_SOC_EFUSE_KEY_PURPOSE_FIELD 1
#define CONFIG_SOC_EFUSE_SUPPORTED 1
#define CONFIG_SOC_TEMP_SENSOR_SUPPORTED 1
#define CONFIG_SOC_CACHE_SUPPORT_WRAP 1
#define CONFIG_SOC_SDMMC_HOST_SUPPORTED 1
#define CONFIG_SOC_RTC_FAST_MEM_SUPPORTED 1
#define CONFIG_SOC_RTC_SLOW_MEM_SUPPORTED 1
#define CONFIG_SOC_RTC_MEM_SUPPORTED 1
@@ -35,6 +41,8 @@
#define CONFIG_SOC_LEDC_SUPPORTED 1
#define CONFIG_SOC_I2C_SUPPORTED 1
#define CONFIG_SOC_SYSTIMER_SUPPORTED 1
#define CONFIG_SOC_SUPPORT_COEXISTENCE 1
#define CONFIG_SOC_TEMP_SENSOR_SUPPORTED 1
#define CONFIG_SOC_AES_SUPPORTED 1
#define CONFIG_SOC_MPI_SUPPORTED 1
#define CONFIG_SOC_SHA_SUPPORTED 1
@@ -50,88 +58,103 @@
#define CONFIG_SOC_WDT_SUPPORTED 1
#define CONFIG_SOC_SPI_FLASH_SUPPORTED 1
#define CONFIG_SOC_XTAL_SUPPORT_40M 1
#define CONFIG_SOC_APPCPU_HAS_CLOCK_GATING_BUG 1
#define CONFIG_SOC_ADC_RTC_CTRL_SUPPORTED 1
#define CONFIG_SOC_ADC_DIG_CTRL_SUPPORTED 1
#define CONFIG_SOC_ADC_ARBITER_SUPPORTED 1
#define CONFIG_SOC_ADC_DIG_IIR_FILTER_SUPPORTED 1
#define CONFIG_SOC_ADC_DIG_IIR_FILTER_UNIT_BINDED 1
#define CONFIG_SOC_ADC_MONITOR_SUPPORTED 1
#define CONFIG_SOC_ADC_DMA_SUPPORTED 1
#define CONFIG_SOC_ADC_PERIPH_NUM 2
#define CONFIG_SOC_ADC_MAX_CHANNEL_NUM 10
#define CONFIG_SOC_ADC_ATTEN_NUM 4
#define CONFIG_SOC_ADC_DIGI_CONTROLLER_NUM 2
#define CONFIG_SOC_ADC_PATT_LEN_MAX 32
#define CONFIG_SOC_ADC_PATT_LEN_MAX 24
#define CONFIG_SOC_ADC_DIGI_MIN_BITWIDTH 12
#define CONFIG_SOC_ADC_DIGI_MAX_BITWIDTH 12
#define CONFIG_SOC_ADC_DIGI_RESULT_BYTES 4
#define CONFIG_SOC_ADC_DIGI_DATA_BYTES_PER_CONV 4
#define CONFIG_SOC_ADC_DIGI_IIR_FILTER_NUM 2
#define CONFIG_SOC_ADC_DIGI_RESULT_BYTES 2
#define CONFIG_SOC_ADC_DIGI_DATA_BYTES_PER_CONV 2
#define CONFIG_SOC_ADC_DIGI_MONITOR_NUM 2
#define CONFIG_SOC_ADC_SAMPLE_FREQ_THRES_HIGH 83333
#define CONFIG_SOC_ADC_SAMPLE_FREQ_THRES_LOW 611
#define CONFIG_SOC_ADC_RTC_MIN_BITWIDTH 13
#define CONFIG_SOC_ADC_RTC_MAX_BITWIDTH 13
#define CONFIG_SOC_ADC_RTC_MIN_BITWIDTH 12
#define CONFIG_SOC_ADC_RTC_MAX_BITWIDTH 12
#define CONFIG_SOC_ADC_CALIBRATION_V1_SUPPORTED 1
#define CONFIG_SOC_ADC_SELF_HW_CALI_SUPPORTED 1
#define CONFIG_SOC_ADC_SHARED_POWER 1
#define CONFIG_SOC_APB_BACKUP_DMA 1
#define CONFIG_SOC_BROWNOUT_RESET_SUPPORTED 1
#define CONFIG_SOC_CACHE_WRITEBACK_SUPPORTED 1
#define CONFIG_SOC_CP_DMA_MAX_BUFFER_SIZE 4095
#define CONFIG_SOC_CPU_CORES_NUM 1
#define CONFIG_SOC_CACHE_FREEZE_SUPPORTED 1
#define CONFIG_SOC_CPU_CORES_NUM 2
#define CONFIG_SOC_CPU_INTR_NUM 32
#define CONFIG_SOC_CPU_HAS_FPU 1
#define CONFIG_SOC_HP_CPU_HAS_MULTIPLE_CORES 1
#define CONFIG_SOC_CPU_BREAKPOINTS_NUM 2
#define CONFIG_SOC_CPU_WATCHPOINTS_NUM 2
#define CONFIG_SOC_CPU_WATCHPOINT_MAX_REGION_SIZE 64
#define CONFIG_SOC_DAC_CHAN_NUM 2
#define CONFIG_SOC_DAC_RESOLUTION 8
#define CONFIG_SOC_DS_SIGNATURE_MAX_BIT_LEN 4096
#define CONFIG_SOC_DS_KEY_PARAM_MD_IV_LENGTH 16
#define CONFIG_SOC_DS_KEY_CHECK_MAX_WAIT_US 1100
#define CONFIG_SOC_AHB_GDMA_VERSION 1
#define CONFIG_SOC_GDMA_NUM_GROUPS_MAX 1
#define CONFIG_SOC_GDMA_PAIRS_PER_GROUP 5
#define CONFIG_SOC_GDMA_PAIRS_PER_GROUP_MAX 5
#define CONFIG_SOC_AHB_GDMA_SUPPORT_PSRAM 1
#define CONFIG_SOC_GPIO_PORT 1
#define CONFIG_SOC_GPIO_PIN_COUNT 47
#define CONFIG_SOC_GPIO_PIN_COUNT 49
#define CONFIG_SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER 1
#define CONFIG_SOC_GPIO_FILTER_CLK_SUPPORT_APB 1
#define CONFIG_SOC_GPIO_SUPPORT_RTC_INDEPENDENT 1
#define CONFIG_SOC_GPIO_SUPPORT_FORCE_HOLD 1
#define CONFIG_SOC_GPIO_VALID_GPIO_MASK 0x7FFFFFFFFFFF
#define CONFIG_SOC_GPIO_IN_RANGE_MAX 46
#define CONFIG_SOC_GPIO_OUT_RANGE_MAX 45
#define CONFIG_SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x00007FFFFC000000
#define CONFIG_SOC_GPIO_VALID_GPIO_MASK 0x1FFFFFFFFFFFF
#define CONFIG_SOC_GPIO_IN_RANGE_MAX 48
#define CONFIG_SOC_GPIO_OUT_RANGE_MAX 48
#define CONFIG_SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x0001FFFFFC000000
#define CONFIG_SOC_GPIO_CLOCKOUT_BY_IO_MUX 1
#define CONFIG_SOC_DEDIC_GPIO_OUT_CHANNELS_NUM 8
#define CONFIG_SOC_DEDIC_GPIO_IN_CHANNELS_NUM 8
#define CONFIG_SOC_DEDIC_GPIO_ALLOW_REG_ACCESS 1
#define CONFIG_SOC_DEDIC_GPIO_HAS_INTERRUPT 1
#define CONFIG_SOC_DEDIC_GPIO_OUT_AUTO_ENABLE 1
#define CONFIG_SOC_I2C_NUM 2
#define CONFIG_SOC_I2C_FIFO_LEN 32
#define CONFIG_SOC_I2C_CMD_REG_NUM 16
#define CONFIG_SOC_I2C_CMD_REG_NUM 8
#define CONFIG_SOC_I2C_SUPPORT_SLAVE 1
#define CONFIG_SOC_I2C_SUPPORT_HW_CLR_BUS 1
#define CONFIG_SOC_I2C_SUPPORT_REF_TICK 1
#define CONFIG_SOC_I2C_SUPPORT_APB 1
#define CONFIG_SOC_I2S_NUM 1
#define CONFIG_SOC_I2S_HW_VERSION_1 1
#define CONFIG_SOC_I2S_SUPPORTS_APLL 1
#define CONFIG_SOC_I2C_SUPPORT_XTAL 1
#define CONFIG_SOC_I2C_SUPPORT_RTC 1
#define CONFIG_SOC_I2C_SUPPORT_10BIT_ADDR 1
#define CONFIG_SOC_I2C_SLAVE_SUPPORT_BROADCAST 1
#define CONFIG_SOC_I2C_SLAVE_SUPPORT_I2CRAM_ACCESS 1
#define CONFIG_SOC_I2S_NUM 2
#define CONFIG_SOC_I2S_HW_VERSION_2 1
#define CONFIG_SOC_I2S_SUPPORTS_XTAL 1
#define CONFIG_SOC_I2S_SUPPORTS_PLL_F160M 1
#define CONFIG_SOC_I2S_SUPPORTS_DMA_EQUAL 1
#define CONFIG_SOC_I2S_SUPPORTS_LCD_CAMERA 1
#define CONFIG_SOC_I2S_APLL_MIN_FREQ 250000000
#define CONFIG_SOC_I2S_APLL_MAX_FREQ 500000000
#define CONFIG_SOC_I2S_APLL_MIN_RATE 10675
#define CONFIG_SOC_I2S_LCD_I80_VARIANT 1
#define CONFIG_SOC_LCD_I80_SUPPORTED 1
#define CONFIG_SOC_LCD_I80_BUSES 1
#define CONFIG_SOC_LCD_I80_BUS_WIDTH 24
#define CONFIG_SOC_LEDC_HAS_TIMER_SPECIFIC_MUX 1
#define CONFIG_SOC_I2S_SUPPORTS_PCM 1
#define CONFIG_SOC_I2S_SUPPORTS_PDM 1
#define CONFIG_SOC_I2S_SUPPORTS_PDM_TX 1
#define CONFIG_SOC_I2S_PDM_MAX_TX_LINES 2
#define CONFIG_SOC_I2S_SUPPORTS_PDM_RX 1
#define CONFIG_SOC_I2S_PDM_MAX_RX_LINES 4
#define CONFIG_SOC_I2S_SUPPORTS_TDM 1
#define CONFIG_SOC_LEDC_SUPPORT_APB_CLOCK 1
#define CONFIG_SOC_LEDC_SUPPORT_REF_TICK 1
#define CONFIG_SOC_LEDC_SUPPORT_XTAL_CLOCK 1
#define CONFIG_SOC_LEDC_CHANNEL_NUM 8
#define CONFIG_SOC_LEDC_TIMER_BIT_WIDTH 14
#define CONFIG_SOC_LEDC_SUPPORT_FADE_STOP 1
#define CONFIG_SOC_MMU_LINEAR_ADDRESS_REGION_NUM 5
#define CONFIG_SOC_MCPWM_GROUPS 2
#define CONFIG_SOC_MCPWM_TIMERS_PER_GROUP 3
#define CONFIG_SOC_MCPWM_OPERATORS_PER_GROUP 3
#define CONFIG_SOC_MCPWM_COMPARATORS_PER_OPERATOR 2
#define CONFIG_SOC_MCPWM_GENERATORS_PER_OPERATOR 2
#define CONFIG_SOC_MCPWM_TRIGGERS_PER_OPERATOR 2
#define CONFIG_SOC_MCPWM_GPIO_FAULTS_PER_GROUP 3
#define CONFIG_SOC_MCPWM_CAPTURE_TIMERS_PER_GROUP 1
#define CONFIG_SOC_MCPWM_CAPTURE_CHANNELS_PER_TIMER 3
#define CONFIG_SOC_MCPWM_GPIO_SYNCHROS_PER_GROUP 3
#define CONFIG_SOC_MCPWM_SWSYNC_CAN_PROPAGATE 1
#define CONFIG_SOC_MMU_LINEAR_ADDRESS_REGION_NUM 1
#define CONFIG_SOC_MMU_PERIPH_NUM 1
#define CONFIG_SOC_MPU_MIN_REGION_SIZE 0x20000000
#define CONFIG_SOC_MPU_REGIONS_MAX_NUM 8
#define CONFIG_SOC_PCNT_GROUPS 1
#define CONFIG_SOC_PCNT_UNITS_PER_GROUP 4
#define CONFIG_SOC_PCNT_CHANNELS_PER_UNIT 2
@@ -139,16 +162,29 @@
#define CONFIG_SOC_RMT_GROUPS 1
#define CONFIG_SOC_RMT_TX_CANDIDATES_PER_GROUP 4
#define CONFIG_SOC_RMT_RX_CANDIDATES_PER_GROUP 4
#define CONFIG_SOC_RMT_CHANNELS_PER_GROUP 4
#define CONFIG_SOC_RMT_MEM_WORDS_PER_CHANNEL 64
#define CONFIG_SOC_RMT_CHANNELS_PER_GROUP 8
#define CONFIG_SOC_RMT_MEM_WORDS_PER_CHANNEL 48
#define CONFIG_SOC_RMT_SUPPORT_RX_PINGPONG 1
#define CONFIG_SOC_RMT_SUPPORT_RX_DEMODULATION 1
#define CONFIG_SOC_RMT_SUPPORT_TX_ASYNC_STOP 1
#define CONFIG_SOC_RMT_SUPPORT_TX_LOOP_COUNT 1
#define CONFIG_SOC_RMT_SUPPORT_TX_LOOP_AUTO_STOP 1
#define CONFIG_SOC_RMT_SUPPORT_TX_SYNCHRO 1
#define CONFIG_SOC_RMT_SUPPORT_TX_CARRIER_DATA_ONLY 1
#define CONFIG_SOC_RMT_SUPPORT_REF_TICK 1
#define CONFIG_SOC_RMT_SUPPORT_XTAL 1
#define CONFIG_SOC_RMT_SUPPORT_RC_FAST 1
#define CONFIG_SOC_RMT_SUPPORT_APB 1
#define CONFIG_SOC_RMT_CHANNEL_CLK_INDEPENDENT 1
#define CONFIG_SOC_RMT_SUPPORT_DMA 1
#define CONFIG_SOC_LCD_I80_SUPPORTED 1
#define CONFIG_SOC_LCD_RGB_SUPPORTED 1
#define CONFIG_SOC_LCD_I80_BUSES 1
#define CONFIG_SOC_LCD_RGB_PANELS 1
#define CONFIG_SOC_LCD_I80_BUS_WIDTH 16
#define CONFIG_SOC_LCD_RGB_DATA_WIDTH 16
#define CONFIG_SOC_LCD_SUPPORT_RGB_YUV_CONV 1
#define CONFIG_SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH 128
#define CONFIG_SOC_RTC_CNTL_CPU_PD_REG_FILE_NUM 549
#define CONFIG_SOC_RTC_CNTL_TAGMEM_PD_DMA_BUS_WIDTH 128
#define CONFIG_SOC_RTCIO_PIN_COUNT 22
#define CONFIG_SOC_RTCIO_INPUT_OUTPUT_SUPPORTED 1
#define CONFIG_SOC_RTCIO_HOLD_SUPPORTED 1
@@ -156,59 +192,64 @@
#define CONFIG_SOC_SDM_GROUPS 1
#define CONFIG_SOC_SDM_CHANNELS_PER_GROUP 8
#define CONFIG_SOC_SDM_CLK_SUPPORT_APB 1
#define CONFIG_SOC_SPI_HD_BOTH_INOUT_SUPPORTED 1
#define CONFIG_SOC_SPI_PERIPH_NUM 3
#define CONFIG_SOC_SPI_DMA_CHAN_NUM 3
#define CONFIG_SOC_SPI_MAX_CS_NUM 6
#define CONFIG_SOC_SPI_MAXIMUM_BUFFER_SIZE 72
#define CONFIG_SOC_SPI_MAX_PRE_DIVIDER 8192
#define CONFIG_SOC_SPI_MAXIMUM_BUFFER_SIZE 64
#define CONFIG_SOC_SPI_SUPPORT_DDRCLK 1
#define CONFIG_SOC_SPI_SLAVE_SUPPORT_SEG_TRANS 1
#define CONFIG_SOC_SPI_SUPPORT_CD_SIG 1
#define CONFIG_SOC_SPI_SUPPORT_CONTINUOUS_TRANS 1
#define CONFIG_SOC_SPI_SUPPORT_CLK_APB 1
#define CONFIG_SOC_SPI_SUPPORT_SLAVE_HD_VER2 1
#define CONFIG_SOC_SPI_SUPPORT_CLK_APB 1
#define CONFIG_SOC_SPI_SUPPORT_CLK_XTAL 1
#define CONFIG_SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUT 1
#define CONFIG_SOC_MEMSPI_IS_INDEPENDENT 1
#define CONFIG_SOC_SPI_MAX_PRE_DIVIDER 16
#define CONFIG_SOC_SPI_SUPPORT_OCT 1
#define CONFIG_SOC_MEMSPI_SRC_FREQ_120M 1
#define CONFIG_SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED 1
#define CONFIG_SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED 1
#define CONFIG_SOC_MEMSPI_SRC_FREQ_26M_SUPPORTED 1
#define CONFIG_SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED 1
#define CONFIG_SOC_SYSTIMER_COUNTER_NUM 1
#define CONFIG_SOC_SPIRAM_SUPPORTED 1
#define CONFIG_SOC_SPIRAM_XIP_SUPPORTED 1
#define CONFIG_SOC_SYSTIMER_COUNTER_NUM 2
#define CONFIG_SOC_SYSTIMER_ALARM_NUM 3
#define CONFIG_SOC_SYSTIMER_BIT_WIDTH_LO 32
#define CONFIG_SOC_SYSTIMER_BIT_WIDTH_HI 32
#define CONFIG_SOC_SYSTIMER_BIT_WIDTH_HI 20
#define CONFIG_SOC_SYSTIMER_FIXED_DIVIDER 1
#define CONFIG_SOC_SYSTIMER_INT_LEVEL 1
#define CONFIG_SOC_SYSTIMER_ALARM_MISS_COMPENSATE 1
#define CONFIG_SOC_TIMER_GROUPS 2
#define CONFIG_SOC_TIMER_GROUP_TIMERS_PER_GROUP 2
#define CONFIG_SOC_TIMER_GROUP_COUNTER_BIT_WIDTH 64
#define CONFIG_SOC_TIMER_GROUP_COUNTER_BIT_WIDTH 54
#define CONFIG_SOC_TIMER_GROUP_SUPPORT_XTAL 1
#define CONFIG_SOC_TIMER_GROUP_SUPPORT_APB 1
#define CONFIG_SOC_TIMER_GROUP_TOTAL_TIMERS 4
#define CONFIG_SOC_TOUCH_VERSION_2 1
#define CONFIG_SOC_TOUCH_SENSOR_NUM 15
#define CONFIG_SOC_TOUCH_PROXIMITY_CHANNEL_NUM 3
#define CONFIG_SOC_TOUCH_PROXIMITY_MEAS_DONE_SUPPORTED 1
#define CONFIG_SOC_TOUCH_PAD_THRESHOLD_MAX 0x1FFFFF
#define CONFIG_SOC_TOUCH_PAD_MEASURE_WAIT_MAX 0xFF
#define CONFIG_SOC_TWAI_CONTROLLER_NUM 1
#define CONFIG_SOC_TWAI_CLK_SUPPORT_APB 1
#define CONFIG_SOC_TWAI_BRP_MIN 2
#define CONFIG_SOC_TWAI_BRP_MAX 32768
#define CONFIG_SOC_TWAI_BRP_MAX 16384
#define CONFIG_SOC_TWAI_SUPPORTS_RX_STATUS 1
#define CONFIG_SOC_UART_NUM 2
#define CONFIG_SOC_UART_HP_NUM 2
#define CONFIG_SOC_UART_SUPPORT_WAKEUP_INT 1
#define CONFIG_SOC_UART_SUPPORT_APB_CLK 1
#define CONFIG_SOC_UART_SUPPORT_REF_TICK 1
#define CONFIG_SOC_UART_NUM 3
#define CONFIG_SOC_UART_HP_NUM 3
#define CONFIG_SOC_UART_FIFO_LEN 128
#define CONFIG_SOC_UART_BITRATE_MAX 5000000
#define CONFIG_SOC_SPIRAM_SUPPORTED 1
#define CONFIG_SOC_SPIRAM_XIP_SUPPORTED 1
#define CONFIG_SOC_UART_SUPPORT_FSM_TX_WAIT_SEND 1
#define CONFIG_SOC_UART_SUPPORT_WAKEUP_INT 1
#define CONFIG_SOC_UART_SUPPORT_APB_CLK 1
#define CONFIG_SOC_UART_SUPPORT_RTC_CLK 1
#define CONFIG_SOC_UART_SUPPORT_XTAL_CLK 1
#define CONFIG_SOC_USB_OTG_PERIPH_NUM 1
#define CONFIG_SOC_SHA_DMA_MAX_BUFFER_SIZE 3968
#define CONFIG_SOC_SHA_SUPPORT_DMA 1
#define CONFIG_SOC_SHA_SUPPORT_RESUME 1
#define CONFIG_SOC_SHA_CRYPTO_DMA 1
#define CONFIG_SOC_SHA_GDMA 1
#define CONFIG_SOC_SHA_SUPPORT_SHA1 1
#define CONFIG_SOC_SHA_SUPPORT_SHA224 1
#define CONFIG_SOC_SHA_SUPPORT_SHA256 1
@@ -221,14 +262,38 @@
#define CONFIG_SOC_MPI_OPERATIONS_NUM 3
#define CONFIG_SOC_RSA_MAX_BIT_LEN 4096
#define CONFIG_SOC_AES_SUPPORT_DMA 1
#define CONFIG_SOC_AES_SUPPORT_GCM 1
#define CONFIG_SOC_AES_GDMA 1
#define CONFIG_SOC_AES_SUPPORT_AES_128 1
#define CONFIG_SOC_AES_SUPPORT_AES_256 1
#define CONFIG_SOC_PM_SUPPORT_EXT0_WAKEUP 1
#define CONFIG_SOC_PM_SUPPORT_EXT1_WAKEUP 1
#define CONFIG_SOC_PM_SUPPORT_EXT_WAKEUP 1
#define CONFIG_SOC_PM_SUPPORT_WIFI_WAKEUP 1
#define CONFIG_SOC_PM_SUPPORT_BT_WAKEUP 1
#define CONFIG_SOC_PM_SUPPORT_TOUCH_SENSOR_WAKEUP 1
#define CONFIG_SOC_PM_SUPPORT_CPU_PD 1
#define CONFIG_SOC_PM_SUPPORT_TAGMEM_PD 1
#define CONFIG_SOC_PM_SUPPORT_RTC_PERIPH_PD 1
#define CONFIG_SOC_PM_SUPPORT_RC_FAST_PD 1
#define CONFIG_SOC_PM_SUPPORT_VDDSDIO_PD 1
#define CONFIG_SOC_PM_SUPPORT_MAC_BB_PD 1
#define CONFIG_SOC_PM_SUPPORT_MODEM_PD 1
#define CONFIG_SOC_CONFIGURABLE_VDDSDIO_SUPPORTED 1
#define CONFIG_SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY 1
#define CONFIG_SOC_PM_CPU_RETENTION_BY_RTCCNTL 1
#define CONFIG_SOC_PM_MODEM_RETENTION_BY_BACKUPDMA 1
#define CONFIG_SOC_CLK_RC_FAST_D256_SUPPORTED 1
#define CONFIG_SOC_RTC_SLOW_CLK_SUPPORT_RC_FAST_D256 1
#define CONFIG_SOC_CLK_RC_FAST_SUPPORT_CALIBRATION 1
#define CONFIG_SOC_CLK_XTAL32K_SUPPORTED 1
#define CONFIG_SOC_EFUSE_DIS_DOWNLOAD_ICACHE 1
#define CONFIG_SOC_EFUSE_DIS_DOWNLOAD_DCACHE 1
#define CONFIG_SOC_EFUSE_HARD_DIS_JTAG 1
#define CONFIG_SOC_EFUSE_DIS_USB_JTAG 1
#define CONFIG_SOC_EFUSE_SOFT_DIS_JTAG 1
#define CONFIG_SOC_EFUSE_DIS_BOOT_REMAP 1
#define CONFIG_SOC_EFUSE_DIS_LEGACY_SPI_BOOT 1
#define CONFIG_SOC_EFUSE_DIS_DIRECT_BOOT 1
#define CONFIG_SOC_EFUSE_DIS_ICACHE 1
#define CONFIG_SOC_EFUSE_BLOCK9_KEY_PURPOSE_QUIRK 1
#define CONFIG_SOC_SECURE_BOOT_V2_RSA 1
#define CONFIG_SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS 3
#define CONFIG_SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS 1
@@ -239,60 +304,56 @@
#define CONFIG_SOC_FLASH_ENCRYPTION_XTS_AES_128 1
#define CONFIG_SOC_FLASH_ENCRYPTION_XTS_AES_256 1
#define CONFIG_SOC_MEMPROT_CPU_PREFETCH_PAD_SIZE 16
#define CONFIG_SOC_MEMPROT_MEM_ALIGN_SIZE 4
#define CONFIG_SOC_AES_CRYPTO_DMA 1
#define CONFIG_SOC_AES_SUPPORT_AES_128 1
#define CONFIG_SOC_AES_SUPPORT_AES_192 1
#define CONFIG_SOC_AES_SUPPORT_AES_256 1
#define CONFIG_SOC_MEMPROT_MEM_ALIGN_SIZE 256
#define CONFIG_SOC_PHY_DIG_REGS_MEM_SIZE 21
#define CONFIG_SOC_MAC_BB_PD_MEM_SIZE 192
#define CONFIG_SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH 12
#define CONFIG_SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE 1
#define CONFIG_SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND 1
#define CONFIG_SOC_SPI_MEM_SUPPORT_AUTO_RESUME 1
#define CONFIG_SOC_SPI_MEM_SUPPORT_SW_SUSPEND 1
#define CONFIG_SOC_SPI_MEM_SUPPORT_OPI_MODE 1
#define CONFIG_SOC_SPI_MEM_SUPPORT_TIMING_TUNING 1
#define CONFIG_SOC_SPI_MEM_SUPPORT_CONFIG_GPIO_BY_EFUSE 1
#define CONFIG_SOC_SPI_MEM_SUPPORT_WRAP 1
#define CONFIG_SOC_PM_SUPPORT_EXT0_WAKEUP 1
#define CONFIG_SOC_PM_SUPPORT_EXT1_WAKEUP 1
#define CONFIG_SOC_PM_SUPPORT_EXT_WAKEUP 1
#define CONFIG_SOC_PM_SUPPORT_WIFI_WAKEUP 1
#define CONFIG_SOC_PM_SUPPORT_TOUCH_SENSOR_WAKEUP 1
#define CONFIG_SOC_PM_SUPPORT_WIFI_PD 1
#define CONFIG_SOC_PM_SUPPORT_RTC_PERIPH_PD 1
#define CONFIG_SOC_PM_SUPPORT_RTC_FAST_MEM_PD 1
#define CONFIG_SOC_PM_SUPPORT_RTC_SLOW_MEM_PD 1
#define CONFIG_SOC_PM_SUPPORT_RC_FAST_PD 1
#define CONFIG_SOC_PM_SUPPORT_VDDSDIO_PD 1
#define CONFIG_SOC_CONFIGURABLE_VDDSDIO_SUPPORTED 1
#define CONFIG_SOC_CLK_APLL_SUPPORTED 1
#define CONFIG_SOC_CLK_RC_FAST_D256_SUPPORTED 1
#define CONFIG_SOC_RTC_SLOW_CLK_SUPPORT_RC_FAST_D256 1
#define CONFIG_SOC_CLK_RC_FAST_SUPPORT_CALIBRATION 1
#define CONFIG_SOC_CLK_XTAL32K_SUPPORTED 1
#define CONFIG_SOC_MEMSPI_TIMING_TUNING_BY_MSPI_DELAY 1
#define CONFIG_SOC_MEMSPI_CORE_CLK_SHARED_WITH_PSRAM 1
#define CONFIG_SOC_COEX_HW_PTI 1
#define CONFIG_SOC_EXTERNAL_COEX_LEADER_TX_LINE 1
#define CONFIG_SOC_SDMMC_USE_GPIO_MATRIX 1
#define CONFIG_SOC_SDMMC_NUM_SLOTS 2
#define CONFIG_SOC_SDMMC_SUPPORT_XTAL_CLOCK 1
#define CONFIG_SOC_SDMMC_DELAY_PHASE_NUM 4
#define CONFIG_SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC 1
#define CONFIG_SOC_WIFI_HW_TSF 1
#define CONFIG_SOC_WIFI_FTM_SUPPORT 1
#define CONFIG_SOC_WIFI_GCMP_SUPPORT 1
#define CONFIG_SOC_WIFI_WAPI_SUPPORT 1
#define CONFIG_SOC_WIFI_CSI_SUPPORT 1
#define CONFIG_SOC_WIFI_MESH_SUPPORT 1
#define CONFIG_SOC_WIFI_SUPPORT_VARIABLE_BEACON_WINDOW 1
#define CONFIG_SOC_WIFI_NAN_SUPPORT 1
#define CONFIG_SOC_BLE_SUPPORTED 1
#define CONFIG_SOC_BLE_MESH_SUPPORTED 1
#define CONFIG_SOC_BLE_50_SUPPORTED 1
#define CONFIG_SOC_BLE_DEVICE_PRIVACY_SUPPORTED 1
#define CONFIG_SOC_BLUFI_SUPPORTED 1
#define CONFIG_SOC_ULP_HAS_ADC 1
#define CONFIG_SOC_PHY_COMBO_MODULE 1
#define CONFIG_IDF_CMAKE 1
#define CONFIG_IDF_TOOLCHAIN "gcc"
#define CONFIG_IDF_TARGET_ARCH_XTENSA 1
#define CONFIG_IDF_TARGET_ARCH "xtensa"
#define CONFIG_IDF_TARGET "esp32s2"
#define CONFIG_IDF_TARGET "esp32s3"
#define CONFIG_IDF_INIT_VERSION "5.2.1"
#define CONFIG_IDF_TARGET_ESP32S2 1
#define CONFIG_IDF_FIRMWARE_CHIP_ID 0x0002
#define CONFIG_IDF_TARGET_ESP32S3 1
#define CONFIG_IDF_FIRMWARE_CHIP_ID 0x0009
#define CONFIG_APP_BUILD_TYPE_APP_2NDBOOT 1
#define CONFIG_APP_BUILD_GENERATE_BINARIES 1
#define CONFIG_APP_BUILD_BOOTLOADER 1
#define CONFIG_APP_BUILD_USE_FLASH_SECTIONS 1
#define CONFIG_BOOTLOADER_COMPILE_TIME_DATE 1
#define CONFIG_BOOTLOADER_PROJECT_VER 1
#define CONFIG_BOOTLOADER_OFFSET_IN_FLASH 0x1000
#define CONFIG_BOOTLOADER_OFFSET_IN_FLASH 0x0
#define CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE 1
#define CONFIG_BOOTLOADER_LOG_LEVEL_INFO 1
#define CONFIG_BOOTLOADER_LOG_LEVEL 3
@@ -308,32 +369,45 @@
#define CONFIG_APP_COMPILE_TIME_DATE 1
#define CONFIG_APP_RETRIEVE_LEN_ELF_SHA 9
#define CONFIG_ESP_ROM_HAS_CRC_LE 1
#define CONFIG_ESP_ROM_HAS_CRC_BE 1
#define CONFIG_ESP_ROM_HAS_MZ_CRC32 1
#define CONFIG_ESP_ROM_HAS_UART_BUF_SWITCH 1
#define CONFIG_ESP_ROM_NEEDS_SWSETUP_WORKAROUND 1
#define CONFIG_ESP_ROM_HAS_REGI2C_BUG 1
#define CONFIG_ESP_ROM_HAS_NEWLIB_NANO_FORMAT 1
#define CONFIG_ESP_ROM_HAS_JPEG_DECODE 1
#define CONFIG_ESP_ROM_UART_CLK_IS_XTAL 1
#define CONFIG_ESP_ROM_HAS_RETARGETABLE_LOCKING 1
#define CONFIG_ESP_ROM_USB_OTG_NUM 3
#define CONFIG_ESP_ROM_USB_SERIAL_DEVICE_NUM 4
#define CONFIG_ESP_ROM_HAS_ERASE_0_REGION_BUG 1
#define CONFIG_ESP_ROM_GET_CLK_FREQ 1
#define CONFIG_ESP_ROM_HAS_HAL_WDT 1
#define CONFIG_ESP_ROM_NEEDS_SWSETUP_WORKAROUND 1
#define CONFIG_ESP_ROM_HAS_LAYOUT_TABLE 1
#define CONFIG_ESP_ROM_HAS_SPI_FLASH 1
#define CONFIG_ESP_ROM_HAS_ETS_PRINTF_BUG 1
#define CONFIG_ESP_ROM_HAS_NEWLIB_NANO_FORMAT 1
#define CONFIG_ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE 1
#define CONFIG_ESP_ROM_RAM_APP_NEEDS_MMU_INIT 1
#define CONFIG_ESP_ROM_HAS_FLASH_COUNT_PAGES_BUG 1
#define CONFIG_ESP_ROM_HAS_CACHE_SUSPEND_WAITI_BUG 1
#define CONFIG_ESP_ROM_HAS_CACHE_WRITEBACK_BUG 1
#define CONFIG_ESP_ROM_HAS_SW_FLOAT 1
#define CONFIG_ESP_ROM_USB_SERIAL_DEVICE_NUM -1
#define CONFIG_BOOT_ROM_LOG_ALWAYS_ON 1
#define CONFIG_ESPTOOLPY_FLASH_MODE_AUTO_DETECT 1
#define CONFIG_ESPTOOLPY_FLASHMODE_DIO 1
#define CONFIG_ESPTOOLPY_FLASH_SAMPLE_MODE_STR 1
#define CONFIG_ESPTOOLPY_FLASHMODE "dio"
#define CONFIG_ESPTOOLPY_FLASHFREQ_80M 1
#define CONFIG_ESPTOOLPY_FLASHFREQ_80M_DEFAULT 1
#define CONFIG_ESPTOOLPY_FLASHFREQ "80m"
#define CONFIG_ESPTOOLPY_FLASHSIZE_4MB 1
#define CONFIG_ESPTOOLPY_FLASHSIZE "4MB"
#define CONFIG_ESPTOOLPY_FLASHSIZE_2MB 1
#define CONFIG_ESPTOOLPY_FLASHSIZE "2MB"
#define CONFIG_ESPTOOLPY_BEFORE_RESET 1
#define CONFIG_ESPTOOLPY_BEFORE "default_reset"
#define CONFIG_ESPTOOLPY_AFTER_RESET 1
#define CONFIG_ESPTOOLPY_AFTER "hard_reset"
#define CONFIG_ESPTOOLPY_MONITOR_BAUD 115200
#define CONFIG_PARTITION_TABLE_CUSTOM 1
#define CONFIG_PARTITION_TABLE_SINGLE_APP 1
#define CONFIG_PARTITION_TABLE_CUSTOM_FILENAME "partitions.csv"
#define CONFIG_PARTITION_TABLE_FILENAME "partitions.csv"
#define CONFIG_PARTITION_TABLE_FILENAME "partitions_singleapp.csv"
#define CONFIG_PARTITION_TABLE_OFFSET 0x8000
#define CONFIG_PARTITION_TABLE_MD5 1
#define CONFIG_COMPILER_OPTIMIZATION_DEBUG 1
@@ -346,35 +420,46 @@
#define CONFIG_COMPILER_RT_LIB_NAME "gcc"
#define CONFIG_EFUSE_MAX_BLK_LEN 256
#define CONFIG_ESP_ERR_TO_NAME_LOOKUP 1
#define CONFIG_ESP32S2_REV_MIN_0 1
#define CONFIG_ESP32S2_REV_MIN_FULL 0
#define CONFIG_ESP32S3_REV_MIN_0 1
#define CONFIG_ESP32S3_REV_MIN_FULL 0
#define CONFIG_ESP_REV_MIN_FULL 0
#define CONFIG_ESP32S2_REV_MAX_FULL 199
#define CONFIG_ESP_REV_MAX_FULL 199
#define CONFIG_ESP32S3_REV_MAX_FULL 99
#define CONFIG_ESP_REV_MAX_FULL 99
#define CONFIG_ESP_MAC_ADDR_UNIVERSE_WIFI_STA 1
#define CONFIG_ESP_MAC_ADDR_UNIVERSE_WIFI_AP 1
#define CONFIG_ESP_MAC_UNIVERSAL_MAC_ADDRESSES_TWO 1
#define CONFIG_ESP32S2_UNIVERSAL_MAC_ADDRESSES_TWO 1
#define CONFIG_ESP32S2_UNIVERSAL_MAC_ADDRESSES 2
#define CONFIG_ESP_MAC_ADDR_UNIVERSE_BT 1
#define CONFIG_ESP_MAC_ADDR_UNIVERSE_ETH 1
#define CONFIG_ESP_MAC_UNIVERSAL_MAC_ADDRESSES_FOUR 1
#define CONFIG_ESP32S3_UNIVERSAL_MAC_ADDRESSES_FOUR 1
#define CONFIG_ESP32S3_UNIVERSAL_MAC_ADDRESSES 4
#define CONFIG_ESP_SLEEP_FLASH_LEAKAGE_WORKAROUND 1
#define CONFIG_ESP_SLEEP_MSPI_NEED_ALL_IO_PU 1
#define CONFIG_ESP_SLEEP_RTC_BUS_ISO_WORKAROUND 1
#define CONFIG_ESP_SLEEP_WAIT_FLASH_READY_EXTRA_DELAY 0
#define CONFIG_ESP_SLEEP_GPIO_RESET_WORKAROUND 1
#define CONFIG_ESP_SLEEP_WAIT_FLASH_READY_EXTRA_DELAY 2000
#define CONFIG_ESP_SLEEP_GPIO_ENABLE_INTERNAL_RESISTORS 1
#define CONFIG_RTC_CLK_SRC_INT_RC 1
#define CONFIG_RTC_CLK_CAL_CYCLES 576
#define CONFIG_RTC_CLK_CAL_CYCLES 1024
#define CONFIG_PERIPH_CTRL_FUNC_IN_IRAM 1
#define CONFIG_XTAL_FREQ_40 1
#define CONFIG_XTAL_FREQ 40
#define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_160 1
#define CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ 160
#define CONFIG_ESP32S2_INSTRUCTION_CACHE_8KB 1
#define CONFIG_ESP32S2_INSTRUCTION_CACHE_LINE_32B 1
#define CONFIG_ESP32S2_DATA_CACHE_8KB 1
#define CONFIG_ESP32S2_DATA_CACHE_LINE_32B 1
#define CONFIG_ESP32S2_TRACEMEM_RESERVE_DRAM 0x0
#define CONFIG_ESP32S3_INSTRUCTION_CACHE_16KB 1
#define CONFIG_ESP32S3_INSTRUCTION_CACHE_SIZE 0x4000
#define CONFIG_ESP32S3_INSTRUCTION_CACHE_8WAYS 1
#define CONFIG_ESP32S3_ICACHE_ASSOCIATED_WAYS 8
#define CONFIG_ESP32S3_INSTRUCTION_CACHE_LINE_32B 1
#define CONFIG_ESP32S3_INSTRUCTION_CACHE_LINE_SIZE 32
#define CONFIG_ESP32S3_DATA_CACHE_32KB 1
#define CONFIG_ESP32S3_DATA_CACHE_SIZE 0x8000
#define CONFIG_ESP32S3_DATA_CACHE_8WAYS 1
#define CONFIG_ESP32S3_DCACHE_ASSOCIATED_WAYS 8
#define CONFIG_ESP32S3_DATA_CACHE_LINE_32B 1
#define CONFIG_ESP32S3_DATA_CACHE_LINE_SIZE 32
#define CONFIG_ESP32S3_TRACEMEM_RESERVE_DRAM 0x0
#define CONFIG_ESP_SYSTEM_PANIC_PRINT_REBOOT 1
#define CONFIG_ESP_SYSTEM_PANIC_REBOOT_DELAY_SECONDS 0
#define CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE 1
#define CONFIG_ESP_SYSTEM_RTC_FAST_MEM_AS_HEAP_DEPCHECK 1
#define CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP 1
#define CONFIG_ESP_SYSTEM_MEMPROT_FEATURE 1
@@ -385,27 +470,31 @@
#define CONFIG_ESP_MAIN_TASK_AFFINITY_CPU0 1
#define CONFIG_ESP_MAIN_TASK_AFFINITY 0x0
#define CONFIG_ESP_MINIMAL_SHARED_STACK_SIZE 2048
#define CONFIG_ESP_CONSOLE_USB_CDC 1
#define CONFIG_ESP_CONSOLE_UART_NUM -1
#define CONFIG_ESP_CONSOLE_USB_CDC_RX_BUF_SIZE 64
#define CONFIG_ESP_CONSOLE_USB_CDC_SUPPORT_ETS_PRINTF 1
#define CONFIG_ESP_CONSOLE_UART_DEFAULT 1
#define CONFIG_ESP_CONSOLE_SECONDARY_USB_SERIAL_JTAG 1
#define CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG_ENABLED 1
#define CONFIG_ESP_CONSOLE_UART 1
#define CONFIG_ESP_CONSOLE_UART_NUM 0
#define CONFIG_ESP_CONSOLE_UART_BAUDRATE 115200
#define CONFIG_ESP_INT_WDT 1
#define CONFIG_ESP_INT_WDT_TIMEOUT_MS 300
#define CONFIG_ESP_INT_WDT_CHECK_CPU1 1
#define CONFIG_ESP_TASK_WDT_EN 1
#define CONFIG_ESP_TASK_WDT_INIT 1
#define CONFIG_ESP_TASK_WDT_TIMEOUT_S 5
#define CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU0 1
#define CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU1 1
#define CONFIG_ESP_DEBUG_OCDAWARE 1
#define CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_4 1
#define CONFIG_ESP_BROWNOUT_DET 1
#define CONFIG_ESP_BROWNOUT_DET_LVL_SEL_7 1
#define CONFIG_ESP_BROWNOUT_DET_LVL 7
#define CONFIG_ESP32S2_KEEP_USB_ALIVE 1
#define CONFIG_ESP_SYSTEM_BROWNOUT_INTR 1
#define CONFIG_ESP_IPC_TASK_STACK_SIZE 1024
#define CONFIG_FREERTOS_UNICORE 1
#define CONFIG_ESP_SYSTEM_BBPLL_RECALIB 1
#define CONFIG_ESP_IPC_TASK_STACK_SIZE 1280
#define CONFIG_ESP_IPC_USES_CALLERS_PRIORITY 1
#define CONFIG_ESP_IPC_ISR_ENABLE 1
#define CONFIG_FREERTOS_HZ 100
#define CONFIG_FREERTOS_OPTIMIZED_SCHEDULER 1
#define CONFIG_FREERTOS_CHECK_STACKOVERFLOW_CANARY 1
#define CONFIG_FREERTOS_THREAD_LOCAL_STORAGE_POINTERS 1
#define CONFIG_FREERTOS_IDLE_TASK_STACKSIZE 1536
@@ -421,9 +510,9 @@
#define CONFIG_FREERTOS_CHECK_MUTEX_GIVEN_BY_OWNER 1
#define CONFIG_FREERTOS_ISR_STACKSIZE 1536
#define CONFIG_FREERTOS_INTERRUPT_BACKTRACE 1
#define CONFIG_FREERTOS_TICK_SUPPORT_CORETIMER 1
#define CONFIG_FREERTOS_CORETIMER_0 1
#define CONFIG_FREERTOS_SYSTICK_USES_CCOUNT 1
#define CONFIG_FREERTOS_TICK_SUPPORT_SYSTIMER 1
#define CONFIG_FREERTOS_CORETIMER_SYSTIMER_LVL1 1
#define CONFIG_FREERTOS_SYSTICK_USES_SYSTIMER 1
#define CONFIG_FREERTOS_PORT 1
#define CONFIG_FREERTOS_NO_AFFINITY 0x7FFFFFFF
#define CONFIG_FREERTOS_SUPPORT_STATIC_ALLOCATION 1
@@ -432,6 +521,7 @@
#define CONFIG_FREERTOS_PLACE_SNAPSHOT_FUNS_INTO_FLASH 1
#define CONFIG_HAL_ASSERTION_EQUALS_SYSTEM 1
#define CONFIG_HAL_DEFAULT_ASSERTION_LEVEL 2
#define CONFIG_HAL_WDT_USE_ROM_IMPL 1
#define CONFIG_LOG_DEFAULT_LEVEL_INFO 1
#define CONFIG_LOG_DEFAULT_LEVEL 3
#define CONFIG_LOG_MAXIMUM_EQUALS_DEFAULT 1
@@ -446,6 +536,10 @@
#define CONFIG_MMU_PAGE_SIZE 0x10000
#define CONFIG_SPI_FLASH_BROWNOUT_RESET_XMC 1
#define CONFIG_SPI_FLASH_BROWNOUT_RESET 1
#define CONFIG_SPI_FLASH_HPM_AUTO 1
#define CONFIG_SPI_FLASH_HPM_ON 1
#define CONFIG_SPI_FLASH_HPM_DC_AUTO 1
#define CONFIG_SPI_FLASH_SUSPEND_QVL_SUPPORTED 1
#define CONFIG_SPI_FLASH_ROM_DRIVER_PATCH 1
#define CONFIG_SPI_FLASH_DANGEROUS_WRITE_ABORTS 1
#define CONFIG_SPI_FLASH_YIELD_DURING_ERASE 1
@@ -465,6 +559,7 @@
#define CONFIG_SPI_FLASH_SUPPORT_WINBOND_CHIP 1
#define CONFIG_SPI_FLASH_SUPPORT_BOYA_CHIP 1
#define CONFIG_SPI_FLASH_SUPPORT_TH_CHIP 1
#define CONFIG_SPI_FLASH_SUPPORT_MXIC_OPI_CHIP 1
#define CONFIG_SPI_FLASH_ENABLE_ENCRYPTED_READ_WRITE 1
/* List of deprecated options */
@@ -473,24 +568,26 @@
#define CONFIG_BROWNOUT_DET_LVL_SEL_7 CONFIG_ESP_BROWNOUT_DET_LVL_SEL_7
#define CONFIG_COMPILER_OPTIMIZATION_DEFAULT CONFIG_COMPILER_OPTIMIZATION_DEBUG
#define CONFIG_COMPILER_OPTIMIZATION_LEVEL_DEBUG CONFIG_COMPILER_OPTIMIZATION_DEBUG
#define CONFIG_CONSOLE_UART CONFIG_ESP_CONSOLE_UART
#define CONFIG_CONSOLE_UART_BAUDRATE CONFIG_ESP_CONSOLE_UART_BAUDRATE
#define CONFIG_CONSOLE_UART_DEFAULT CONFIG_ESP_CONSOLE_UART_DEFAULT
#define CONFIG_CONSOLE_UART_NUM CONFIG_ESP_CONSOLE_UART_NUM
#define CONFIG_ESP32S2_ALLOW_RTC_FAST_MEM_AS_HEAP CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
#define CONFIG_ESP32S2_BROWNOUT_DET CONFIG_ESP_BROWNOUT_DET
#define CONFIG_ESP32S2_BROWNOUT_DET_LVL CONFIG_ESP_BROWNOUT_DET_LVL
#define CONFIG_ESP32S2_BROWNOUT_DET_LVL_SEL_7 CONFIG_ESP_BROWNOUT_DET_LVL_SEL_7
#define CONFIG_ESP32S2_DEBUG_OCDAWARE CONFIG_ESP_DEBUG_OCDAWARE
#define CONFIG_ESP32S2_DEFAULT_CPU_FREQ_160 CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_160
#define CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ
#define CONFIG_ESP32S2_MEMPROT_FEATURE CONFIG_ESP_SYSTEM_MEMPROT_FEATURE
#define CONFIG_ESP32S2_MEMPROT_FEATURE_LOCK CONFIG_ESP_SYSTEM_MEMPROT_FEATURE_LOCK
#define CONFIG_ESP32S2_PANIC_PRINT_REBOOT CONFIG_ESP_SYSTEM_PANIC_PRINT_REBOOT
#define CONFIG_ESP32S2_RTC_CLK_CAL_CYCLES CONFIG_RTC_CLK_CAL_CYCLES
#define CONFIG_ESP32S2_RTC_CLK_SRC_INT_RC CONFIG_RTC_CLK_SRC_INT_RC
#define CONFIG_ESP32S2_TIME_SYSCALL_USE_RTC_FRC1 CONFIG_NEWLIB_TIME_SYSCALL_USE_RTC_HRT
#define CONFIG_ESP32S2_TIME_SYSCALL_USE_RTC_SYSTIMER CONFIG_NEWLIB_TIME_SYSCALL_USE_RTC_HRT
#define CONFIG_ESP32S3_BROWNOUT_DET CONFIG_ESP_BROWNOUT_DET
#define CONFIG_ESP32S3_BROWNOUT_DET_LVL CONFIG_ESP_BROWNOUT_DET_LVL
#define CONFIG_ESP32S3_BROWNOUT_DET_LVL_SEL_7 CONFIG_ESP_BROWNOUT_DET_LVL_SEL_7
#define CONFIG_ESP32S3_DEBUG_OCDAWARE CONFIG_ESP_DEBUG_OCDAWARE
#define CONFIG_ESP32S3_DEEP_SLEEP_WAKEUP_DELAY CONFIG_ESP_SLEEP_WAIT_FLASH_READY_EXTRA_DELAY
#define CONFIG_ESP32S3_DEFAULT_CPU_FREQ_160 CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_160
#define CONFIG_ESP32S3_DEFAULT_CPU_FREQ_MHZ CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ
#define CONFIG_ESP32S3_RTC_CLK_CAL_CYCLES CONFIG_RTC_CLK_CAL_CYCLES
#define CONFIG_ESP32S3_RTC_CLK_SRC_INT_RC CONFIG_RTC_CLK_SRC_INT_RC
#define CONFIG_ESP32S3_TIME_SYSCALL_USE_RTC_FRC1 CONFIG_NEWLIB_TIME_SYSCALL_USE_RTC_HRT
#define CONFIG_ESP32S3_TIME_SYSCALL_USE_RTC_SYSTIMER CONFIG_NEWLIB_TIME_SYSCALL_USE_RTC_HRT
#define CONFIG_ESP_SLEEP_DEEP_SLEEP_WAKEUP_DELAY CONFIG_ESP_SLEEP_WAIT_FLASH_READY_EXTRA_DELAY
#define CONFIG_ESP_TASK_WDT CONFIG_ESP_TASK_WDT_INIT
#define CONFIG_FLASHMODE_DIO CONFIG_ESPTOOLPY_FLASHMODE_DIO
#define CONFIG_INT_WDT CONFIG_ESP_INT_WDT
#define CONFIG_INT_WDT_CHECK_CPU1 CONFIG_ESP_INT_WDT_CHECK_CPU1
#define CONFIG_INT_WDT_TIMEOUT_MS CONFIG_ESP_INT_WDT_TIMEOUT_MS
#define CONFIG_IPC_TASK_STACK_SIZE CONFIG_ESP_IPC_TASK_STACK_SIZE
#define CONFIG_LOG_BOOTLOADER_LEVEL CONFIG_BOOTLOADER_LOG_LEVEL
@@ -506,6 +603,7 @@
#define CONFIG_SYSTEM_EVENT_TASK_STACK_SIZE CONFIG_ESP_SYSTEM_EVENT_TASK_STACK_SIZE
#define CONFIG_TASK_WDT CONFIG_ESP_TASK_WDT_INIT
#define CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU0 CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU0
#define CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU1 CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU1
#define CONFIG_TASK_WDT_TIMEOUT_S CONFIG_ESP_TASK_WDT_TIMEOUT_S
#define CONFIG_TIMER_QUEUE_LENGTH CONFIG_FREERTOS_TIMER_QUEUE_LENGTH
#define CONFIG_TIMER_TASK_PRIORITY CONFIG_FREERTOS_TIMER_TASK_PRIORITY

348
build/bootloader/config/sdkconfig.json
View File

@@ -29,7 +29,7 @@
"BOOTLOADER_LOG_LEVEL_NONE": false,
"BOOTLOADER_LOG_LEVEL_VERBOSE": false,
"BOOTLOADER_LOG_LEVEL_WARN": false,
"BOOTLOADER_OFFSET_IN_FLASH": 4096,
"BOOTLOADER_OFFSET_IN_FLASH": 0,
"BOOTLOADER_PROJECT_VER": 1,
"BOOTLOADER_REGION_PROTECTION_ENABLE": true,
"BOOTLOADER_RESERVE_RTC_SIZE": 0,
@@ -70,29 +70,38 @@
"EFUSE_CUSTOM_TABLE": false,
"EFUSE_MAX_BLK_LEN": 256,
"EFUSE_VIRTUAL": false,
"ESP32S2_DATA_CACHE_0KB": false,
"ESP32S2_DATA_CACHE_16KB": false,
"ESP32S2_DATA_CACHE_8KB": true,
"ESP32S2_DATA_CACHE_LINE_16B": false,
"ESP32S2_DATA_CACHE_LINE_32B": true,
"ESP32S2_DATA_CACHE_WRAP": false,
"ESP32S2_INSTRUCTION_CACHE_16KB": false,
"ESP32S2_INSTRUCTION_CACHE_8KB": true,
"ESP32S2_INSTRUCTION_CACHE_LINE_16B": false,
"ESP32S2_INSTRUCTION_CACHE_LINE_32B": true,
"ESP32S2_INSTRUCTION_CACHE_WRAP": false,
"ESP32S2_KEEP_USB_ALIVE": true,
"ESP32S2_REV_MAX_FULL": 199,
"ESP32S2_REV_MIN_0": true,
"ESP32S2_REV_MIN_1": false,
"ESP32S2_REV_MIN_FULL": 0,
"ESP32S2_RTCDATA_IN_FAST_MEM": false,
"ESP32S2_TRACEMEM_RESERVE_DRAM": 0,
"ESP32S2_TRAX": false,
"ESP32S2_UNIVERSAL_MAC_ADDRESSES": 2,
"ESP32S2_UNIVERSAL_MAC_ADDRESSES_ONE": false,
"ESP32S2_UNIVERSAL_MAC_ADDRESSES_TWO": true,
"ESP32S2_USE_FIXED_STATIC_RAM_SIZE": false,
"ESP32S3_DATA_CACHE_16KB": false,
"ESP32S3_DATA_CACHE_32KB": true,
"ESP32S3_DATA_CACHE_4WAYS": false,
"ESP32S3_DATA_CACHE_64KB": false,
"ESP32S3_DATA_CACHE_8WAYS": true,
"ESP32S3_DATA_CACHE_LINE_16B": false,
"ESP32S3_DATA_CACHE_LINE_32B": true,
"ESP32S3_DATA_CACHE_LINE_64B": false,
"ESP32S3_DATA_CACHE_LINE_SIZE": 32,
"ESP32S3_DATA_CACHE_SIZE": 32768,
"ESP32S3_DCACHE_ASSOCIATED_WAYS": 8,
"ESP32S3_ICACHE_ASSOCIATED_WAYS": 8,
"ESP32S3_INSTRUCTION_CACHE_16KB": true,
"ESP32S3_INSTRUCTION_CACHE_32KB": false,
"ESP32S3_INSTRUCTION_CACHE_4WAYS": false,
"ESP32S3_INSTRUCTION_CACHE_8WAYS": true,
"ESP32S3_INSTRUCTION_CACHE_LINE_16B": false,
"ESP32S3_INSTRUCTION_CACHE_LINE_32B": true,
"ESP32S3_INSTRUCTION_CACHE_LINE_SIZE": 32,
"ESP32S3_INSTRUCTION_CACHE_SIZE": 16384,
"ESP32S3_REV_MAX_FULL": 99,
"ESP32S3_REV_MIN_0": true,
"ESP32S3_REV_MIN_1": false,
"ESP32S3_REV_MIN_2": false,
"ESP32S3_REV_MIN_FULL": 0,
"ESP32S3_RTCDATA_IN_FAST_MEM": false,
"ESP32S3_TRACEMEM_RESERVE_DRAM": 0,
"ESP32S3_TRAX": false,
"ESP32S3_UNIVERSAL_MAC_ADDRESSES": 4,
"ESP32S3_UNIVERSAL_MAC_ADDRESSES_FOUR": true,
"ESP32S3_UNIVERSAL_MAC_ADDRESSES_TWO": false,
"ESP32S3_USE_FIXED_STATIC_RAM_SIZE": false,
"ESPTOOLPY_AFTER": "hard_reset",
"ESPTOOLPY_AFTER_NORESET": false,
"ESPTOOLPY_AFTER_RESET": true,
@@ -100,8 +109,8 @@
"ESPTOOLPY_BEFORE_NORESET": false,
"ESPTOOLPY_BEFORE_RESET": true,
"ESPTOOLPY_FLASHFREQ": "80m",
"ESPTOOLPY_FLASHFREQ_120M": false,
"ESPTOOLPY_FLASHFREQ_20M": false,
"ESPTOOLPY_FLASHFREQ_26M": false,
"ESPTOOLPY_FLASHFREQ_40M": false,
"ESPTOOLPY_FLASHFREQ_80M": true,
"ESPTOOLPY_FLASHFREQ_80M_DEFAULT": true,
@@ -110,19 +119,21 @@
"ESPTOOLPY_FLASHMODE_DOUT": false,
"ESPTOOLPY_FLASHMODE_QIO": false,
"ESPTOOLPY_FLASHMODE_QOUT": false,
"ESPTOOLPY_FLASHSIZE": "4MB",
"ESPTOOLPY_FLASHSIZE": "2MB",
"ESPTOOLPY_FLASHSIZE_128MB": false,
"ESPTOOLPY_FLASHSIZE_16MB": false,
"ESPTOOLPY_FLASHSIZE_1MB": false,
"ESPTOOLPY_FLASHSIZE_2MB": false,
"ESPTOOLPY_FLASHSIZE_2MB": true,
"ESPTOOLPY_FLASHSIZE_32MB": false,
"ESPTOOLPY_FLASHSIZE_4MB": true,
"ESPTOOLPY_FLASHSIZE_4MB": false,
"ESPTOOLPY_FLASHSIZE_64MB": false,
"ESPTOOLPY_FLASHSIZE_8MB": false,
"ESPTOOLPY_FLASH_MODE_AUTO_DETECT": true,
"ESPTOOLPY_FLASH_SAMPLE_MODE_STR": true,
"ESPTOOLPY_HEADER_FLASHSIZE_UPDATE": false,
"ESPTOOLPY_MONITOR_BAUD": 115200,
"ESPTOOLPY_NO_STUB": false,
"ESPTOOLPY_OCT_FLASH": false,
"ESP_BROWNOUT_DET": true,
"ESP_BROWNOUT_DET_LVL": 7,
"ESP_BROWNOUT_DET_LVL_SEL_1": false,
@@ -133,12 +144,16 @@
"ESP_BROWNOUT_DET_LVL_SEL_6": false,
"ESP_BROWNOUT_DET_LVL_SEL_7": true,
"ESP_CONSOLE_NONE": false,
"ESP_CONSOLE_SECONDARY_NONE": false,
"ESP_CONSOLE_SECONDARY_USB_SERIAL_JTAG": true,
"ESP_CONSOLE_UART": true,
"ESP_CONSOLE_UART_BAUDRATE": 115200,
"ESP_CONSOLE_UART_CUSTOM": false,
"ESP_CONSOLE_UART_DEFAULT": false,
"ESP_CONSOLE_UART_NUM": -1,
"ESP_CONSOLE_USB_CDC": true,
"ESP_CONSOLE_USB_CDC_RX_BUF_SIZE": 64,
"ESP_CONSOLE_USB_CDC_SUPPORT_ETS_PRINTF": true,
"ESP_CONSOLE_UART_DEFAULT": true,
"ESP_CONSOLE_UART_NUM": 0,
"ESP_CONSOLE_USB_CDC": false,
"ESP_CONSOLE_USB_SERIAL_JTAG": false,
"ESP_CONSOLE_USB_SERIAL_JTAG_ENABLED": true,
"ESP_DEBUG_OCDAWARE": true,
"ESP_DEBUG_STUBS_ENABLE": false,
"ESP_DEFAULT_CPU_FREQ_MHZ": 160,
@@ -147,40 +162,59 @@
"ESP_DEFAULT_CPU_FREQ_MHZ_80": false,
"ESP_ERR_TO_NAME_LOOKUP": true,
"ESP_INT_WDT": true,
"ESP_INT_WDT_CHECK_CPU1": true,
"ESP_INT_WDT_TIMEOUT_MS": 300,
"ESP_IPC_TASK_STACK_SIZE": 1024,
"ESP_IPC_ISR_ENABLE": true,
"ESP_IPC_TASK_STACK_SIZE": 1280,
"ESP_IPC_USES_CALLERS_PRIORITY": true,
"ESP_MAC_ADDR_UNIVERSE_BT": true,
"ESP_MAC_ADDR_UNIVERSE_ETH": true,
"ESP_MAC_ADDR_UNIVERSE_WIFI_AP": true,
"ESP_MAC_ADDR_UNIVERSE_WIFI_STA": true,
"ESP_MAC_UNIVERSAL_MAC_ADDRESSES_TWO": true,
"ESP_MAC_UNIVERSAL_MAC_ADDRESSES_FOUR": true,
"ESP_MAC_USE_CUSTOM_MAC_AS_BASE_MAC": false,
"ESP_MAIN_TASK_AFFINITY": 0,
"ESP_MAIN_TASK_AFFINITY_CPU0": true,
"ESP_MAIN_TASK_AFFINITY_CPU1": false,
"ESP_MAIN_TASK_AFFINITY_NO_AFFINITY": false,
"ESP_MAIN_TASK_STACK_SIZE": 3584,
"ESP_MINIMAL_SHARED_STACK_SIZE": 2048,
"ESP_PANIC_HANDLER_IRAM": false,
"ESP_REV_MAX_FULL": 199,
"ESP_REV_MAX_FULL": 99,
"ESP_REV_MIN_FULL": 0,
"ESP_ROM_GET_CLK_FREQ": true,
"ESP_ROM_HAS_CACHE_SUSPEND_WAITI_BUG": true,
"ESP_ROM_HAS_CACHE_WRITEBACK_BUG": true,
"ESP_ROM_HAS_CRC_BE": true,
"ESP_ROM_HAS_CRC_LE": true,
"ESP_ROM_HAS_ERASE_0_REGION_BUG": true,
"ESP_ROM_HAS_ETS_PRINTF_BUG": true,
"ESP_ROM_HAS_FLASH_COUNT_PAGES_BUG": true,
"ESP_ROM_HAS_HAL_WDT": true,
"ESP_ROM_HAS_JPEG_DECODE": true,
"ESP_ROM_HAS_LAYOUT_TABLE": true,
"ESP_ROM_HAS_MZ_CRC32": true,
"ESP_ROM_HAS_NEWLIB_NANO_FORMAT": true,
"ESP_ROM_HAS_REGI2C_BUG": true,
"ESP_ROM_HAS_RETARGETABLE_LOCKING": true,
"ESP_ROM_HAS_SPI_FLASH": true,
"ESP_ROM_HAS_SW_FLOAT": true,
"ESP_ROM_HAS_UART_BUF_SWITCH": true,
"ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE": true,
"ESP_ROM_NEEDS_SWSETUP_WORKAROUND": true,
"ESP_ROM_RAM_APP_NEEDS_MMU_INIT": true,
"ESP_ROM_UART_CLK_IS_XTAL": true,
"ESP_ROM_USB_OTG_NUM": 3,
"ESP_ROM_USB_SERIAL_DEVICE_NUM": -1,
"ESP_ROM_USB_SERIAL_DEVICE_NUM": 4,
"ESP_SLEEP_CACHE_SAFE_ASSERTION": false,
"ESP_SLEEP_DEBUG": false,
"ESP_SLEEP_FLASH_LEAKAGE_WORKAROUND": true,
"ESP_SLEEP_GPIO_ENABLE_INTERNAL_RESISTORS": true,
"ESP_SLEEP_GPIO_RESET_WORKAROUND": false,
"ESP_SLEEP_MSPI_NEED_ALL_IO_PU": false,
"ESP_SLEEP_GPIO_RESET_WORKAROUND": true,
"ESP_SLEEP_MSPI_NEED_ALL_IO_PU": true,
"ESP_SLEEP_POWER_DOWN_FLASH": false,
"ESP_SLEEP_RTC_BUS_ISO_WORKAROUND": true,
"ESP_SLEEP_WAIT_FLASH_READY_EXTRA_DELAY": 0,
"ESP_SLEEP_WAIT_FLASH_READY_EXTRA_DELAY": 2000,
"ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP": true,
"ESP_SYSTEM_BBPLL_RECALIB": true,
"ESP_SYSTEM_BROWNOUT_INTR": true,
"ESP_SYSTEM_CHECK_INT_LEVEL_4": true,
"ESP_SYSTEM_EVENT_QUEUE_SIZE": 32,
@@ -193,8 +227,8 @@
"ESP_SYSTEM_PANIC_REBOOT_DELAY_SECONDS": 0,
"ESP_SYSTEM_PANIC_SILENT_REBOOT": false,
"ESP_SYSTEM_RTC_FAST_MEM_AS_HEAP_DEPCHECK": true,
"ESP_SYSTEM_SINGLE_CORE_MODE": true,
"ESP_TASK_WDT_CHECK_IDLE_TASK_CPU0": true,
"ESP_TASK_WDT_CHECK_IDLE_TASK_CPU1": true,
"ESP_TASK_WDT_EN": true,
"ESP_TASK_WDT_INIT": true,
"ESP_TASK_WDT_PANIC": false,
@@ -204,8 +238,8 @@
"FREERTOS_CHECK_STACKOVERFLOW_CANARY": true,
"FREERTOS_CHECK_STACKOVERFLOW_NONE": false,
"FREERTOS_CHECK_STACKOVERFLOW_PTRVAL": false,
"FREERTOS_CORETIMER_0": true,
"FREERTOS_CORETIMER_1": false,
"FREERTOS_CORETIMER_SYSTIMER_LVL1": true,
"FREERTOS_CORETIMER_SYSTIMER_LVL3": false,
"FREERTOS_DEBUG_OCDAWARE": true,
"FREERTOS_ENABLE_BACKWARD_COMPATIBILITY": false,
"FREERTOS_ENABLE_STATIC_TASK_CLEAN_UP": false,
@@ -217,42 +251,45 @@
"FREERTOS_ISR_STACKSIZE": 1536,
"FREERTOS_MAX_TASK_NAME_LEN": 16,
"FREERTOS_NO_AFFINITY": 2147483647,
"FREERTOS_OPTIMIZED_SCHEDULER": true,
"FREERTOS_PLACE_FUNCTIONS_INTO_FLASH": false,
"FREERTOS_PLACE_SNAPSHOT_FUNS_INTO_FLASH": true,
"FREERTOS_PORT": true,
"FREERTOS_QUEUE_REGISTRY_SIZE": 0,
"FREERTOS_SMP": false,
"FREERTOS_SUPPORT_STATIC_ALLOCATION": true,
"FREERTOS_SYSTICK_USES_CCOUNT": true,
"FREERTOS_SYSTICK_USES_SYSTIMER": true,
"FREERTOS_TASK_FUNCTION_WRAPPER": true,
"FREERTOS_TASK_NOTIFICATION_ARRAY_ENTRIES": 1,
"FREERTOS_TASK_PRE_DELETION_HOOK": false,
"FREERTOS_THREAD_LOCAL_STORAGE_POINTERS": 1,
"FREERTOS_TICK_SUPPORT_CORETIMER": true,
"FREERTOS_TICK_SUPPORT_SYSTIMER": true,
"FREERTOS_TIMER_QUEUE_LENGTH": 10,
"FREERTOS_TIMER_SERVICE_TASK_NAME": "Tmr Svc",
"FREERTOS_TIMER_TASK_PRIORITY": 1,
"FREERTOS_TIMER_TASK_STACK_DEPTH": 2048,
"FREERTOS_TLSP_DELETION_CALLBACKS": true,
"FREERTOS_UNICORE": true,
"FREERTOS_UNICORE": false,
"FREERTOS_USE_IDLE_HOOK": false,
"FREERTOS_USE_TICK_HOOK": false,
"FREERTOS_USE_TRACE_FACILITY": false,
"FREERTOS_WATCHPOINT_END_OF_STACK": false,
"GDMA_CTRL_FUNC_IN_IRAM": false,
"GDMA_ENABLE_DEBUG_LOG": false,
"GDMA_ISR_IRAM_SAFE": false,
"HAL_ASSERTION_DISABLE": false,
"HAL_ASSERTION_ENABLE": false,
"HAL_ASSERTION_EQUALS_SYSTEM": true,
"HAL_ASSERTION_SILENT": false,
"HAL_DEFAULT_ASSERTION_LEVEL": 2,
"HAL_WDT_USE_ROM_IMPL": true,
"IDF_CMAKE": true,
"IDF_EXPERIMENTAL_FEATURES": false,
"IDF_FIRMWARE_CHIP_ID": 2,
"IDF_FIRMWARE_CHIP_ID": 9,
"IDF_INIT_VERSION": "5.2.1",
"IDF_TARGET": "esp32s2",
"IDF_TARGET": "esp32s3",
"IDF_TARGET_ARCH": "xtensa",
"IDF_TARGET_ARCH_XTENSA": true,
"IDF_TARGET_ESP32S2": true,
"IDF_TARGET_ESP32S3": true,
"IDF_TOOLCHAIN": "gcc",
"LOG_COLORS": true,
"LOG_DEFAULT_LEVEL": 3,
@@ -283,16 +320,16 @@
"NEWLIB_TIME_SYSCALL_USE_NONE": false,
"NEWLIB_TIME_SYSCALL_USE_RTC": false,
"NEWLIB_TIME_SYSCALL_USE_RTC_HRT": true,
"PARTITION_TABLE_CUSTOM": true,
"PARTITION_TABLE_CUSTOM": false,
"PARTITION_TABLE_CUSTOM_FILENAME": "partitions.csv",
"PARTITION_TABLE_FILENAME": "partitions.csv",
"PARTITION_TABLE_FILENAME": "partitions_singleapp.csv",
"PARTITION_TABLE_MD5": true,
"PARTITION_TABLE_OFFSET": 32768,
"PARTITION_TABLE_SINGLE_APP": false,
"PARTITION_TABLE_SINGLE_APP": true,
"PARTITION_TABLE_SINGLE_APP_LARGE": false,
"PARTITION_TABLE_TWO_OTA": false,
"PERIPH_CTRL_FUNC_IN_IRAM": true,
"RTC_CLK_CAL_CYCLES": 576,
"RTC_CLK_CAL_CYCLES": 1024,
"RTC_CLK_SRC_EXT_CRYS": false,
"RTC_CLK_SRC_EXT_OSC": false,
"RTC_CLK_SRC_INT_8MD256": false,
@@ -307,42 +344,50 @@
"SOC_ADC_ATTEN_NUM": 4,
"SOC_ADC_CALIBRATION_V1_SUPPORTED": true,
"SOC_ADC_DIGI_CONTROLLER_NUM": 2,
"SOC_ADC_DIGI_DATA_BYTES_PER_CONV": 2,
"SOC_ADC_DIGI_DATA_BYTES_PER_CONV": 4,
"SOC_ADC_DIGI_IIR_FILTER_NUM": 2,
"SOC_ADC_DIGI_MAX_BITWIDTH": 12,
"SOC_ADC_DIGI_MIN_BITWIDTH": 12,
"SOC_ADC_DIGI_MONITOR_NUM": 2,
"SOC_ADC_DIGI_RESULT_BYTES": 2,
"SOC_ADC_DIGI_RESULT_BYTES": 4,
"SOC_ADC_DIG_CTRL_SUPPORTED": true,
"SOC_ADC_DIG_IIR_FILTER_SUPPORTED": true,
"SOC_ADC_DIG_IIR_FILTER_UNIT_BINDED": true,
"SOC_ADC_DMA_SUPPORTED": true,
"SOC_ADC_MAX_CHANNEL_NUM": 10,
"SOC_ADC_MONITOR_SUPPORTED": true,
"SOC_ADC_PATT_LEN_MAX": 32,
"SOC_ADC_PATT_LEN_MAX": 24,
"SOC_ADC_PERIPH_NUM": 2,
"SOC_ADC_RTC_CTRL_SUPPORTED": true,
"SOC_ADC_RTC_MAX_BITWIDTH": 13,
"SOC_ADC_RTC_MIN_BITWIDTH": 13,
"SOC_ADC_RTC_MAX_BITWIDTH": 12,
"SOC_ADC_RTC_MIN_BITWIDTH": 12,
"SOC_ADC_SAMPLE_FREQ_THRES_HIGH": 83333,
"SOC_ADC_SAMPLE_FREQ_THRES_LOW": 611,
"SOC_ADC_SELF_HW_CALI_SUPPORTED": true,
"SOC_ADC_SHARED_POWER": true,
"SOC_ADC_SUPPORTED": true,
"SOC_AES_CRYPTO_DMA": true,
"SOC_AES_GDMA": true,
"SOC_AES_SUPPORTED": true,
"SOC_AES_SUPPORT_AES_128": true,
"SOC_AES_SUPPORT_AES_192": true,
"SOC_AES_SUPPORT_AES_256": true,
"SOC_AES_SUPPORT_DMA": true,
"SOC_AES_SUPPORT_GCM": true,
"SOC_AHB_GDMA_SUPPORTED": true,
"SOC_AHB_GDMA_SUPPORT_PSRAM": true,
"SOC_AHB_GDMA_VERSION": 1,
"SOC_APB_BACKUP_DMA": true,
"SOC_APPCPU_HAS_CLOCK_GATING_BUG": true,
"SOC_ASYNC_MEMCPY_SUPPORTED": true,
"SOC_BLE_50_SUPPORTED": true,
"SOC_BLE_DEVICE_PRIVACY_SUPPORTED": true,
"SOC_BLE_MESH_SUPPORTED": true,
"SOC_BLE_SUPPORTED": true,
"SOC_BLUFI_SUPPORTED": true,
"SOC_BOD_SUPPORTED": true,
"SOC_BROWNOUT_RESET_SUPPORTED": true,
"SOC_BT_SUPPORTED": true,
"SOC_CACHE_FREEZE_SUPPORTED": true,
"SOC_CACHE_SUPPORT_WRAP": true,
"SOC_CACHE_WRITEBACK_SUPPORTED": true,
"SOC_CCOMP_TIMER_SUPPORTED": true,
"SOC_CLK_APLL_SUPPORTED": true,
"SOC_CLK_RC_FAST_D256_SUPPORTED": true,
"SOC_CLK_RC_FAST_SUPPORT_CALIBRATION": true,
"SOC_CLK_TREE_SUPPORTED": true,
@@ -350,27 +395,25 @@
"SOC_COEX_HW_PTI": true,
"SOC_CONFIGURABLE_VDDSDIO_SUPPORTED": true,
"SOC_CPU_BREAKPOINTS_NUM": 2,
"SOC_CPU_CORES_NUM": 1,
"SOC_CPU_CORES_NUM": 2,
"SOC_CPU_HAS_FPU": true,
"SOC_CPU_INTR_NUM": 32,
"SOC_CPU_WATCHPOINTS_NUM": 2,
"SOC_CPU_WATCHPOINT_MAX_REGION_SIZE": 64,
"SOC_CP_DMA_MAX_BUFFER_SIZE": 4095,
"SOC_CP_DMA_SUPPORTED": true,
"SOC_DAC_CHAN_NUM": 2,
"SOC_DAC_RESOLUTION": 8,
"SOC_DAC_SUPPORTED": true,
"SOC_DEDICATED_GPIO_SUPPORTED": true,
"SOC_DEDIC_GPIO_ALLOW_REG_ACCESS": true,
"SOC_DEDIC_GPIO_HAS_INTERRUPT": true,
"SOC_DEDIC_GPIO_IN_CHANNELS_NUM": 8,
"SOC_DEDIC_GPIO_OUT_AUTO_ENABLE": true,
"SOC_DEDIC_GPIO_OUT_CHANNELS_NUM": 8,
"SOC_DIG_SIGN_SUPPORTED": true,
"SOC_EFUSE_DIS_BOOT_REMAP": true,
"SOC_DS_KEY_CHECK_MAX_WAIT_US": 1100,
"SOC_DS_KEY_PARAM_MD_IV_LENGTH": 16,
"SOC_DS_SIGNATURE_MAX_BIT_LEN": 4096,
"SOC_EFUSE_BLOCK9_KEY_PURPOSE_QUIRK": true,
"SOC_EFUSE_DIS_DIRECT_BOOT": true,
"SOC_EFUSE_DIS_DOWNLOAD_DCACHE": true,
"SOC_EFUSE_DIS_DOWNLOAD_ICACHE": true,
"SOC_EFUSE_DIS_ICACHE": true,
"SOC_EFUSE_DIS_LEGACY_SPI_BOOT": true,
"SOC_EFUSE_DIS_USB_JTAG": true,
"SOC_EFUSE_HARD_DIS_JTAG": true,
"SOC_EFUSE_KEY_PURPOSE_FIELD": true,
"SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS": true,
@@ -384,59 +427,86 @@
"SOC_FLASH_ENCRYPTION_XTS_AES_256": true,
"SOC_FLASH_ENCRYPTION_XTS_AES_OPTIONS": true,
"SOC_FLASH_ENC_SUPPORTED": true,
"SOC_GDMA_NUM_GROUPS_MAX": 1,
"SOC_GDMA_PAIRS_PER_GROUP": 5,
"SOC_GDMA_PAIRS_PER_GROUP_MAX": 5,
"SOC_GDMA_SUPPORTED": true,
"SOC_GPIO_CLOCKOUT_BY_IO_MUX": true,
"SOC_GPIO_FILTER_CLK_SUPPORT_APB": true,
"SOC_GPIO_IN_RANGE_MAX": 46,
"SOC_GPIO_OUT_RANGE_MAX": 45,
"SOC_GPIO_PIN_COUNT": 47,
"SOC_GPIO_IN_RANGE_MAX": 48,
"SOC_GPIO_OUT_RANGE_MAX": 48,
"SOC_GPIO_PIN_COUNT": 49,
"SOC_GPIO_PORT": 1,
"SOC_GPIO_SUPPORT_FORCE_HOLD": true,
"SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER": true,
"SOC_GPIO_SUPPORT_RTC_INDEPENDENT": true,
"SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK": 140737421246464,
"SOC_GPIO_VALID_GPIO_MASK": 140737488355327,
"SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK": 562949886312448,
"SOC_GPIO_VALID_GPIO_MASK": 562949953421311,
"SOC_GPSPI_SUPPORTED": true,
"SOC_GPTIMER_SUPPORTED": true,
"SOC_HMAC_SUPPORTED": true,
"SOC_I2C_CMD_REG_NUM": 16,
"SOC_HP_CPU_HAS_MULTIPLE_CORES": true,
"SOC_I2C_CMD_REG_NUM": 8,
"SOC_I2C_FIFO_LEN": 32,
"SOC_I2C_NUM": 2,
"SOC_I2C_SLAVE_SUPPORT_BROADCAST": true,
"SOC_I2C_SLAVE_SUPPORT_I2CRAM_ACCESS": true,
"SOC_I2C_SUPPORTED": true,
"SOC_I2C_SUPPORT_APB": true,
"SOC_I2C_SUPPORT_10BIT_ADDR": true,
"SOC_I2C_SUPPORT_HW_CLR_BUS": true,
"SOC_I2C_SUPPORT_REF_TICK": true,
"SOC_I2C_SUPPORT_RTC": true,
"SOC_I2C_SUPPORT_SLAVE": true,
"SOC_I2S_APLL_MAX_FREQ": 500000000,
"SOC_I2S_APLL_MIN_FREQ": 250000000,
"SOC_I2S_APLL_MIN_RATE": 10675,
"SOC_I2S_HW_VERSION_1": true,
"SOC_I2S_LCD_I80_VARIANT": true,
"SOC_I2S_NUM": 1,
"SOC_I2C_SUPPORT_XTAL": true,
"SOC_I2S_HW_VERSION_2": true,
"SOC_I2S_NUM": 2,
"SOC_I2S_PDM_MAX_RX_LINES": 4,
"SOC_I2S_PDM_MAX_TX_LINES": 2,
"SOC_I2S_SUPPORTED": true,
"SOC_I2S_SUPPORTS_APLL": true,
"SOC_I2S_SUPPORTS_DMA_EQUAL": true,
"SOC_I2S_SUPPORTS_LCD_CAMERA": true,
"SOC_I2S_SUPPORTS_PCM": true,
"SOC_I2S_SUPPORTS_PDM": true,
"SOC_I2S_SUPPORTS_PDM_RX": true,
"SOC_I2S_SUPPORTS_PDM_TX": true,
"SOC_I2S_SUPPORTS_PLL_F160M": true,
"SOC_I2S_SUPPORTS_TDM": true,
"SOC_I2S_SUPPORTS_XTAL": true,
"SOC_LCDCAM_SUPPORTED": true,
"SOC_LCD_I80_BUSES": 1,
"SOC_LCD_I80_BUS_WIDTH": 24,
"SOC_LCD_I80_BUS_WIDTH": 16,
"SOC_LCD_I80_SUPPORTED": true,
"SOC_LCD_RGB_DATA_WIDTH": 16,
"SOC_LCD_RGB_PANELS": 1,
"SOC_LCD_RGB_SUPPORTED": true,
"SOC_LCD_SUPPORT_RGB_YUV_CONV": true,
"SOC_LEDC_CHANNEL_NUM": 8,
"SOC_LEDC_HAS_TIMER_SPECIFIC_MUX": true,
"SOC_LEDC_SUPPORTED": true,
"SOC_LEDC_SUPPORT_APB_CLOCK": true,
"SOC_LEDC_SUPPORT_FADE_STOP": true,
"SOC_LEDC_SUPPORT_REF_TICK": true,
"SOC_LEDC_SUPPORT_XTAL_CLOCK": true,
"SOC_LEDC_TIMER_BIT_WIDTH": 14,
"SOC_MAC_BB_PD_MEM_SIZE": 192,
"SOC_MCPWM_CAPTURE_CHANNELS_PER_TIMER": 3,
"SOC_MCPWM_CAPTURE_TIMERS_PER_GROUP": true,
"SOC_MCPWM_COMPARATORS_PER_OPERATOR": 2,
"SOC_MCPWM_GENERATORS_PER_OPERATOR": 2,
"SOC_MCPWM_GPIO_FAULTS_PER_GROUP": 3,
"SOC_MCPWM_GPIO_SYNCHROS_PER_GROUP": 3,
"SOC_MCPWM_GROUPS": 2,
"SOC_MCPWM_OPERATORS_PER_GROUP": 3,
"SOC_MCPWM_SUPPORTED": true,
"SOC_MCPWM_SWSYNC_CAN_PROPAGATE": true,
"SOC_MCPWM_TIMERS_PER_GROUP": 3,
"SOC_MCPWM_TRIGGERS_PER_OPERATOR": 2,
"SOC_MEMPROT_CPU_PREFETCH_PAD_SIZE": 16,
"SOC_MEMPROT_MEM_ALIGN_SIZE": 4,
"SOC_MEMPROT_MEM_ALIGN_SIZE": 256,
"SOC_MEMPROT_SUPPORTED": true,
"SOC_MEMSPI_CORE_CLK_SHARED_WITH_PSRAM": true,
"SOC_MEMSPI_IS_INDEPENDENT": true,
"SOC_MEMSPI_SRC_FREQ_120M": true,
"SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED": true,
"SOC_MEMSPI_SRC_FREQ_26M_SUPPORTED": true,
"SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED": true,
"SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED": true,
"SOC_MMU_LINEAR_ADDRESS_REGION_NUM": 5,
"SOC_MEMSPI_TIMING_TUNING_BY_MSPI_DELAY": true,
"SOC_MMU_LINEAR_ADDRESS_REGION_NUM": 1,
"SOC_MMU_PERIPH_NUM": 1,
"SOC_MPI_MEM_BLOCKS_NUM": 4,
"SOC_MPI_OPERATIONS_NUM": 3,
@@ -449,51 +519,68 @@
"SOC_PCNT_SUPPORTED": true,
"SOC_PCNT_THRES_POINT_PER_UNIT": 2,
"SOC_PCNT_UNITS_PER_GROUP": 4,
"SOC_PHY_COMBO_MODULE": true,
"SOC_PHY_DIG_REGS_MEM_SIZE": 21,
"SOC_PM_CPU_RETENTION_BY_RTCCNTL": true,
"SOC_PM_MODEM_RETENTION_BY_BACKUPDMA": true,
"SOC_PM_SUPPORT_BT_WAKEUP": true,
"SOC_PM_SUPPORT_CPU_PD": true,
"SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY": true,
"SOC_PM_SUPPORT_EXT0_WAKEUP": true,
"SOC_PM_SUPPORT_EXT1_WAKEUP": true,
"SOC_PM_SUPPORT_EXT_WAKEUP": true,
"SOC_PM_SUPPORT_MAC_BB_PD": true,
"SOC_PM_SUPPORT_MODEM_PD": true,
"SOC_PM_SUPPORT_RC_FAST_PD": true,
"SOC_PM_SUPPORT_RTC_FAST_MEM_PD": true,
"SOC_PM_SUPPORT_RTC_PERIPH_PD": true,
"SOC_PM_SUPPORT_RTC_SLOW_MEM_PD": true,
"SOC_PM_SUPPORT_TAGMEM_PD": true,
"SOC_PM_SUPPORT_TOUCH_SENSOR_WAKEUP": true,
"SOC_PM_SUPPORT_VDDSDIO_PD": true,
"SOC_PM_SUPPORT_WIFI_PD": true,
"SOC_PM_SUPPORT_WIFI_WAKEUP": true,
"SOC_PSRAM_DMA_CAPABLE": true,
"SOC_RISCV_COPROC_SUPPORTED": true,
"SOC_RMT_CHANNELS_PER_GROUP": 4,
"SOC_RMT_CHANNEL_CLK_INDEPENDENT": true,
"SOC_RMT_CHANNELS_PER_GROUP": 8,
"SOC_RMT_GROUPS": 1,
"SOC_RMT_MEM_WORDS_PER_CHANNEL": 64,
"SOC_RMT_MEM_WORDS_PER_CHANNEL": 48,
"SOC_RMT_RX_CANDIDATES_PER_GROUP": 4,
"SOC_RMT_SUPPORTED": true,
"SOC_RMT_SUPPORT_APB": true,
"SOC_RMT_SUPPORT_REF_TICK": true,
"SOC_RMT_SUPPORT_DMA": true,
"SOC_RMT_SUPPORT_RC_FAST": true,
"SOC_RMT_SUPPORT_RX_DEMODULATION": true,
"SOC_RMT_SUPPORT_RX_PINGPONG": true,
"SOC_RMT_SUPPORT_TX_ASYNC_STOP": true,
"SOC_RMT_SUPPORT_TX_CARRIER_DATA_ONLY": true,
"SOC_RMT_SUPPORT_TX_LOOP_AUTO_STOP": true,
"SOC_RMT_SUPPORT_TX_LOOP_COUNT": true,
"SOC_RMT_SUPPORT_TX_SYNCHRO": true,
"SOC_RMT_SUPPORT_XTAL": true,
"SOC_RMT_TX_CANDIDATES_PER_GROUP": 4,
"SOC_RSA_MAX_BIT_LEN": 4096,
"SOC_RTCIO_HOLD_SUPPORTED": true,
"SOC_RTCIO_INPUT_OUTPUT_SUPPORTED": true,
"SOC_RTCIO_PIN_COUNT": 22,
"SOC_RTCIO_WAKE_SUPPORTED": true,
"SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH": 128,
"SOC_RTC_CNTL_CPU_PD_REG_FILE_NUM": 549,
"SOC_RTC_CNTL_TAGMEM_PD_DMA_BUS_WIDTH": 128,
"SOC_RTC_FAST_MEM_SUPPORTED": true,
"SOC_RTC_MEM_SUPPORTED": true,
"SOC_RTC_SLOW_CLK_SUPPORT_RC_FAST_D256": true,
"SOC_RTC_SLOW_MEM_SUPPORTED": true,
"SOC_SDMMC_DELAY_PHASE_NUM": 4,
"SOC_SDMMC_HOST_SUPPORTED": true,
"SOC_SDMMC_NUM_SLOTS": 2,
"SOC_SDMMC_SUPPORT_XTAL_CLOCK": true,
"SOC_SDMMC_USE_GPIO_MATRIX": true,
"SOC_SDM_CHANNELS_PER_GROUP": 8,
"SOC_SDM_CLK_SUPPORT_APB": true,
"SOC_SDM_GROUPS": 1,
"SOC_SDM_GROUPS": true,
"SOC_SDM_SUPPORTED": true,
"SOC_SECURE_BOOT_SUPPORTED": true,
"SOC_SECURE_BOOT_V2_RSA": true,
"SOC_SHA_CRYPTO_DMA": true,
"SOC_SHA_DMA_MAX_BUFFER_SIZE": 3968,
"SOC_SHA_GDMA": true,
"SOC_SHA_SUPPORTED": true,
"SOC_SHA_SUPPORT_DMA": true,
"SOC_SHA_SUPPORT_RESUME": true,
@@ -507,36 +594,43 @@
"SOC_SHA_SUPPORT_SHA512_T": true,
"SOC_SPIRAM_SUPPORTED": true,
"SOC_SPIRAM_XIP_SUPPORTED": true,
"SOC_SPI_DMA_CHAN_NUM": 3,
"SOC_SPI_FLASH_SUPPORTED": true,
"SOC_SPI_HD_BOTH_INOUT_SUPPORTED": true,
"SOC_SPI_MAXIMUM_BUFFER_SIZE": 72,
"SOC_SPI_MAXIMUM_BUFFER_SIZE": 64,
"SOC_SPI_MAX_CS_NUM": 6,
"SOC_SPI_MAX_PRE_DIVIDER": 8192,
"SOC_SPI_MAX_PRE_DIVIDER": 16,
"SOC_SPI_MEM_SUPPORT_AUTO_RESUME": true,
"SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND": true,
"SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE": true,
"SOC_SPI_MEM_SUPPORT_CONFIG_GPIO_BY_EFUSE": true,
"SOC_SPI_MEM_SUPPORT_OPI_MODE": true,
"SOC_SPI_MEM_SUPPORT_SW_SUSPEND": true,
"SOC_SPI_MEM_SUPPORT_TIMING_TUNING": true,
"SOC_SPI_MEM_SUPPORT_WRAP": true,
"SOC_SPI_PERIPH_NUM": 3,
"SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUT": true,
"SOC_SPI_SLAVE_SUPPORT_SEG_TRANS": true,
"SOC_SPI_SUPPORT_CD_SIG": true,
"SOC_SPI_SUPPORT_CLK_APB": true,
"SOC_SPI_SUPPORT_CLK_XTAL": true,
"SOC_SPI_SUPPORT_CONTINUOUS_TRANS": true,
"SOC_SPI_SUPPORT_DDRCLK": true,
"SOC_SPI_SUPPORT_OCT": true,
"SOC_SPI_SUPPORT_SLAVE_HD_VER2": true,
"SOC_SUPPORTS_SECURE_DL_MODE": true,
"SOC_SUPPORT_COEXISTENCE": true,
"SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY": true,
"SOC_SYSTIMER_ALARM_MISS_COMPENSATE": true,
"SOC_SYSTIMER_ALARM_NUM": 3,
"SOC_SYSTIMER_BIT_WIDTH_HI": 32,
"SOC_SYSTIMER_BIT_WIDTH_HI": 20,
"SOC_SYSTIMER_BIT_WIDTH_LO": 32,
"SOC_SYSTIMER_COUNTER_NUM": true,
"SOC_SYSTIMER_COUNTER_NUM": 2,
"SOC_SYSTIMER_FIXED_DIVIDER": true,
"SOC_SYSTIMER_INT_LEVEL": true,
"SOC_SYSTIMER_SUPPORTED": true,
"SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC": true,
"SOC_TEMP_SENSOR_SUPPORTED": true,
"SOC_TIMER_GROUPS": 2,
"SOC_TIMER_GROUP_COUNTER_BIT_WIDTH": 64,
"SOC_TIMER_GROUP_COUNTER_BIT_WIDTH": 54,
"SOC_TIMER_GROUP_SUPPORT_APB": true,
"SOC_TIMER_GROUP_SUPPORT_XTAL": true,
"SOC_TIMER_GROUP_TIMERS_PER_GROUP": 2,
@@ -544,10 +638,11 @@
"SOC_TOUCH_PAD_MEASURE_WAIT_MAX": 255,
"SOC_TOUCH_PAD_THRESHOLD_MAX": 2097151,
"SOC_TOUCH_PROXIMITY_CHANNEL_NUM": 3,
"SOC_TOUCH_PROXIMITY_MEAS_DONE_SUPPORTED": true,
"SOC_TOUCH_SENSOR_NUM": 15,
"SOC_TOUCH_SENSOR_SUPPORTED": true,
"SOC_TOUCH_VERSION_2": true,
"SOC_TWAI_BRP_MAX": 32768,
"SOC_TWAI_BRP_MAX": 16384,
"SOC_TWAI_BRP_MIN": 2,
"SOC_TWAI_CLK_SUPPORT_APB": true,
"SOC_TWAI_CONTROLLER_NUM": 1,
@@ -555,29 +650,33 @@
"SOC_TWAI_SUPPORTS_RX_STATUS": true,
"SOC_UART_BITRATE_MAX": 5000000,
"SOC_UART_FIFO_LEN": 128,
"SOC_UART_HP_NUM": 2,
"SOC_UART_NUM": 2,
"SOC_UART_HP_NUM": 3,
"SOC_UART_NUM": 3,
"SOC_UART_SUPPORTED": true,
"SOC_UART_SUPPORT_APB_CLK": true,
"SOC_UART_SUPPORT_REF_TICK": true,
"SOC_UART_SUPPORT_FSM_TX_WAIT_SEND": true,
"SOC_UART_SUPPORT_RTC_CLK": true,
"SOC_UART_SUPPORT_WAKEUP_INT": true,
"SOC_UART_SUPPORT_XTAL_CLK": true,
"SOC_ULP_FSM_SUPPORTED": true,
"SOC_ULP_HAS_ADC": true,
"SOC_ULP_SUPPORTED": true,
"SOC_USB_OTG_PERIPH_NUM": 1,
"SOC_USB_OTG_SUPPORTED": true,
"SOC_USB_SERIAL_JTAG_SUPPORTED": true,
"SOC_WDT_SUPPORTED": true,
"SOC_WIFI_CSI_SUPPORT": true,
"SOC_WIFI_FTM_SUPPORT": true,
"SOC_WIFI_GCMP_SUPPORT": true,
"SOC_WIFI_HW_TSF": true,
"SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH": 12,
"SOC_WIFI_MESH_SUPPORT": true,
"SOC_WIFI_NAN_SUPPORT": true,
"SOC_WIFI_SUPPORTED": true,
"SOC_WIFI_SUPPORT_VARIABLE_BEACON_WINDOW": true,
"SOC_WIFI_WAPI_SUPPORT": true,
"SOC_XTAL_SUPPORT_40M": true,
"SOC_XT_WDT_SUPPORTED": true,
"SPI_FLASH_AUTO_SUSPEND": false,
"SPI_FLASH_BROWNOUT_RESET": true,
"SPI_FLASH_BROWNOUT_RESET_XMC": true,
"SPI_FLASH_BYPASS_BLOCK_ERASE": false,
@@ -589,15 +688,24 @@
"SPI_FLASH_ENABLE_ENCRYPTED_READ_WRITE": true,
"SPI_FLASH_ERASE_YIELD_DURATION_MS": 20,
"SPI_FLASH_ERASE_YIELD_TICKS": 1,
"SPI_FLASH_HPM_AUTO": true,
"SPI_FLASH_HPM_DC_AUTO": true,
"SPI_FLASH_HPM_DC_DISABLE": false,
"SPI_FLASH_HPM_DIS": false,
"SPI_FLASH_HPM_ENA": false,
"SPI_FLASH_HPM_ON": true,
"SPI_FLASH_OVERRIDE_CHIP_DRIVER_LIST": false,
"SPI_FLASH_ROM_DRIVER_PATCH": true,
"SPI_FLASH_ROM_IMPL": false,
"SPI_FLASH_SIZE_OVERRIDE": false,
"SPI_FLASH_SUPPORT_BOYA_CHIP": true,
"SPI_FLASH_SUPPORT_GD_CHIP": true,
"SPI_FLASH_SUPPORT_ISSI_CHIP": true,
"SPI_FLASH_SUPPORT_MXIC_CHIP": true,
"SPI_FLASH_SUPPORT_MXIC_OPI_CHIP": true,
"SPI_FLASH_SUPPORT_TH_CHIP": true,
"SPI_FLASH_SUPPORT_WINBOND_CHIP": true,
"SPI_FLASH_SUSPEND_QVL_SUPPORTED": true,
"SPI_FLASH_VENDOR_BOYA_SUPPORTED": true,
"SPI_FLASH_VENDOR_GD_SUPPORTED": true,
"SPI_FLASH_VENDOR_ISSI_SUPPORTED": true,